2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev_driver.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
58 #include "nfpcore/nfp_cpp.h"
59 #include "nfpcore/nfp_nffw.h"
60 #include "nfpcore/nfp_hwinfo.h"
61 #include "nfpcore/nfp_mip.h"
62 #include "nfpcore/nfp_rtsym.h"
63 #include "nfpcore/nfp_nsp.h"
65 #include "nfp_net_pmd.h"
66 #include "nfp_net_logs.h"
67 #include "nfp_net_ctrl.h"
70 static void nfp_net_close(struct rte_eth_dev *dev);
71 static int nfp_net_configure(struct rte_eth_dev *dev);
72 static void nfp_net_dev_interrupt_handler(void *param);
73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
76 struct rte_eth_dev_info *dev_info);
77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
86 static void nfp_net_rx_queue_release(void *rxq);
87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_rxconf *rx_conf,
90 struct rte_mempool *mp);
91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
92 static void nfp_net_tx_queue_release(void *txq);
93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
94 uint16_t nb_desc, unsigned int socket_id,
95 const struct rte_eth_txconf *tx_conf);
96 static int nfp_net_start(struct rte_eth_dev *dev);
97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
98 struct rte_eth_stats *stats);
99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
100 static void nfp_net_stop(struct rte_eth_dev *dev);
101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
106 struct rte_eth_rss_conf *rss_conf);
107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
111 struct rte_eth_rss_conf *rss_conf);
112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
113 struct ether_addr *mac_addr);
115 /* The offset of the queue controller queues in the PCIe Target */
116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
118 /* Maximum value which can be added to a queue with one transaction */
119 #define NFP_QCP_MAX_ADD 0x7f
121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
122 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
126 NFP_QCP_READ_PTR = 0,
131 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
132 * @q: Base address for queue structure
133 * @ptr: Add to the Read or Write pointer
134 * @val: Value to add to the queue pointer
136 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
143 if (ptr == NFP_QCP_READ_PTR)
144 off = NFP_QCP_QUEUE_ADD_RPTR;
146 off = NFP_QCP_QUEUE_ADD_WPTR;
148 while (val > NFP_QCP_MAX_ADD) {
149 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
150 val -= NFP_QCP_MAX_ADD;
153 nn_writel(rte_cpu_to_le_32(val), q + off);
157 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
158 * @q: Base address for queue structure
159 * @ptr: Read or Write pointer
161 static inline uint32_t
162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
167 if (ptr == NFP_QCP_READ_PTR)
168 off = NFP_QCP_QUEUE_STS_LO;
170 off = NFP_QCP_QUEUE_STS_HI;
172 val = rte_cpu_to_le_32(nn_readl(q + off));
174 if (ptr == NFP_QCP_READ_PTR)
175 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
177 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
181 * Functions to read/write from/to Config BAR
182 * Performs any endian conversion necessary.
184 static inline uint8_t
185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
187 return nn_readb(hw->ctrl_bar + off);
191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
193 nn_writeb(val, hw->ctrl_bar + off);
196 static inline uint32_t
197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
205 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
208 static inline uint64_t
209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
211 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
217 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
225 if (rxq->rxbufs == NULL)
228 for (i = 0; i < rxq->rx_count; i++) {
229 if (rxq->rxbufs[i].mbuf) {
230 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
231 rxq->rxbufs[i].mbuf = NULL;
237 nfp_net_rx_queue_release(void *rx_queue)
239 struct nfp_net_rxq *rxq = rx_queue;
242 nfp_net_rx_queue_release_mbufs(rxq);
243 rte_free(rxq->rxbufs);
249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
251 nfp_net_rx_queue_release_mbufs(rxq);
257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
261 if (txq->txbufs == NULL)
264 for (i = 0; i < txq->tx_count; i++) {
265 if (txq->txbufs[i].mbuf) {
266 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
267 txq->txbufs[i].mbuf = NULL;
273 nfp_net_tx_queue_release(void *tx_queue)
275 struct nfp_net_txq *txq = tx_queue;
278 nfp_net_tx_queue_release_mbufs(txq);
279 rte_free(txq->txbufs);
285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
287 nfp_net_tx_queue_release_mbufs(txq);
293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
297 struct timespec wait;
299 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
302 if (hw->qcp_cfg == NULL)
303 rte_panic("Bad configuration queue pointer\n");
305 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
308 wait.tv_nsec = 1000000;
310 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
312 /* Poll update field, waiting for NFP to ack the config */
313 for (cnt = 0; ; cnt++) {
314 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
317 if (new & NFP_NET_CFG_UPDATE_ERR) {
318 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
321 if (cnt >= NFP_NET_POLL_TIMEOUT) {
322 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
323 " %dms", update, cnt);
324 rte_panic("Exiting\n");
326 nanosleep(&wait, 0); /* waiting for a 1ms */
328 PMD_DRV_LOG(DEBUG, "Ack DONE");
333 * Reconfigure the NIC
334 * @nn: device to reconfigure
335 * @ctrl: The value for the ctrl field in the BAR config
336 * @update: The value for the update field in the BAR config
338 * Write the update word to the BAR and ping the reconfig queue. Then poll
339 * until the firmware has acknowledged the update by zeroing the update word.
342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
346 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
349 rte_spinlock_lock(&hw->reconfig_lock);
351 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
352 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
356 err = __nfp_net_reconfig(hw, update);
358 rte_spinlock_unlock(&hw->reconfig_lock);
364 * Reconfig errors imply situations where they can be handled.
365 * Otherwise, rte_panic is called inside __nfp_net_reconfig
367 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
373 * Configure an Ethernet device. This function must be invoked first
374 * before any other function in the Ethernet API. This function can
375 * also be re-invoked when a device is in the stopped state.
378 nfp_net_configure(struct rte_eth_dev *dev)
380 struct rte_eth_conf *dev_conf;
381 struct rte_eth_rxmode *rxmode;
382 struct rte_eth_txmode *txmode;
383 struct nfp_net_hw *hw;
385 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
388 * A DPDK app sends info about how many queues to use and how
389 * those queues need to be configured. This is used by the
390 * DPDK core and it makes sure no more queues than those
391 * advertised by the driver are requested. This function is
392 * called after that internal process
395 PMD_INIT_LOG(DEBUG, "Configure");
397 dev_conf = &dev->data->dev_conf;
398 rxmode = &dev_conf->rxmode;
399 txmode = &dev_conf->txmode;
401 /* Checking TX mode */
402 if (txmode->mq_mode) {
403 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
407 /* Checking RX mode */
408 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
409 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
410 PMD_INIT_LOG(INFO, "RSS not supported");
414 /* Checking RX offloads */
415 if (!(rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP))
416 PMD_INIT_LOG(INFO, "HW does strip CRC. No configurable!");
422 nfp_net_enable_queues(struct rte_eth_dev *dev)
424 struct nfp_net_hw *hw;
425 uint64_t enabled_queues = 0;
428 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
430 /* Enabling the required TX queues in the device */
431 for (i = 0; i < dev->data->nb_tx_queues; i++)
432 enabled_queues |= (1 << i);
434 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
438 /* Enabling the required RX queues in the device */
439 for (i = 0; i < dev->data->nb_rx_queues; i++)
440 enabled_queues |= (1 << i);
442 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
446 nfp_net_disable_queues(struct rte_eth_dev *dev)
448 struct nfp_net_hw *hw;
449 uint32_t new_ctrl, update = 0;
451 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
453 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
454 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
456 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
457 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
458 NFP_NET_CFG_UPDATE_MSIX;
460 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
461 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
463 /* If an error when reconfig we avoid to change hw state */
464 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
471 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
475 for (i = 0; i < dev->data->nb_rx_queues; i++) {
476 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
483 nfp_net_params_setup(struct nfp_net_hw *hw)
485 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
486 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
490 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
492 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
495 #define ETH_ADDR_LEN 6
498 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
502 for (i = 0; i < ETH_ADDR_LEN; i++)
507 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
509 struct nfp_eth_table *nfp_eth_table;
511 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
513 * hw points to port0 private data. We need hw now pointing to
517 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
518 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
525 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
529 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
530 memcpy(&hw->mac_addr[0], &tmp, 4);
532 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
533 memcpy(&hw->mac_addr[4], &tmp, 2);
537 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
539 uint32_t mac0 = *(uint32_t *)mac;
542 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
545 mac1 = *(uint16_t *)mac;
546 nn_writew(rte_cpu_to_be_16(mac1),
547 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
551 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
553 struct nfp_net_hw *hw;
554 uint32_t update, ctrl;
556 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
557 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
558 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
559 PMD_INIT_LOG(INFO, "MAC address unable to change when"
564 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
565 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
568 /* Writing new MAC to the specific port BAR address */
569 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
571 /* Signal the NIC about the change */
572 update = NFP_NET_CFG_UPDATE_MACADDR;
573 ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
574 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
575 PMD_INIT_LOG(INFO, "MAC address update failed");
582 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
583 struct rte_intr_handle *intr_handle)
585 struct nfp_net_hw *hw;
588 if (!intr_handle->intr_vec) {
589 intr_handle->intr_vec =
590 rte_zmalloc("intr_vec",
591 dev->data->nb_rx_queues * sizeof(int), 0);
592 if (!intr_handle->intr_vec) {
593 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
594 " intr_vec", dev->data->nb_rx_queues);
599 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
601 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
602 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
603 /* UIO just supports one queue and no LSC*/
604 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
605 intr_handle->intr_vec[0] = 0;
607 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
608 for (i = 0; i < dev->data->nb_rx_queues; i++) {
610 * The first msix vector is reserved for non
613 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
614 intr_handle->intr_vec[i] = i + 1;
615 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
616 intr_handle->intr_vec[i]);
620 /* Avoiding TX interrupts */
621 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
626 nfp_check_offloads(struct rte_eth_dev *dev)
628 struct nfp_net_hw *hw;
629 struct rte_eth_conf *dev_conf;
630 struct rte_eth_rxmode *rxmode;
631 struct rte_eth_txmode *txmode;
634 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
636 dev_conf = &dev->data->dev_conf;
637 rxmode = &dev_conf->rxmode;
638 txmode = &dev_conf->txmode;
640 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
641 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
642 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
645 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
646 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
647 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
650 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
651 hw->mtu = rxmode->max_rx_pkt_len;
653 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
654 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
657 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
658 ctrl |= NFP_NET_CFG_CTRL_L2BC;
661 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
662 ctrl |= NFP_NET_CFG_CTRL_L2MC;
664 /* TX checksum offload */
665 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
666 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
667 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
668 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
671 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
672 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
673 ctrl |= NFP_NET_CFG_CTRL_LSO;
675 ctrl |= NFP_NET_CFG_CTRL_LSO2;
679 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
680 ctrl |= NFP_NET_CFG_CTRL_GATHER;
686 nfp_net_start(struct rte_eth_dev *dev)
688 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
689 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
690 uint32_t new_ctrl, update = 0;
691 struct nfp_net_hw *hw;
692 struct rte_eth_conf *dev_conf;
693 struct rte_eth_rxmode *rxmode;
694 uint32_t intr_vector;
697 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
699 PMD_INIT_LOG(DEBUG, "Start");
701 /* Disabling queues just in case... */
702 nfp_net_disable_queues(dev);
704 /* Enabling the required queues in the device */
705 nfp_net_enable_queues(dev);
707 /* check and configure queue intr-vector mapping */
708 if (dev->data->dev_conf.intr_conf.rxq != 0) {
709 if (hw->pf_multiport_enabled) {
710 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
711 "with NFP multiport PF");
714 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
716 * Better not to share LSC with RX interrupts.
717 * Unregistering LSC interrupt handler
719 rte_intr_callback_unregister(&pci_dev->intr_handle,
720 nfp_net_dev_interrupt_handler, (void *)dev);
722 if (dev->data->nb_rx_queues > 1) {
723 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
724 "supports 1 queue with UIO");
728 intr_vector = dev->data->nb_rx_queues;
729 if (rte_intr_efd_enable(intr_handle, intr_vector))
732 nfp_configure_rx_interrupt(dev, intr_handle);
733 update = NFP_NET_CFG_UPDATE_MSIX;
736 rte_intr_enable(intr_handle);
738 new_ctrl = nfp_check_offloads(dev);
740 /* Writing configuration parameters in the device */
741 nfp_net_params_setup(hw);
743 dev_conf = &dev->data->dev_conf;
744 rxmode = &dev_conf->rxmode;
746 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
747 nfp_net_rss_config_default(dev);
748 update |= NFP_NET_CFG_UPDATE_RSS;
749 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
753 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
755 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
757 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
758 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
760 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
761 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
765 * Allocating rte mbuffs for configured rx queues.
766 * This requires queues being enabled before
768 if (nfp_net_rx_freelist_setup(dev) < 0) {
774 /* Configure the physical port up */
775 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
783 * An error returned by this function should mean the app
784 * exiting and then the system releasing all the memory
785 * allocated even memory coming from hugepages.
787 * The device could be enabled at this point with some queues
788 * ready for getting packets. This is true if the call to
789 * nfp_net_rx_freelist_setup() succeeds for some queues but
790 * fails for subsequent queues.
792 * This should make the app exiting but better if we tell the
795 nfp_net_disable_queues(dev);
800 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
802 nfp_net_stop(struct rte_eth_dev *dev)
805 struct nfp_net_hw *hw;
807 PMD_INIT_LOG(DEBUG, "Stop");
809 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
811 nfp_net_disable_queues(dev);
814 for (i = 0; i < dev->data->nb_tx_queues; i++) {
815 nfp_net_reset_tx_queue(
816 (struct nfp_net_txq *)dev->data->tx_queues[i]);
819 for (i = 0; i < dev->data->nb_rx_queues; i++) {
820 nfp_net_reset_rx_queue(
821 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
825 /* Configure the physical port down */
826 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
829 /* Reset and stop device. The device can not be restarted. */
831 nfp_net_close(struct rte_eth_dev *dev)
833 struct nfp_net_hw *hw;
834 struct rte_pci_device *pci_dev;
837 PMD_INIT_LOG(DEBUG, "Close");
839 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
840 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
843 * We assume that the DPDK application is stopping all the
844 * threads/queues before calling the device close function.
847 nfp_net_disable_queues(dev);
850 for (i = 0; i < dev->data->nb_tx_queues; i++) {
851 nfp_net_reset_tx_queue(
852 (struct nfp_net_txq *)dev->data->tx_queues[i]);
855 for (i = 0; i < dev->data->nb_rx_queues; i++) {
856 nfp_net_reset_rx_queue(
857 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
860 rte_intr_disable(&pci_dev->intr_handle);
861 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
863 /* unregister callback func from eal lib */
864 rte_intr_callback_unregister(&pci_dev->intr_handle,
865 nfp_net_dev_interrupt_handler,
869 * The ixgbe PMD driver disables the pcie master on the
870 * device. The i40e does not...
875 nfp_net_promisc_enable(struct rte_eth_dev *dev)
877 uint32_t new_ctrl, update = 0;
878 struct nfp_net_hw *hw;
880 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
882 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
884 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
885 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
889 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
890 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
894 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
895 update = NFP_NET_CFG_UPDATE_GEN;
898 * DPDK sets promiscuous mode on just after this call assuming
899 * it can not fail ...
901 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
908 nfp_net_promisc_disable(struct rte_eth_dev *dev)
910 uint32_t new_ctrl, update = 0;
911 struct nfp_net_hw *hw;
913 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
915 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
916 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
920 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
921 update = NFP_NET_CFG_UPDATE_GEN;
924 * DPDK sets promiscuous mode off just before this call
925 * assuming it can not fail ...
927 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
934 * return 0 means link status changed, -1 means not changed
936 * Wait to complete is needed as it can take up to 9 seconds to get the Link
940 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
942 struct nfp_net_hw *hw;
943 struct rte_eth_link link;
944 uint32_t nn_link_status;
947 static const uint32_t ls_to_ethtool[] = {
948 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
949 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
950 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
951 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
952 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
953 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
954 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
955 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
958 PMD_DRV_LOG(DEBUG, "Link update");
960 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
962 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
964 memset(&link, 0, sizeof(struct rte_eth_link));
966 if (nn_link_status & NFP_NET_CFG_STS_LINK)
967 link.link_status = ETH_LINK_UP;
969 link.link_duplex = ETH_LINK_FULL_DUPLEX;
971 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
972 NFP_NET_CFG_STS_LINK_RATE_MASK;
974 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
975 link.link_speed = ETH_SPEED_NUM_NONE;
977 link.link_speed = ls_to_ethtool[nn_link_status];
979 ret = rte_eth_linkstatus_set(dev, &link);
981 if (link.link_status)
982 PMD_DRV_LOG(INFO, "NIC Link is Up");
984 PMD_DRV_LOG(INFO, "NIC Link is Down");
990 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
993 struct nfp_net_hw *hw;
994 struct rte_eth_stats nfp_dev_stats;
996 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
998 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1000 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1002 /* reading per RX ring stats */
1003 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1004 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1007 nfp_dev_stats.q_ipackets[i] =
1008 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1010 nfp_dev_stats.q_ipackets[i] -=
1011 hw->eth_stats_base.q_ipackets[i];
1013 nfp_dev_stats.q_ibytes[i] =
1014 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1016 nfp_dev_stats.q_ibytes[i] -=
1017 hw->eth_stats_base.q_ibytes[i];
1020 /* reading per TX ring stats */
1021 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1022 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1025 nfp_dev_stats.q_opackets[i] =
1026 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1028 nfp_dev_stats.q_opackets[i] -=
1029 hw->eth_stats_base.q_opackets[i];
1031 nfp_dev_stats.q_obytes[i] =
1032 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1034 nfp_dev_stats.q_obytes[i] -=
1035 hw->eth_stats_base.q_obytes[i];
1038 nfp_dev_stats.ipackets =
1039 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1041 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1043 nfp_dev_stats.ibytes =
1044 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1046 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1048 nfp_dev_stats.opackets =
1049 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1051 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1053 nfp_dev_stats.obytes =
1054 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1056 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1058 /* reading general device stats */
1059 nfp_dev_stats.ierrors =
1060 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1062 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1064 nfp_dev_stats.oerrors =
1065 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1067 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1069 /* RX ring mbuf allocation failures */
1070 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1072 nfp_dev_stats.imissed =
1073 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1075 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1078 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1085 nfp_net_stats_reset(struct rte_eth_dev *dev)
1088 struct nfp_net_hw *hw;
1090 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093 * hw->eth_stats_base records the per counter starting point.
1094 * Lets update it now
1097 /* reading per RX ring stats */
1098 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1099 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1102 hw->eth_stats_base.q_ipackets[i] =
1103 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1105 hw->eth_stats_base.q_ibytes[i] =
1106 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1109 /* reading per TX ring stats */
1110 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1111 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1114 hw->eth_stats_base.q_opackets[i] =
1115 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1117 hw->eth_stats_base.q_obytes[i] =
1118 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1121 hw->eth_stats_base.ipackets =
1122 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1124 hw->eth_stats_base.ibytes =
1125 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1127 hw->eth_stats_base.opackets =
1128 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1130 hw->eth_stats_base.obytes =
1131 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1133 /* reading general device stats */
1134 hw->eth_stats_base.ierrors =
1135 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1137 hw->eth_stats_base.oerrors =
1138 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1140 /* RX ring mbuf allocation failures */
1141 dev->data->rx_mbuf_alloc_failed = 0;
1143 hw->eth_stats_base.imissed =
1144 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1148 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1150 struct nfp_net_hw *hw;
1152 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1155 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1156 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1157 dev_info->max_rx_pktlen = hw->max_mtu;
1158 /* Next should change when PF support is implemented */
1159 dev_info->max_mac_addrs = 1;
1161 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1162 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1164 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1165 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1166 DEV_RX_OFFLOAD_UDP_CKSUM |
1167 DEV_RX_OFFLOAD_TCP_CKSUM;
1169 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1171 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1172 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1174 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1175 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1176 DEV_TX_OFFLOAD_UDP_CKSUM |
1177 DEV_TX_OFFLOAD_TCP_CKSUM;
1179 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1180 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1182 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1183 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1185 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1187 .pthresh = DEFAULT_RX_PTHRESH,
1188 .hthresh = DEFAULT_RX_HTHRESH,
1189 .wthresh = DEFAULT_RX_WTHRESH,
1191 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1195 dev_info->default_txconf = (struct rte_eth_txconf) {
1197 .pthresh = DEFAULT_TX_PTHRESH,
1198 .hthresh = DEFAULT_TX_HTHRESH,
1199 .wthresh = DEFAULT_TX_WTHRESH,
1201 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1202 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1205 dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1206 ETH_RSS_NONFRAG_IPV4_UDP |
1207 ETH_RSS_NONFRAG_IPV6_TCP |
1208 ETH_RSS_NONFRAG_IPV6_UDP;
1210 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1211 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1213 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1214 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1215 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1218 static const uint32_t *
1219 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1221 static const uint32_t ptypes[] = {
1222 /* refers to nfp_net_set_hash() */
1223 RTE_PTYPE_INNER_L3_IPV4,
1224 RTE_PTYPE_INNER_L3_IPV6,
1225 RTE_PTYPE_INNER_L3_IPV6_EXT,
1226 RTE_PTYPE_INNER_L4_MASK,
1230 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1236 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1238 struct nfp_net_rxq *rxq;
1239 struct nfp_net_rx_desc *rxds;
1243 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1250 * Other PMDs are just checking the DD bit in intervals of 4
1251 * descriptors and counting all four if the first has the DD
1252 * bit on. Of course, this is not accurate but can be good for
1253 * performance. But ideally that should be done in descriptors
1254 * chunks belonging to the same cache line
1257 while (count < rxq->rx_count) {
1258 rxds = &rxq->rxds[idx];
1259 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1266 if ((idx) == rxq->rx_count)
1274 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1276 struct rte_pci_device *pci_dev;
1277 struct nfp_net_hw *hw;
1280 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1281 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1283 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1286 /* Make sure all updates are written before un-masking */
1288 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1289 NFP_NET_CFG_ICR_UNMASKED);
1294 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1296 struct rte_pci_device *pci_dev;
1297 struct nfp_net_hw *hw;
1300 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1303 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1306 /* Make sure all updates are written before un-masking */
1308 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1313 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1315 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1316 struct rte_eth_link link;
1318 rte_eth_linkstatus_get(dev, &link);
1319 if (link.link_status)
1320 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1321 dev->data->port_id, link.link_speed,
1322 link.link_duplex == ETH_LINK_FULL_DUPLEX
1323 ? "full-duplex" : "half-duplex");
1325 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1326 dev->data->port_id);
1328 PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1329 pci_dev->addr.domain, pci_dev->addr.bus,
1330 pci_dev->addr.devid, pci_dev->addr.function);
1333 /* Interrupt configuration and handling */
1336 * nfp_net_irq_unmask - Unmask an interrupt
1338 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1339 * clear the ICR for the entry.
1342 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1344 struct nfp_net_hw *hw;
1345 struct rte_pci_device *pci_dev;
1347 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1350 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1351 /* If MSI-X auto-masking is used, clear the entry */
1353 rte_intr_enable(&pci_dev->intr_handle);
1355 /* Make sure all updates are written before un-masking */
1357 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1358 NFP_NET_CFG_ICR_UNMASKED);
1363 nfp_net_dev_interrupt_handler(void *param)
1366 struct rte_eth_link link;
1367 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1369 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1371 rte_eth_linkstatus_get(dev, &link);
1373 nfp_net_link_update(dev, 0);
1376 if (!link.link_status) {
1377 /* handle it 1 sec later, wait it being stable */
1378 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1379 /* likely to down */
1381 /* handle it 4 sec later, wait it being stable */
1382 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1385 if (rte_eal_alarm_set(timeout * 1000,
1386 nfp_net_dev_interrupt_delayed_handler,
1388 PMD_INIT_LOG(ERR, "Error setting alarm");
1390 nfp_net_irq_unmask(dev);
1395 * Interrupt handler which shall be registered for alarm callback for delayed
1396 * handling specific interrupt to wait for the stable nic state. As the NIC
1397 * interrupt state is not stable for nfp after link is just down, it needs
1398 * to wait 4 seconds to get the stable status.
1400 * @param handle Pointer to interrupt handle.
1401 * @param param The address of parameter (struct rte_eth_dev *)
1406 nfp_net_dev_interrupt_delayed_handler(void *param)
1408 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1410 nfp_net_link_update(dev, 0);
1411 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1413 nfp_net_dev_link_status_print(dev);
1416 nfp_net_irq_unmask(dev);
1420 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1422 struct nfp_net_hw *hw;
1424 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 /* check that mtu is within the allowed range */
1427 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1430 /* mtu setting is forbidden if port is started */
1431 if (dev->data->dev_started) {
1432 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1433 dev->data->port_id);
1437 /* switch to jumbo mode if needed */
1438 if ((uint32_t)mtu > ETHER_MAX_LEN)
1439 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1441 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1443 /* update max frame size */
1444 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1446 /* writing to configuration space */
1447 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1455 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1456 uint16_t queue_idx, uint16_t nb_desc,
1457 unsigned int socket_id,
1458 const struct rte_eth_rxconf *rx_conf,
1459 struct rte_mempool *mp)
1461 const struct rte_memzone *tz;
1462 struct nfp_net_rxq *rxq;
1463 struct nfp_net_hw *hw;
1465 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467 PMD_INIT_FUNC_TRACE();
1469 /* Validating number of descriptors */
1470 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1471 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1472 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1473 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1478 * Free memory prior to re-allocation if needed. This is the case after
1479 * calling nfp_net_stop
1481 if (dev->data->rx_queues[queue_idx]) {
1482 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1483 dev->data->rx_queues[queue_idx] = NULL;
1486 /* Allocating rx queue data structure */
1487 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1488 RTE_CACHE_LINE_SIZE, socket_id);
1492 /* Hw queues mapping based on firmware confifguration */
1493 rxq->qidx = queue_idx;
1494 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1495 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1496 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1497 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1500 * Tracking mbuf size for detecting a potential mbuf overflow due to
1504 rxq->mbuf_size = rxq->mem_pool->elt_size;
1505 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1506 hw->flbufsz = rxq->mbuf_size;
1508 rxq->rx_count = nb_desc;
1509 rxq->port_id = dev->data->port_id;
1510 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1511 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1513 rxq->drop_en = rx_conf->rx_drop_en;
1516 * Allocate RX ring hardware descriptors. A memzone large enough to
1517 * handle the maximum ring size is allocated in order to allow for
1518 * resizing in later calls to the queue setup function.
1520 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1521 sizeof(struct nfp_net_rx_desc) *
1522 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1526 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1527 nfp_net_rx_queue_release(rxq);
1531 /* Saving physical and virtual addresses for the RX ring */
1532 rxq->dma = (uint64_t)tz->iova;
1533 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1535 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1536 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1537 sizeof(*rxq->rxbufs) * nb_desc,
1538 RTE_CACHE_LINE_SIZE, socket_id);
1539 if (rxq->rxbufs == NULL) {
1540 nfp_net_rx_queue_release(rxq);
1544 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1545 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1547 nfp_net_reset_rx_queue(rxq);
1549 dev->data->rx_queues[queue_idx] = rxq;
1553 * Telling the HW about the physical address of the RX ring and number
1554 * of descriptors in log2 format
1556 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1557 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1563 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1565 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1569 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1572 for (i = 0; i < rxq->rx_count; i++) {
1573 struct nfp_net_rx_desc *rxd;
1574 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1577 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1578 (unsigned)rxq->qidx);
1582 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1584 rxd = &rxq->rxds[i];
1586 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1587 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1589 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1592 /* Make sure all writes are flushed before telling the hardware */
1595 /* Not advertising the whole ring as the firmware gets confused if so */
1596 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1599 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1605 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1606 uint16_t nb_desc, unsigned int socket_id,
1607 const struct rte_eth_txconf *tx_conf)
1609 const struct rte_memzone *tz;
1610 struct nfp_net_txq *txq;
1611 uint16_t tx_free_thresh;
1612 struct nfp_net_hw *hw;
1614 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616 PMD_INIT_FUNC_TRACE();
1618 /* Validating number of descriptors */
1619 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1620 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1621 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1622 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1626 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1627 tx_conf->tx_free_thresh :
1628 DEFAULT_TX_FREE_THRESH);
1630 if (tx_free_thresh > (nb_desc)) {
1632 "tx_free_thresh must be less than the number of TX "
1633 "descriptors. (tx_free_thresh=%u port=%d "
1634 "queue=%d)", (unsigned int)tx_free_thresh,
1635 dev->data->port_id, (int)queue_idx);
1640 * Free memory prior to re-allocation if needed. This is the case after
1641 * calling nfp_net_stop
1643 if (dev->data->tx_queues[queue_idx]) {
1644 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1646 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1647 dev->data->tx_queues[queue_idx] = NULL;
1650 /* Allocating tx queue data structure */
1651 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1652 RTE_CACHE_LINE_SIZE, socket_id);
1654 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1659 * Allocate TX ring hardware descriptors. A memzone large enough to
1660 * handle the maximum ring size is allocated in order to allow for
1661 * resizing in later calls to the queue setup function.
1663 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1664 sizeof(struct nfp_net_tx_desc) *
1665 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1668 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1669 nfp_net_tx_queue_release(txq);
1673 txq->tx_count = nb_desc;
1674 txq->tx_free_thresh = tx_free_thresh;
1675 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1676 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1677 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1679 /* queue mapping based on firmware configuration */
1680 txq->qidx = queue_idx;
1681 txq->tx_qcidx = queue_idx * hw->stride_tx;
1682 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1684 txq->port_id = dev->data->port_id;
1686 /* Saving physical and virtual addresses for the TX ring */
1687 txq->dma = (uint64_t)tz->iova;
1688 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1690 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1691 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1692 sizeof(*txq->txbufs) * nb_desc,
1693 RTE_CACHE_LINE_SIZE, socket_id);
1694 if (txq->txbufs == NULL) {
1695 nfp_net_tx_queue_release(txq);
1698 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1699 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1701 nfp_net_reset_tx_queue(txq);
1703 dev->data->tx_queues[queue_idx] = txq;
1707 * Telling the HW about the physical address of the TX ring and number
1708 * of descriptors in log2 format
1710 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1711 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1716 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1718 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1719 struct rte_mbuf *mb)
1722 struct nfp_net_hw *hw = txq->hw;
1724 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1727 ol_flags = mb->ol_flags;
1729 if (!(ol_flags & PKT_TX_TCP_SEG))
1732 txd->l3_offset = mb->l2_len;
1733 txd->l4_offset = mb->l2_len + mb->l3_len;
1734 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1735 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1736 txd->flags = PCIE_DESC_TX_LSO;
1743 txd->lso_hdrlen = 0;
1747 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1749 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1750 struct rte_mbuf *mb)
1753 struct nfp_net_hw *hw = txq->hw;
1755 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1758 ol_flags = mb->ol_flags;
1760 /* IPv6 does not need checksum */
1761 if (ol_flags & PKT_TX_IP_CKSUM)
1762 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1764 switch (ol_flags & PKT_TX_L4_MASK) {
1765 case PKT_TX_UDP_CKSUM:
1766 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1768 case PKT_TX_TCP_CKSUM:
1769 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1773 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1774 txd->flags |= PCIE_DESC_TX_CSUM;
1777 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1779 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1780 struct rte_mbuf *mb)
1782 struct nfp_net_hw *hw = rxq->hw;
1784 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1787 /* If IPv4 and IP checksum error, fail */
1788 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1789 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1790 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1792 /* If neither UDP nor TCP return */
1793 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1794 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1797 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1798 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1799 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1801 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1802 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1803 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1806 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1807 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1809 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1812 * nfp_net_set_hash - Set mbuf hash data
1814 * The RSS hash and hash-type are pre-pended to the packet data.
1815 * Extract and decode it and set the mbuf fields.
1818 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1819 struct rte_mbuf *mbuf)
1821 struct nfp_net_hw *hw = rxq->hw;
1822 uint8_t *meta_offset;
1825 uint32_t hash_type = 0;
1827 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1830 /* this is true for new firmwares */
1831 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1832 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1833 NFP_DESC_META_LEN(rxd))) {
1836 * <---- 32 bit ----->
1841 * ====================
1844 * Field type word contains up to 8 4bit field types
1845 * A 4bit field type refers to a data field word
1846 * A data field word can have several 4bit field types
1848 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1849 meta_offset -= NFP_DESC_META_LEN(rxd);
1850 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1852 /* NFP PMD just supports metadata for hashing */
1853 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1854 case NFP_NET_META_HASH:
1855 /* next field type is about the hash type */
1856 meta_info >>= NFP_NET_META_FIELD_SIZE;
1857 /* hash value is in the data field */
1858 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1859 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1862 /* Unsupported metadata can be a performance issue */
1866 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1869 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1870 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1873 mbuf->hash.rss = hash;
1874 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1876 switch (hash_type) {
1877 case NFP_NET_RSS_IPV4:
1878 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1880 case NFP_NET_RSS_IPV6:
1881 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1883 case NFP_NET_RSS_IPV6_EX:
1884 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1887 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1892 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1894 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1897 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1902 * There are some decissions to take:
1903 * 1) How to check DD RX descriptors bit
1904 * 2) How and when to allocate new mbufs
1906 * Current implementation checks just one single DD bit each loop. As each
1907 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1908 * a single cache line instead. Tests with this change have not shown any
1909 * performance improvement but it requires further investigation. For example,
1910 * depending on which descriptor is next, the number of descriptors could be
1911 * less than 8 for just checking those in the same cache line. This implies
1912 * extra work which could be counterproductive by itself. Indeed, last firmware
1913 * changes are just doing this: writing several descriptors with the DD bit
1914 * for saving PCIe bandwidth and DMA operations from the NFP.
1916 * Mbuf allocation is done when a new packet is received. Then the descriptor
1917 * is automatically linked with the new mbuf and the old one is given to the
1918 * user. The main drawback with this design is mbuf allocation is heavier than
1919 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1920 * cache point of view it does not seem allocating the mbuf early on as we are
1921 * doing now have any benefit at all. Again, tests with this change have not
1922 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1923 * so looking at the implications of this type of allocation should be studied
1928 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1930 struct nfp_net_rxq *rxq;
1931 struct nfp_net_rx_desc *rxds;
1932 struct nfp_net_rx_buff *rxb;
1933 struct nfp_net_hw *hw;
1934 struct rte_mbuf *mb;
1935 struct rte_mbuf *new_mb;
1941 if (unlikely(rxq == NULL)) {
1943 * DPDK just checks the queue is lower than max queues
1944 * enabled. But the queue needs to be configured
1946 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1954 while (avail < nb_pkts) {
1955 rxb = &rxq->rxbufs[rxq->rd_p];
1956 if (unlikely(rxb == NULL)) {
1957 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1961 rxds = &rxq->rxds[rxq->rd_p];
1962 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1966 * Memory barrier to ensure that we won't do other
1967 * reads before the DD bit.
1972 * We got a packet. Let's alloc a new mbuff for refilling the
1973 * free descriptor ring as soon as possible
1975 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1976 if (unlikely(new_mb == NULL)) {
1977 RTE_LOG_DP(DEBUG, PMD,
1978 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1979 rxq->port_id, (unsigned int)rxq->qidx);
1980 nfp_net_mbuf_alloc_failed(rxq);
1987 * Grab the mbuff and refill the descriptor with the
1988 * previously allocated mbuff
1993 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
1994 rxds->rxd.data_len, rxq->mbuf_size);
1996 /* Size of this segment */
1997 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1998 /* Size of the whole packet. We just support 1 segment */
1999 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2001 if (unlikely((mb->data_len + hw->rx_offset) >
2004 * This should not happen and the user has the
2005 * responsibility of avoiding it. But we have
2006 * to give some info about the error
2008 RTE_LOG_DP(ERR, PMD,
2009 "mbuf overflow likely due to the RX offset.\n"
2010 "\t\tYour mbuf size should have extra space for"
2011 " RX offset=%u bytes.\n"
2012 "\t\tCurrently you just have %u bytes available"
2013 " but the received packet is %u bytes long",
2015 rxq->mbuf_size - hw->rx_offset,
2020 /* Filling the received mbuff with packet info */
2022 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2024 mb->data_off = RTE_PKTMBUF_HEADROOM +
2025 NFP_DESC_META_LEN(rxds);
2027 /* No scatter mode supported */
2031 mb->port = rxq->port_id;
2033 /* Checking the RSS flag */
2034 nfp_net_set_hash(rxq, rxds, mb);
2036 /* Checking the checksum flag */
2037 nfp_net_rx_cksum(rxq, rxds, mb);
2039 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2040 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2041 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2042 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2045 /* Adding the mbuff to the mbuff array passed by the app */
2046 rx_pkts[avail++] = mb;
2048 /* Now resetting and updating the descriptor */
2051 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2053 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2054 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2057 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2064 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2065 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2067 nb_hold += rxq->nb_rx_hold;
2070 * FL descriptors needs to be written before incrementing the
2071 * FL queue WR pointer
2074 if (nb_hold > rxq->rx_free_thresh) {
2075 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2076 rxq->port_id, (unsigned int)rxq->qidx,
2077 (unsigned)nb_hold, (unsigned)avail);
2078 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2081 rxq->nb_rx_hold = nb_hold;
2087 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2089 * @txq: TX queue to work with
2090 * Returns number of descriptors freed
2093 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2098 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2099 " status", txq->qidx);
2101 /* Work out how many packets have been sent */
2102 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2104 if (qcp_rd_p == txq->rd_p) {
2105 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2106 "packets (%u, %u)", txq->qidx,
2107 qcp_rd_p, txq->rd_p);
2111 if (qcp_rd_p > txq->rd_p)
2112 todo = qcp_rd_p - txq->rd_p;
2114 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2116 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2117 qcp_rd_p, txq->rd_p, txq->rd_p);
2123 if (unlikely(txq->rd_p >= txq->tx_count))
2124 txq->rd_p -= txq->tx_count;
2129 /* Leaving always free descriptors for avoiding wrapping confusion */
2131 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2133 if (txq->wr_p >= txq->rd_p)
2134 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2136 return txq->rd_p - txq->wr_p - 8;
2140 * nfp_net_txq_full - Check if the TX queue free descriptors
2141 * is below tx_free_threshold
2143 * @txq: TX queue to check
2145 * This function uses the host copy* of read/write pointers
2148 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2150 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2154 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2156 struct nfp_net_txq *txq;
2157 struct nfp_net_hw *hw;
2158 struct nfp_net_tx_desc *txds, txd;
2159 struct rte_mbuf *pkt;
2161 int pkt_size, dma_size;
2162 uint16_t free_descs, issued_descs;
2163 struct rte_mbuf **lmbuf;
2168 txds = &txq->txds[txq->wr_p];
2170 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2171 txq->qidx, txq->wr_p, nb_pkts);
2173 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2174 nfp_net_tx_free_bufs(txq);
2176 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2177 if (unlikely(free_descs == 0))
2184 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2185 txq->qidx, nb_pkts);
2186 /* Sending packets */
2187 while ((i < nb_pkts) && free_descs) {
2188 /* Grabbing the mbuf linked to the current descriptor */
2189 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2190 /* Warming the cache for releasing the mbuf later on */
2191 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2193 pkt = *(tx_pkts + i);
2195 if (unlikely((pkt->nb_segs > 1) &&
2196 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2197 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2198 rte_panic("Multisegment packet unsupported\n");
2201 /* Checking if we have enough descriptors */
2202 if (unlikely(pkt->nb_segs > free_descs))
2206 * Checksum and VLAN flags just in the first descriptor for a
2207 * multisegment packet, but TSO info needs to be in all of them.
2209 txd.data_len = pkt->pkt_len;
2210 nfp_net_tx_tso(txq, &txd, pkt);
2211 nfp_net_tx_cksum(txq, &txd, pkt);
2213 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2214 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2215 txd.flags |= PCIE_DESC_TX_VLAN;
2216 txd.vlan = pkt->vlan_tci;
2220 * mbuf data_len is the data in one segment and pkt_len data
2221 * in the whole packet. When the packet is just one segment,
2222 * then data_len = pkt_len
2224 pkt_size = pkt->pkt_len;
2227 /* Copying TSO, VLAN and cksum info */
2230 /* Releasing mbuf used by this descriptor previously*/
2232 rte_pktmbuf_free_seg(*lmbuf);
2235 * Linking mbuf with descriptor for being released
2236 * next time descriptor is used
2240 dma_size = pkt->data_len;
2241 dma_addr = rte_mbuf_data_iova(pkt);
2242 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2243 "%" PRIx64 "", dma_addr);
2245 /* Filling descriptors fields */
2246 txds->dma_len = dma_size;
2247 txds->data_len = txd.data_len;
2248 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2249 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2250 ASSERT(free_descs > 0);
2254 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2257 pkt_size -= dma_size;
2260 txds->offset_eop |= PCIE_DESC_TX_EOP;
2262 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2265 /* Referencing next free TX descriptor */
2266 txds = &txq->txds[txq->wr_p];
2267 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2274 /* Increment write pointers. Force memory write before we let HW know */
2276 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2282 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2284 uint32_t new_ctrl, update;
2285 struct nfp_net_hw *hw;
2288 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2292 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2293 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2294 " ETH_VLAN_EXTEND_OFFLOAD");
2296 /* Enable vlan strip if it is not configured yet */
2297 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2298 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2299 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2301 /* Disable vlan strip just if it is configured */
2302 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2303 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2304 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2309 update = NFP_NET_CFG_UPDATE_GEN;
2311 ret = nfp_net_reconfig(hw, new_ctrl, update);
2313 hw->ctrl = new_ctrl;
2319 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2320 struct rte_eth_rss_reta_entry64 *reta_conf,
2323 uint32_t reta, mask;
2326 struct nfp_net_hw *hw =
2327 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2329 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2330 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2331 "(%d) doesn't match the number hardware can supported "
2332 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2337 * Update Redirection Table. There are 128 8bit-entries which can be
2338 * manage as 32 32bit-entries
2340 for (i = 0; i < reta_size; i += 4) {
2341 /* Handling 4 RSS entries per loop */
2342 idx = i / RTE_RETA_GROUP_SIZE;
2343 shift = i % RTE_RETA_GROUP_SIZE;
2344 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2350 /* If all 4 entries were set, don't need read RETA register */
2352 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2354 for (j = 0; j < 4; j++) {
2355 if (!(mask & (0x1 << j)))
2358 /* Clearing the entry bits */
2359 reta &= ~(0xFF << (8 * j));
2360 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2362 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2368 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2370 nfp_net_reta_update(struct rte_eth_dev *dev,
2371 struct rte_eth_rss_reta_entry64 *reta_conf,
2374 struct nfp_net_hw *hw =
2375 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2382 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2386 update = NFP_NET_CFG_UPDATE_RSS;
2388 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2394 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2396 nfp_net_reta_query(struct rte_eth_dev *dev,
2397 struct rte_eth_rss_reta_entry64 *reta_conf,
2403 struct nfp_net_hw *hw;
2405 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2410 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2411 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2412 "(%d) doesn't match the number hardware can supported "
2413 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2418 * Reading Redirection Table. There are 128 8bit-entries which can be
2419 * manage as 32 32bit-entries
2421 for (i = 0; i < reta_size; i += 4) {
2422 /* Handling 4 RSS entries per loop */
2423 idx = i / RTE_RETA_GROUP_SIZE;
2424 shift = i % RTE_RETA_GROUP_SIZE;
2425 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2430 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2432 for (j = 0; j < 4; j++) {
2433 if (!(mask & (0x1 << j)))
2435 reta_conf->reta[shift + j] =
2436 (uint8_t)((reta >> (8 * j)) & 0xF);
2443 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2444 struct rte_eth_rss_conf *rss_conf)
2446 struct nfp_net_hw *hw;
2448 uint32_t cfg_rss_ctrl = 0;
2452 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454 /* Writing the key byte a byte */
2455 for (i = 0; i < rss_conf->rss_key_len; i++) {
2456 memcpy(&key, &rss_conf->rss_key[i], 1);
2457 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2460 rss_hf = rss_conf->rss_hf;
2462 if (rss_hf & ETH_RSS_IPV4)
2463 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2464 NFP_NET_CFG_RSS_IPV4_TCP |
2465 NFP_NET_CFG_RSS_IPV4_UDP;
2467 if (rss_hf & ETH_RSS_IPV6)
2468 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2469 NFP_NET_CFG_RSS_IPV6_TCP |
2470 NFP_NET_CFG_RSS_IPV6_UDP;
2472 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2473 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2475 /* configuring where to apply the RSS hash */
2476 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2478 /* Writing the key size */
2479 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2485 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2486 struct rte_eth_rss_conf *rss_conf)
2490 struct nfp_net_hw *hw;
2492 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494 rss_hf = rss_conf->rss_hf;
2496 /* Checking if RSS is enabled */
2497 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2498 if (rss_hf != 0) { /* Enable RSS? */
2499 PMD_DRV_LOG(ERR, "RSS unsupported");
2502 return 0; /* Nothing to do */
2505 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2506 PMD_DRV_LOG(ERR, "hash key too long");
2510 nfp_net_rss_hash_write(dev, rss_conf);
2512 update = NFP_NET_CFG_UPDATE_RSS;
2514 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2521 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2522 struct rte_eth_rss_conf *rss_conf)
2525 uint32_t cfg_rss_ctrl;
2528 struct nfp_net_hw *hw;
2530 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2532 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2535 rss_hf = rss_conf->rss_hf;
2536 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2538 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2539 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2541 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2542 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2544 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2545 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2547 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2548 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2550 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2551 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2553 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2554 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2556 /* Reading the key size */
2557 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2559 /* Reading the key byte a byte */
2560 for (i = 0; i < rss_conf->rss_key_len; i++) {
2561 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2562 memcpy(&rss_conf->rss_key[i], &key, 1);
2569 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2571 struct rte_eth_conf *dev_conf;
2572 struct rte_eth_rss_conf rss_conf;
2573 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2574 uint16_t rx_queues = dev->data->nb_rx_queues;
2578 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2581 nfp_reta_conf[0].mask = ~0x0;
2582 nfp_reta_conf[1].mask = ~0x0;
2585 for (i = 0; i < 0x40; i += 8) {
2586 for (j = i; j < (i + 8); j++) {
2587 nfp_reta_conf[0].reta[j] = queue;
2588 nfp_reta_conf[1].reta[j] = queue++;
2592 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2596 dev_conf = &dev->data->dev_conf;
2598 PMD_DRV_LOG(INFO, "wrong rss conf");
2601 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2603 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2609 /* Initialise and register driver with DPDK Application */
2610 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2611 .dev_configure = nfp_net_configure,
2612 .dev_start = nfp_net_start,
2613 .dev_stop = nfp_net_stop,
2614 .dev_close = nfp_net_close,
2615 .promiscuous_enable = nfp_net_promisc_enable,
2616 .promiscuous_disable = nfp_net_promisc_disable,
2617 .link_update = nfp_net_link_update,
2618 .stats_get = nfp_net_stats_get,
2619 .stats_reset = nfp_net_stats_reset,
2620 .dev_infos_get = nfp_net_infos_get,
2621 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2622 .mtu_set = nfp_net_dev_mtu_set,
2623 .mac_addr_set = nfp_set_mac_addr,
2624 .vlan_offload_set = nfp_net_vlan_offload_set,
2625 .reta_update = nfp_net_reta_update,
2626 .reta_query = nfp_net_reta_query,
2627 .rss_hash_update = nfp_net_rss_hash_update,
2628 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2629 .rx_queue_setup = nfp_net_rx_queue_setup,
2630 .rx_queue_release = nfp_net_rx_queue_release,
2631 .rx_queue_count = nfp_net_rx_queue_count,
2632 .tx_queue_setup = nfp_net_tx_queue_setup,
2633 .tx_queue_release = nfp_net_tx_queue_release,
2634 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2635 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2639 * All eth_dev created got its private data, but before nfp_net_init, that
2640 * private data is referencing private data for all the PF ports. This is due
2641 * to how the vNIC bars are mapped based on first port, so all ports need info
2642 * about port 0 private data. Inside nfp_net_init the private data pointer is
2643 * changed to the right address for each port once the bars have been mapped.
2645 * This functions helps to find out which port and therefore which offset
2646 * inside the private data array to use.
2649 get_pf_port_number(char *name)
2651 char *pf_str = name;
2654 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2659 * This should not happen at all and it would mean major
2660 * implementation fault.
2662 rte_panic("nfp_net: problem with pf device name\n");
2664 /* Expecting _portX with X within [0,7] */
2667 return (int)strtol(pf_str, NULL, 10);
2671 nfp_net_init(struct rte_eth_dev *eth_dev)
2673 struct rte_pci_device *pci_dev;
2674 struct nfp_net_hw *hw, *hwport0;
2676 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2682 PMD_INIT_FUNC_TRACE();
2684 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2686 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2687 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2688 port = get_pf_port_number(eth_dev->data->name);
2689 if (port < 0 || port > 7) {
2690 PMD_DRV_LOG(ERR, "Port value is wrong");
2694 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2696 /* This points to port 0 private data */
2697 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2699 /* This points to the specific port private data */
2700 hw = &hwport0[port];
2702 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2706 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2707 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2708 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2710 /* For secondary processes, the primary has done all the work */
2711 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2714 rte_eth_copy_pci_info(eth_dev, pci_dev);
2716 hw->device_id = pci_dev->id.device_id;
2717 hw->vendor_id = pci_dev->id.vendor_id;
2718 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2719 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2721 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2722 pci_dev->id.vendor_id, pci_dev->id.device_id,
2723 pci_dev->addr.domain, pci_dev->addr.bus,
2724 pci_dev->addr.devid, pci_dev->addr.function);
2726 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2727 if (hw->ctrl_bar == NULL) {
2729 "hw->ctrl_bar is NULL. BAR0 not configured");
2733 if (hw->is_pf && port == 0) {
2734 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2735 hw->total_ports * 32768,
2737 if (!hw->ctrl_bar) {
2738 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2742 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2746 if (!hwport0->ctrl_bar)
2749 /* address based on port0 offset */
2750 hw->ctrl_bar = hwport0->ctrl_bar +
2751 (port * NFP_PF_CSR_SLICE_SIZE);
2754 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2756 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2757 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2759 /* Work out where in the BAR the queues start. */
2760 switch (pci_dev->id.device_id) {
2761 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2762 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2763 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2764 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2765 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2766 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2767 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2770 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2772 goto dev_err_ctrl_map;
2775 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2776 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2778 if (hw->is_pf && port == 0) {
2779 /* configure access to tx/rx vNIC BARs */
2780 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2782 NFP_QCP_QUEUE_AREA_SZ,
2783 &hw->hwqueues_area);
2785 if (!hwport0->hw_queues) {
2786 printf("nfp_rtsym_map fails for net.qc");
2788 goto dev_err_ctrl_map;
2791 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2792 hwport0->hw_queues);
2796 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2797 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2798 eth_dev->data->dev_private = hw;
2800 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2802 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2806 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2807 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2809 nfp_net_cfg_queue_setup(hw);
2811 /* Get some of the read-only fields from the config BAR */
2812 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2813 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2814 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2815 hw->mtu = ETHER_MTU;
2817 /* VLAN insertion is incompatible with LSOv2 */
2818 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2819 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2821 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2822 hw->rx_offset = NFP_NET_RX_OFFSET;
2824 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2826 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2827 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2828 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2830 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2831 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2832 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2833 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2834 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2835 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2836 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2837 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2838 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2839 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2840 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2841 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2842 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2843 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2844 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2848 hw->stride_rx = stride;
2849 hw->stride_tx = stride;
2851 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2852 hw->max_rx_queues, hw->max_tx_queues);
2854 /* Initializing spinlock for reconfigs */
2855 rte_spinlock_init(&hw->reconfig_lock);
2857 /* Allocating memory for mac addr */
2858 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2859 if (eth_dev->data->mac_addrs == NULL) {
2860 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2862 goto dev_err_queues_map;
2866 nfp_net_pf_read_mac(hwport0, port);
2867 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2869 nfp_net_vf_read_mac(hw);
2872 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2873 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2875 /* Using random mac addresses for VFs */
2876 eth_random_addr(&hw->mac_addr[0]);
2877 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2880 /* Copying mac address to DPDK eth_dev struct */
2881 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2882 ð_dev->data->mac_addrs[0]);
2884 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2885 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2886 eth_dev->data->port_id, pci_dev->id.vendor_id,
2887 pci_dev->id.device_id,
2888 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2889 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2891 /* Registering LSC interrupt handler */
2892 rte_intr_callback_register(&pci_dev->intr_handle,
2893 nfp_net_dev_interrupt_handler,
2896 /* Telling the firmware about the LSC interrupt entry */
2897 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2899 /* Recording current stats counters values */
2900 nfp_net_stats_reset(eth_dev);
2905 nfp_cpp_area_free(hw->hwqueues_area);
2907 nfp_cpp_area_free(hw->ctrl_area);
2913 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2914 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2915 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2917 struct rte_eth_dev *eth_dev;
2918 struct nfp_net_hw *hw;
2922 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2927 sprintf(port_name, "%s_port%d", dev->device.name, port);
2929 sprintf(port_name, "%s", dev->device.name);
2931 eth_dev = rte_eth_dev_allocate(port_name);
2936 *priv = rte_zmalloc(port_name,
2937 sizeof(struct nfp_net_adapter) * ports,
2938 RTE_CACHE_LINE_SIZE);
2940 rte_eth_dev_release_port(eth_dev);
2945 eth_dev->data->dev_private = *priv;
2948 * dev_private pointing to port0 dev_private because we need
2949 * to configure vNIC bars based on port0 at nfp_net_init.
2950 * Then dev_private is adjusted per port.
2952 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2954 hw->hwinfo = hwinfo;
2955 hw->sym_tbl = sym_tbl;
2956 hw->pf_port_idx = phys_port;
2959 hw->pf_multiport_enabled = 1;
2961 hw->total_ports = ports;
2963 eth_dev->device = &dev->device;
2964 rte_eth_copy_pci_info(eth_dev, dev);
2966 ret = nfp_net_init(eth_dev);
2969 rte_eth_dev_release_port(eth_dev);
2971 rte_eth_dev_probing_finish(eth_dev);
2973 rte_free(port_name);
2978 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
2981 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
2983 struct nfp_cpp *cpp = nsp->cpp;
2988 struct stat file_stat;
2991 /* Looking for firmware file in order of priority */
2993 /* First try to find a firmware image specific for this device */
2994 sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
2995 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
2996 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
2997 cpp->interface & 0xff);
2999 sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3001 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3002 fw_f = open(fw_name, O_RDONLY);
3006 /* Then try the PCI name */
3007 sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3009 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3010 fw_f = open(fw_name, O_RDONLY);
3014 /* Finally try the card type and media */
3015 sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3016 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3017 fw_f = open(fw_name, O_RDONLY);
3019 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3024 if (fstat(fw_f, &file_stat) < 0) {
3025 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3030 fsize = file_stat.st_size;
3031 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3032 fw_name, (uint64_t)fsize);
3034 fw_buf = malloc((size_t)fsize);
3036 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3040 memset(fw_buf, 0, fsize);
3042 bytes = read(fw_f, fw_buf, fsize);
3043 if (bytes != fsize) {
3044 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3045 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3046 (uint64_t)bytes, (uint64_t)fsize);
3052 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3053 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3054 PMD_DRV_LOG(INFO, "Done");
3063 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3064 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3066 struct nfp_nsp *nsp;
3067 const char *nfp_fw_model;
3068 char card_desc[100];
3071 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3074 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3076 PMD_DRV_LOG(ERR, "firmware model NOT found");
3080 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3081 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3082 nfp_eth_table->count);
3086 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3087 nfp_eth_table->count);
3089 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3091 sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3092 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3094 nsp = nfp_nsp_open(cpp);
3096 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3100 nfp_nsp_device_soft_reset(nsp);
3101 err = nfp_fw_upload(dev, nsp, card_desc);
3107 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3108 struct rte_pci_device *dev)
3110 struct nfp_cpp *cpp;
3111 struct nfp_hwinfo *hwinfo;
3112 struct nfp_rtsym_table *sym_tbl;
3113 struct nfp_eth_table *nfp_eth_table = NULL;
3123 cpp = nfp_cpp_from_device_name(dev->device.name);
3125 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3130 hwinfo = nfp_hwinfo_read(cpp);
3132 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3136 nfp_eth_table = nfp_eth_read_ports(cpp);
3137 if (!nfp_eth_table) {
3138 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3142 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3143 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3148 /* Now the symbol table should be there */
3149 sym_tbl = nfp_rtsym_table_read(cpp);
3151 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3157 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3158 if (total_ports != (int)nfp_eth_table->count) {
3159 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3163 PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3165 if (total_ports <= 0 || total_ports > 8) {
3166 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3171 for (i = 0; i < total_ports; i++) {
3172 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3173 nfp_eth_table->ports[i].index,
3180 free(nfp_eth_table);
3184 int nfp_logtype_init;
3185 int nfp_logtype_driver;
3187 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3189 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3190 PCI_DEVICE_ID_NFP4000_PF_NIC)
3193 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3194 PCI_DEVICE_ID_NFP6000_PF_NIC)
3201 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3203 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3204 PCI_DEVICE_ID_NFP6000_VF_NIC)
3211 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3212 struct rte_pci_device *pci_dev)
3214 return rte_eth_dev_pci_generic_probe(pci_dev,
3215 sizeof(struct nfp_net_adapter), nfp_net_init);
3218 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3220 struct rte_eth_dev *eth_dev;
3221 struct nfp_net_hw *hw, *hwport0;
3224 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3225 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3226 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3227 port = get_pf_port_number(eth_dev->data->name);
3229 * hotplug is not possible with multiport PF although freeing
3230 * data structures can be done for first port.
3234 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3235 hw = &hwport0[port];
3236 nfp_cpp_area_free(hw->ctrl_area);
3237 nfp_cpp_area_free(hw->hwqueues_area);
3240 nfp_cpp_free(hw->cpp);
3242 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3244 /* hotplug is not possible with multiport PF */
3245 if (hw->pf_multiport_enabled)
3247 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3250 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3251 .id_table = pci_id_nfp_pf_net_map,
3252 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3253 .probe = nfp_pf_pci_probe,
3254 .remove = eth_nfp_pci_remove,
3257 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3258 .id_table = pci_id_nfp_vf_net_map,
3259 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3260 .probe = eth_nfp_pci_probe,
3261 .remove = eth_nfp_pci_remove,
3264 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3265 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3266 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3267 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3268 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3269 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3271 RTE_INIT(nfp_init_log);
3275 nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3276 if (nfp_logtype_init >= 0)
3277 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3278 nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3279 if (nfp_logtype_driver >= 0)
3280 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3284 * c-file-style: "Linux"
3285 * indent-tabs-mode: t