2 * Copyright (c) 2014-2018 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_ethdev_driver.h>
47 #include <rte_ethdev_pci.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_memzone.h>
52 #include <rte_mempool.h>
53 #include <rte_version.h>
54 #include <rte_string_fns.h>
55 #include <rte_alarm.h>
56 #include <rte_spinlock.h>
58 #include "nfpcore/nfp_cpp.h"
59 #include "nfpcore/nfp_nffw.h"
60 #include "nfpcore/nfp_hwinfo.h"
61 #include "nfpcore/nfp_mip.h"
62 #include "nfpcore/nfp_rtsym.h"
63 #include "nfpcore/nfp_nsp.h"
65 #include "nfp_net_pmd.h"
66 #include "nfp_net_logs.h"
67 #include "nfp_net_ctrl.h"
70 static void nfp_net_close(struct rte_eth_dev *dev);
71 static int nfp_net_configure(struct rte_eth_dev *dev);
72 static void nfp_net_dev_interrupt_handler(void *param);
73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
76 struct rte_eth_dev_info *dev_info);
77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
86 static void nfp_net_rx_queue_release(void *rxq);
87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_rxconf *rx_conf,
90 struct rte_mempool *mp);
91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
92 static void nfp_net_tx_queue_release(void *txq);
93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
94 uint16_t nb_desc, unsigned int socket_id,
95 const struct rte_eth_txconf *tx_conf);
96 static int nfp_net_start(struct rte_eth_dev *dev);
97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
98 struct rte_eth_stats *stats);
99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
100 static void nfp_net_stop(struct rte_eth_dev *dev);
101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
106 struct rte_eth_rss_conf *rss_conf);
107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
111 struct rte_eth_rss_conf *rss_conf);
112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
113 struct ether_addr *mac_addr);
115 /* The offset of the queue controller queues in the PCIe Target */
116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
118 /* Maximum value which can be added to a queue with one transaction */
119 #define NFP_QCP_MAX_ADD 0x7f
121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
122 (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
126 NFP_QCP_READ_PTR = 0,
131 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
132 * @q: Base address for queue structure
133 * @ptr: Add to the Read or Write pointer
134 * @val: Value to add to the queue pointer
136 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
143 if (ptr == NFP_QCP_READ_PTR)
144 off = NFP_QCP_QUEUE_ADD_RPTR;
146 off = NFP_QCP_QUEUE_ADD_WPTR;
148 while (val > NFP_QCP_MAX_ADD) {
149 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
150 val -= NFP_QCP_MAX_ADD;
153 nn_writel(rte_cpu_to_le_32(val), q + off);
157 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
158 * @q: Base address for queue structure
159 * @ptr: Read or Write pointer
161 static inline uint32_t
162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
167 if (ptr == NFP_QCP_READ_PTR)
168 off = NFP_QCP_QUEUE_STS_LO;
170 off = NFP_QCP_QUEUE_STS_HI;
172 val = rte_cpu_to_le_32(nn_readl(q + off));
174 if (ptr == NFP_QCP_READ_PTR)
175 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
177 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
181 * Functions to read/write from/to Config BAR
182 * Performs any endian conversion necessary.
184 static inline uint8_t
185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
187 return nn_readb(hw->ctrl_bar + off);
191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
193 nn_writeb(val, hw->ctrl_bar + off);
196 static inline uint32_t
197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
205 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
208 static inline uint64_t
209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
211 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
217 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
225 if (rxq->rxbufs == NULL)
228 for (i = 0; i < rxq->rx_count; i++) {
229 if (rxq->rxbufs[i].mbuf) {
230 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
231 rxq->rxbufs[i].mbuf = NULL;
237 nfp_net_rx_queue_release(void *rx_queue)
239 struct nfp_net_rxq *rxq = rx_queue;
242 nfp_net_rx_queue_release_mbufs(rxq);
243 rte_free(rxq->rxbufs);
249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
251 nfp_net_rx_queue_release_mbufs(rxq);
257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
261 if (txq->txbufs == NULL)
264 for (i = 0; i < txq->tx_count; i++) {
265 if (txq->txbufs[i].mbuf) {
266 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
267 txq->txbufs[i].mbuf = NULL;
273 nfp_net_tx_queue_release(void *tx_queue)
275 struct nfp_net_txq *txq = tx_queue;
278 nfp_net_tx_queue_release_mbufs(txq);
279 rte_free(txq->txbufs);
285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
287 nfp_net_tx_queue_release_mbufs(txq);
293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
297 struct timespec wait;
299 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
302 if (hw->qcp_cfg == NULL)
303 rte_panic("Bad configuration queue pointer\n");
305 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
308 wait.tv_nsec = 1000000;
310 PMD_DRV_LOG(DEBUG, "Polling for update ack...");
312 /* Poll update field, waiting for NFP to ack the config */
313 for (cnt = 0; ; cnt++) {
314 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
317 if (new & NFP_NET_CFG_UPDATE_ERR) {
318 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
321 if (cnt >= NFP_NET_POLL_TIMEOUT) {
322 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
323 " %dms", update, cnt);
324 rte_panic("Exiting\n");
326 nanosleep(&wait, 0); /* waiting for a 1ms */
328 PMD_DRV_LOG(DEBUG, "Ack DONE");
333 * Reconfigure the NIC
334 * @nn: device to reconfigure
335 * @ctrl: The value for the ctrl field in the BAR config
336 * @update: The value for the update field in the BAR config
338 * Write the update word to the BAR and ping the reconfig queue. Then poll
339 * until the firmware has acknowledged the update by zeroing the update word.
342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
346 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
349 rte_spinlock_lock(&hw->reconfig_lock);
351 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
352 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
356 err = __nfp_net_reconfig(hw, update);
358 rte_spinlock_unlock(&hw->reconfig_lock);
364 * Reconfig errors imply situations where they can be handled.
365 * Otherwise, rte_panic is called inside __nfp_net_reconfig
367 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
373 * Configure an Ethernet device. This function must be invoked first
374 * before any other function in the Ethernet API. This function can
375 * also be re-invoked when a device is in the stopped state.
378 nfp_net_configure(struct rte_eth_dev *dev)
380 struct rte_eth_conf *dev_conf;
381 struct rte_eth_rxmode *rxmode;
382 struct rte_eth_txmode *txmode;
383 struct nfp_net_hw *hw;
385 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
388 * A DPDK app sends info about how many queues to use and how
389 * those queues need to be configured. This is used by the
390 * DPDK core and it makes sure no more queues than those
391 * advertised by the driver are requested. This function is
392 * called after that internal process
395 PMD_INIT_LOG(DEBUG, "Configure");
397 dev_conf = &dev->data->dev_conf;
398 rxmode = &dev_conf->rxmode;
399 txmode = &dev_conf->txmode;
401 /* Checking TX mode */
402 if (txmode->mq_mode) {
403 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
407 /* Checking RX mode */
408 if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
409 !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
410 PMD_INIT_LOG(INFO, "RSS not supported");
418 nfp_net_enable_queues(struct rte_eth_dev *dev)
420 struct nfp_net_hw *hw;
421 uint64_t enabled_queues = 0;
424 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
426 /* Enabling the required TX queues in the device */
427 for (i = 0; i < dev->data->nb_tx_queues; i++)
428 enabled_queues |= (1 << i);
430 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
434 /* Enabling the required RX queues in the device */
435 for (i = 0; i < dev->data->nb_rx_queues; i++)
436 enabled_queues |= (1 << i);
438 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
442 nfp_net_disable_queues(struct rte_eth_dev *dev)
444 struct nfp_net_hw *hw;
445 uint32_t new_ctrl, update = 0;
447 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
449 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
450 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
452 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
453 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
454 NFP_NET_CFG_UPDATE_MSIX;
456 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
457 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
459 /* If an error when reconfig we avoid to change hw state */
460 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
467 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
471 for (i = 0; i < dev->data->nb_rx_queues; i++) {
472 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
479 nfp_net_params_setup(struct nfp_net_hw *hw)
481 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
482 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
486 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
488 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
491 #define ETH_ADDR_LEN 6
494 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
498 for (i = 0; i < ETH_ADDR_LEN; i++)
503 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
505 struct nfp_eth_table *nfp_eth_table;
507 nfp_eth_table = nfp_eth_read_ports(hw->cpp);
509 * hw points to port0 private data. We need hw now pointing to
513 nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
514 (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
521 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
525 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
526 memcpy(&hw->mac_addr[0], &tmp, 4);
528 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
529 memcpy(&hw->mac_addr[4], &tmp, 2);
533 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
535 uint32_t mac0 = *(uint32_t *)mac;
538 nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
541 mac1 = *(uint16_t *)mac;
542 nn_writew(rte_cpu_to_be_16(mac1),
543 hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
547 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
549 struct nfp_net_hw *hw;
550 uint32_t update, ctrl;
552 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
554 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
555 PMD_INIT_LOG(INFO, "MAC address unable to change when"
560 if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
561 !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
564 /* Writing new MAC to the specific port BAR address */
565 nfp_net_write_mac(hw, (uint8_t *)mac_addr);
567 /* Signal the NIC about the change */
568 update = NFP_NET_CFG_UPDATE_MACADDR;
569 ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
570 if (nfp_net_reconfig(hw, ctrl, update) < 0) {
571 PMD_INIT_LOG(INFO, "MAC address update failed");
578 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
579 struct rte_intr_handle *intr_handle)
581 struct nfp_net_hw *hw;
584 if (!intr_handle->intr_vec) {
585 intr_handle->intr_vec =
586 rte_zmalloc("intr_vec",
587 dev->data->nb_rx_queues * sizeof(int), 0);
588 if (!intr_handle->intr_vec) {
589 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
590 " intr_vec", dev->data->nb_rx_queues);
595 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
597 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
598 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
599 /* UIO just supports one queue and no LSC*/
600 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
601 intr_handle->intr_vec[0] = 0;
603 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
604 for (i = 0; i < dev->data->nb_rx_queues; i++) {
606 * The first msix vector is reserved for non
609 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
610 intr_handle->intr_vec[i] = i + 1;
611 PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
612 intr_handle->intr_vec[i]);
616 /* Avoiding TX interrupts */
617 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
622 nfp_check_offloads(struct rte_eth_dev *dev)
624 struct nfp_net_hw *hw;
625 struct rte_eth_conf *dev_conf;
626 struct rte_eth_rxmode *rxmode;
627 struct rte_eth_txmode *txmode;
630 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
632 dev_conf = &dev->data->dev_conf;
633 rxmode = &dev_conf->rxmode;
634 txmode = &dev_conf->txmode;
636 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
637 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
638 ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
641 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
642 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
643 ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
646 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
647 hw->mtu = rxmode->max_rx_pkt_len;
649 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
650 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
653 if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
654 ctrl |= NFP_NET_CFG_CTRL_L2BC;
657 if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
658 ctrl |= NFP_NET_CFG_CTRL_L2MC;
660 /* TX checksum offload */
661 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
662 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
663 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
664 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
667 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
668 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
669 ctrl |= NFP_NET_CFG_CTRL_LSO;
671 ctrl |= NFP_NET_CFG_CTRL_LSO2;
675 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
676 ctrl |= NFP_NET_CFG_CTRL_GATHER;
682 nfp_net_start(struct rte_eth_dev *dev)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t new_ctrl, update = 0;
687 struct nfp_net_hw *hw;
688 struct rte_eth_conf *dev_conf;
689 struct rte_eth_rxmode *rxmode;
690 uint32_t intr_vector;
693 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
695 PMD_INIT_LOG(DEBUG, "Start");
697 /* Disabling queues just in case... */
698 nfp_net_disable_queues(dev);
700 /* Enabling the required queues in the device */
701 nfp_net_enable_queues(dev);
703 /* check and configure queue intr-vector mapping */
704 if (dev->data->dev_conf.intr_conf.rxq != 0) {
705 if (hw->pf_multiport_enabled) {
706 PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
707 "with NFP multiport PF");
710 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
712 * Better not to share LSC with RX interrupts.
713 * Unregistering LSC interrupt handler
715 rte_intr_callback_unregister(&pci_dev->intr_handle,
716 nfp_net_dev_interrupt_handler, (void *)dev);
718 if (dev->data->nb_rx_queues > 1) {
719 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
720 "supports 1 queue with UIO");
724 intr_vector = dev->data->nb_rx_queues;
725 if (rte_intr_efd_enable(intr_handle, intr_vector))
728 nfp_configure_rx_interrupt(dev, intr_handle);
729 update = NFP_NET_CFG_UPDATE_MSIX;
732 rte_intr_enable(intr_handle);
734 new_ctrl = nfp_check_offloads(dev);
736 /* Writing configuration parameters in the device */
737 nfp_net_params_setup(hw);
739 dev_conf = &dev->data->dev_conf;
740 rxmode = &dev_conf->rxmode;
742 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
743 nfp_net_rss_config_default(dev);
744 update |= NFP_NET_CFG_UPDATE_RSS;
745 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
749 new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
751 update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
753 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
754 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
756 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
757 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
761 * Allocating rte mbuffs for configured rx queues.
762 * This requires queues being enabled before
764 if (nfp_net_rx_freelist_setup(dev) < 0) {
769 if (hw->is_pf && rte_eal_process_type() == RTE_PROC_PRIMARY)
770 /* Configure the physical port up */
771 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
773 nfp_eth_set_configured(dev->process_private,
782 * An error returned by this function should mean the app
783 * exiting and then the system releasing all the memory
784 * allocated even memory coming from hugepages.
786 * The device could be enabled at this point with some queues
787 * ready for getting packets. This is true if the call to
788 * nfp_net_rx_freelist_setup() succeeds for some queues but
789 * fails for subsequent queues.
791 * This should make the app exiting but better if we tell the
794 nfp_net_disable_queues(dev);
799 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
801 nfp_net_stop(struct rte_eth_dev *dev)
804 struct nfp_net_hw *hw;
806 PMD_INIT_LOG(DEBUG, "Stop");
808 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
810 nfp_net_disable_queues(dev);
813 for (i = 0; i < dev->data->nb_tx_queues; i++) {
814 nfp_net_reset_tx_queue(
815 (struct nfp_net_txq *)dev->data->tx_queues[i]);
818 for (i = 0; i < dev->data->nb_rx_queues; i++) {
819 nfp_net_reset_rx_queue(
820 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
823 if (hw->is_pf && rte_eal_process_type() == RTE_PROC_PRIMARY)
824 /* Configure the physical port down */
825 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
827 nfp_eth_set_configured(dev->process_private,
831 /* Reset and stop device. The device can not be restarted. */
833 nfp_net_close(struct rte_eth_dev *dev)
835 struct nfp_net_hw *hw;
836 struct rte_pci_device *pci_dev;
839 PMD_INIT_LOG(DEBUG, "Close");
841 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
842 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
845 * We assume that the DPDK application is stopping all the
846 * threads/queues before calling the device close function.
849 nfp_net_disable_queues(dev);
852 for (i = 0; i < dev->data->nb_tx_queues; i++) {
853 nfp_net_reset_tx_queue(
854 (struct nfp_net_txq *)dev->data->tx_queues[i]);
857 for (i = 0; i < dev->data->nb_rx_queues; i++) {
858 nfp_net_reset_rx_queue(
859 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
862 rte_intr_disable(&pci_dev->intr_handle);
863 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
865 /* unregister callback func from eal lib */
866 rte_intr_callback_unregister(&pci_dev->intr_handle,
867 nfp_net_dev_interrupt_handler,
871 * The ixgbe PMD driver disables the pcie master on the
872 * device. The i40e does not...
877 nfp_net_promisc_enable(struct rte_eth_dev *dev)
879 uint32_t new_ctrl, update = 0;
880 struct nfp_net_hw *hw;
882 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
884 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
886 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
887 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
891 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
892 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
896 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
897 update = NFP_NET_CFG_UPDATE_GEN;
900 * DPDK sets promiscuous mode on just after this call assuming
901 * it can not fail ...
903 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
910 nfp_net_promisc_disable(struct rte_eth_dev *dev)
912 uint32_t new_ctrl, update = 0;
913 struct nfp_net_hw *hw;
915 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
917 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
918 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
922 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
923 update = NFP_NET_CFG_UPDATE_GEN;
926 * DPDK sets promiscuous mode off just before this call
927 * assuming it can not fail ...
929 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
936 * return 0 means link status changed, -1 means not changed
938 * Wait to complete is needed as it can take up to 9 seconds to get the Link
942 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
944 struct nfp_net_hw *hw;
945 struct rte_eth_link link;
946 uint32_t nn_link_status;
949 static const uint32_t ls_to_ethtool[] = {
950 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
951 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
952 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
953 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
954 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
955 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
956 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
957 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
960 PMD_DRV_LOG(DEBUG, "Link update");
962 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
964 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
966 memset(&link, 0, sizeof(struct rte_eth_link));
968 if (nn_link_status & NFP_NET_CFG_STS_LINK)
969 link.link_status = ETH_LINK_UP;
971 link.link_duplex = ETH_LINK_FULL_DUPLEX;
973 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
974 NFP_NET_CFG_STS_LINK_RATE_MASK;
976 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
977 link.link_speed = ETH_SPEED_NUM_NONE;
979 link.link_speed = ls_to_ethtool[nn_link_status];
981 ret = rte_eth_linkstatus_set(dev, &link);
983 if (link.link_status)
984 PMD_DRV_LOG(INFO, "NIC Link is Up");
986 PMD_DRV_LOG(INFO, "NIC Link is Down");
992 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
995 struct nfp_net_hw *hw;
996 struct rte_eth_stats nfp_dev_stats;
998 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1000 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1002 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1004 /* reading per RX ring stats */
1005 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1006 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1009 nfp_dev_stats.q_ipackets[i] =
1010 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1012 nfp_dev_stats.q_ipackets[i] -=
1013 hw->eth_stats_base.q_ipackets[i];
1015 nfp_dev_stats.q_ibytes[i] =
1016 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1018 nfp_dev_stats.q_ibytes[i] -=
1019 hw->eth_stats_base.q_ibytes[i];
1022 /* reading per TX ring stats */
1023 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1024 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1027 nfp_dev_stats.q_opackets[i] =
1028 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1030 nfp_dev_stats.q_opackets[i] -=
1031 hw->eth_stats_base.q_opackets[i];
1033 nfp_dev_stats.q_obytes[i] =
1034 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1036 nfp_dev_stats.q_obytes[i] -=
1037 hw->eth_stats_base.q_obytes[i];
1040 nfp_dev_stats.ipackets =
1041 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1043 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1045 nfp_dev_stats.ibytes =
1046 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1048 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1050 nfp_dev_stats.opackets =
1051 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1053 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1055 nfp_dev_stats.obytes =
1056 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1058 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1060 /* reading general device stats */
1061 nfp_dev_stats.ierrors =
1062 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1064 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1066 nfp_dev_stats.oerrors =
1067 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1069 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1071 /* RX ring mbuf allocation failures */
1072 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1074 nfp_dev_stats.imissed =
1075 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1077 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1080 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1087 nfp_net_stats_reset(struct rte_eth_dev *dev)
1090 struct nfp_net_hw *hw;
1092 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1095 * hw->eth_stats_base records the per counter starting point.
1096 * Lets update it now
1099 /* reading per RX ring stats */
1100 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1101 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1104 hw->eth_stats_base.q_ipackets[i] =
1105 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1107 hw->eth_stats_base.q_ibytes[i] =
1108 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1111 /* reading per TX ring stats */
1112 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1113 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1116 hw->eth_stats_base.q_opackets[i] =
1117 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1119 hw->eth_stats_base.q_obytes[i] =
1120 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1123 hw->eth_stats_base.ipackets =
1124 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1126 hw->eth_stats_base.ibytes =
1127 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1129 hw->eth_stats_base.opackets =
1130 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1132 hw->eth_stats_base.obytes =
1133 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1135 /* reading general device stats */
1136 hw->eth_stats_base.ierrors =
1137 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1139 hw->eth_stats_base.oerrors =
1140 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1142 /* RX ring mbuf allocation failures */
1143 dev->data->rx_mbuf_alloc_failed = 0;
1145 hw->eth_stats_base.imissed =
1146 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1150 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1152 struct nfp_net_hw *hw;
1154 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1156 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1157 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1158 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1159 dev_info->max_rx_pktlen = hw->max_mtu;
1160 /* Next should change when PF support is implemented */
1161 dev_info->max_mac_addrs = 1;
1163 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1164 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1166 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1167 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1168 DEV_RX_OFFLOAD_UDP_CKSUM |
1169 DEV_RX_OFFLOAD_TCP_CKSUM;
1171 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1173 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1174 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1176 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1177 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1178 DEV_TX_OFFLOAD_UDP_CKSUM |
1179 DEV_TX_OFFLOAD_TCP_CKSUM;
1181 if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1182 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1184 if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1185 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1187 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1189 .pthresh = DEFAULT_RX_PTHRESH,
1190 .hthresh = DEFAULT_RX_HTHRESH,
1191 .wthresh = DEFAULT_RX_WTHRESH,
1193 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1197 dev_info->default_txconf = (struct rte_eth_txconf) {
1199 .pthresh = DEFAULT_TX_PTHRESH,
1200 .hthresh = DEFAULT_TX_HTHRESH,
1201 .wthresh = DEFAULT_TX_WTHRESH,
1203 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1204 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1207 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1208 ETH_RSS_NONFRAG_IPV4_TCP |
1209 ETH_RSS_NONFRAG_IPV4_UDP |
1211 ETH_RSS_NONFRAG_IPV6_TCP |
1212 ETH_RSS_NONFRAG_IPV6_UDP;
1214 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1215 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1217 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1218 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1219 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1222 static const uint32_t *
1223 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1225 static const uint32_t ptypes[] = {
1226 /* refers to nfp_net_set_hash() */
1227 RTE_PTYPE_INNER_L3_IPV4,
1228 RTE_PTYPE_INNER_L3_IPV6,
1229 RTE_PTYPE_INNER_L3_IPV6_EXT,
1230 RTE_PTYPE_INNER_L4_MASK,
1234 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1240 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1242 struct nfp_net_rxq *rxq;
1243 struct nfp_net_rx_desc *rxds;
1247 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1254 * Other PMDs are just checking the DD bit in intervals of 4
1255 * descriptors and counting all four if the first has the DD
1256 * bit on. Of course, this is not accurate but can be good for
1257 * performance. But ideally that should be done in descriptors
1258 * chunks belonging to the same cache line
1261 while (count < rxq->rx_count) {
1262 rxds = &rxq->rxds[idx];
1263 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1270 if ((idx) == rxq->rx_count)
1278 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1280 struct rte_pci_device *pci_dev;
1281 struct nfp_net_hw *hw;
1284 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1287 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1290 /* Make sure all updates are written before un-masking */
1292 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1293 NFP_NET_CFG_ICR_UNMASKED);
1298 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1300 struct rte_pci_device *pci_dev;
1301 struct nfp_net_hw *hw;
1304 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1307 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1310 /* Make sure all updates are written before un-masking */
1312 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1317 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1319 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1320 struct rte_eth_link link;
1322 rte_eth_linkstatus_get(dev, &link);
1323 if (link.link_status)
1324 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1325 dev->data->port_id, link.link_speed,
1326 link.link_duplex == ETH_LINK_FULL_DUPLEX
1327 ? "full-duplex" : "half-duplex");
1329 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1330 dev->data->port_id);
1332 PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1333 pci_dev->addr.domain, pci_dev->addr.bus,
1334 pci_dev->addr.devid, pci_dev->addr.function);
1337 /* Interrupt configuration and handling */
1340 * nfp_net_irq_unmask - Unmask an interrupt
1342 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1343 * clear the ICR for the entry.
1346 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1348 struct nfp_net_hw *hw;
1349 struct rte_pci_device *pci_dev;
1351 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1354 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1355 /* If MSI-X auto-masking is used, clear the entry */
1357 rte_intr_enable(&pci_dev->intr_handle);
1359 /* Make sure all updates are written before un-masking */
1361 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1362 NFP_NET_CFG_ICR_UNMASKED);
1367 nfp_net_dev_interrupt_handler(void *param)
1370 struct rte_eth_link link;
1371 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1373 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1375 rte_eth_linkstatus_get(dev, &link);
1377 nfp_net_link_update(dev, 0);
1380 if (!link.link_status) {
1381 /* handle it 1 sec later, wait it being stable */
1382 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1383 /* likely to down */
1385 /* handle it 4 sec later, wait it being stable */
1386 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1389 if (rte_eal_alarm_set(timeout * 1000,
1390 nfp_net_dev_interrupt_delayed_handler,
1392 PMD_INIT_LOG(ERR, "Error setting alarm");
1394 nfp_net_irq_unmask(dev);
1399 * Interrupt handler which shall be registered for alarm callback for delayed
1400 * handling specific interrupt to wait for the stable nic state. As the NIC
1401 * interrupt state is not stable for nfp after link is just down, it needs
1402 * to wait 4 seconds to get the stable status.
1404 * @param handle Pointer to interrupt handle.
1405 * @param param The address of parameter (struct rte_eth_dev *)
1410 nfp_net_dev_interrupt_delayed_handler(void *param)
1412 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1414 nfp_net_link_update(dev, 0);
1415 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1417 nfp_net_dev_link_status_print(dev);
1420 nfp_net_irq_unmask(dev);
1424 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1426 struct nfp_net_hw *hw;
1428 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1430 /* check that mtu is within the allowed range */
1431 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1434 /* mtu setting is forbidden if port is started */
1435 if (dev->data->dev_started) {
1436 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1437 dev->data->port_id);
1441 /* switch to jumbo mode if needed */
1442 if ((uint32_t)mtu > ETHER_MAX_LEN)
1443 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1445 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1447 /* update max frame size */
1448 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1450 /* writing to configuration space */
1451 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1459 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1460 uint16_t queue_idx, uint16_t nb_desc,
1461 unsigned int socket_id,
1462 const struct rte_eth_rxconf *rx_conf,
1463 struct rte_mempool *mp)
1465 const struct rte_memzone *tz;
1466 struct nfp_net_rxq *rxq;
1467 struct nfp_net_hw *hw;
1469 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1471 PMD_INIT_FUNC_TRACE();
1473 /* Validating number of descriptors */
1474 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1475 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1476 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1477 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1482 * Free memory prior to re-allocation if needed. This is the case after
1483 * calling nfp_net_stop
1485 if (dev->data->rx_queues[queue_idx]) {
1486 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1487 dev->data->rx_queues[queue_idx] = NULL;
1490 /* Allocating rx queue data structure */
1491 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1492 RTE_CACHE_LINE_SIZE, socket_id);
1496 /* Hw queues mapping based on firmware confifguration */
1497 rxq->qidx = queue_idx;
1498 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1499 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1500 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1501 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1504 * Tracking mbuf size for detecting a potential mbuf overflow due to
1508 rxq->mbuf_size = rxq->mem_pool->elt_size;
1509 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1510 hw->flbufsz = rxq->mbuf_size;
1512 rxq->rx_count = nb_desc;
1513 rxq->port_id = dev->data->port_id;
1514 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1515 rxq->drop_en = rx_conf->rx_drop_en;
1518 * Allocate RX ring hardware descriptors. A memzone large enough to
1519 * handle the maximum ring size is allocated in order to allow for
1520 * resizing in later calls to the queue setup function.
1522 tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1523 sizeof(struct nfp_net_rx_desc) *
1524 NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1528 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1529 nfp_net_rx_queue_release(rxq);
1533 /* Saving physical and virtual addresses for the RX ring */
1534 rxq->dma = (uint64_t)tz->iova;
1535 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1537 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1538 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1539 sizeof(*rxq->rxbufs) * nb_desc,
1540 RTE_CACHE_LINE_SIZE, socket_id);
1541 if (rxq->rxbufs == NULL) {
1542 nfp_net_rx_queue_release(rxq);
1546 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1547 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1549 nfp_net_reset_rx_queue(rxq);
1551 dev->data->rx_queues[queue_idx] = rxq;
1555 * Telling the HW about the physical address of the RX ring and number
1556 * of descriptors in log2 format
1558 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1559 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1565 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1567 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1571 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1574 for (i = 0; i < rxq->rx_count; i++) {
1575 struct nfp_net_rx_desc *rxd;
1576 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1579 PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1580 (unsigned)rxq->qidx);
1584 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1586 rxd = &rxq->rxds[i];
1588 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1589 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1591 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1594 /* Make sure all writes are flushed before telling the hardware */
1597 /* Not advertising the whole ring as the firmware gets confused if so */
1598 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1601 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1607 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1608 uint16_t nb_desc, unsigned int socket_id,
1609 const struct rte_eth_txconf *tx_conf)
1611 const struct rte_memzone *tz;
1612 struct nfp_net_txq *txq;
1613 uint16_t tx_free_thresh;
1614 struct nfp_net_hw *hw;
1616 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618 PMD_INIT_FUNC_TRACE();
1620 /* Validating number of descriptors */
1621 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1622 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1623 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1624 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1628 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1629 tx_conf->tx_free_thresh :
1630 DEFAULT_TX_FREE_THRESH);
1632 if (tx_free_thresh > (nb_desc)) {
1634 "tx_free_thresh must be less than the number of TX "
1635 "descriptors. (tx_free_thresh=%u port=%d "
1636 "queue=%d)", (unsigned int)tx_free_thresh,
1637 dev->data->port_id, (int)queue_idx);
1642 * Free memory prior to re-allocation if needed. This is the case after
1643 * calling nfp_net_stop
1645 if (dev->data->tx_queues[queue_idx]) {
1646 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1648 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1649 dev->data->tx_queues[queue_idx] = NULL;
1652 /* Allocating tx queue data structure */
1653 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1654 RTE_CACHE_LINE_SIZE, socket_id);
1656 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1661 * Allocate TX ring hardware descriptors. A memzone large enough to
1662 * handle the maximum ring size is allocated in order to allow for
1663 * resizing in later calls to the queue setup function.
1665 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1666 sizeof(struct nfp_net_tx_desc) *
1667 NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1670 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1671 nfp_net_tx_queue_release(txq);
1675 txq->tx_count = nb_desc;
1676 txq->tx_free_thresh = tx_free_thresh;
1677 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1678 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1679 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1681 /* queue mapping based on firmware configuration */
1682 txq->qidx = queue_idx;
1683 txq->tx_qcidx = queue_idx * hw->stride_tx;
1684 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1686 txq->port_id = dev->data->port_id;
1688 /* Saving physical and virtual addresses for the TX ring */
1689 txq->dma = (uint64_t)tz->iova;
1690 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1692 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1693 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1694 sizeof(*txq->txbufs) * nb_desc,
1695 RTE_CACHE_LINE_SIZE, socket_id);
1696 if (txq->txbufs == NULL) {
1697 nfp_net_tx_queue_release(txq);
1700 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1701 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1703 nfp_net_reset_tx_queue(txq);
1705 dev->data->tx_queues[queue_idx] = txq;
1709 * Telling the HW about the physical address of the TX ring and number
1710 * of descriptors in log2 format
1712 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1713 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1718 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1720 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1721 struct rte_mbuf *mb)
1724 struct nfp_net_hw *hw = txq->hw;
1726 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1729 ol_flags = mb->ol_flags;
1731 if (!(ol_flags & PKT_TX_TCP_SEG))
1734 txd->l3_offset = mb->l2_len;
1735 txd->l4_offset = mb->l2_len + mb->l3_len;
1736 txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1737 txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1738 txd->flags = PCIE_DESC_TX_LSO;
1745 txd->lso_hdrlen = 0;
1749 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1751 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1752 struct rte_mbuf *mb)
1755 struct nfp_net_hw *hw = txq->hw;
1757 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1760 ol_flags = mb->ol_flags;
1762 /* IPv6 does not need checksum */
1763 if (ol_flags & PKT_TX_IP_CKSUM)
1764 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1766 switch (ol_flags & PKT_TX_L4_MASK) {
1767 case PKT_TX_UDP_CKSUM:
1768 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1770 case PKT_TX_TCP_CKSUM:
1771 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1775 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1776 txd->flags |= PCIE_DESC_TX_CSUM;
1779 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1781 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1782 struct rte_mbuf *mb)
1784 struct nfp_net_hw *hw = rxq->hw;
1786 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1789 /* If IPv4 and IP checksum error, fail */
1790 if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1791 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1792 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1794 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1796 /* If neither UDP nor TCP return */
1797 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1798 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1801 if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1802 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1804 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1807 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1808 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1810 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1813 * nfp_net_set_hash - Set mbuf hash data
1815 * The RSS hash and hash-type are pre-pended to the packet data.
1816 * Extract and decode it and set the mbuf fields.
1819 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1820 struct rte_mbuf *mbuf)
1822 struct nfp_net_hw *hw = rxq->hw;
1823 uint8_t *meta_offset;
1826 uint32_t hash_type = 0;
1828 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1831 /* this is true for new firmwares */
1832 if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1833 (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1834 NFP_DESC_META_LEN(rxd))) {
1837 * <---- 32 bit ----->
1842 * ====================
1845 * Field type word contains up to 8 4bit field types
1846 * A 4bit field type refers to a data field word
1847 * A data field word can have several 4bit field types
1849 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1850 meta_offset -= NFP_DESC_META_LEN(rxd);
1851 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1853 /* NFP PMD just supports metadata for hashing */
1854 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1855 case NFP_NET_META_HASH:
1856 /* next field type is about the hash type */
1857 meta_info >>= NFP_NET_META_FIELD_SIZE;
1858 /* hash value is in the data field */
1859 hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1860 hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1863 /* Unsupported metadata can be a performance issue */
1867 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1870 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1871 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1874 mbuf->hash.rss = hash;
1875 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1877 switch (hash_type) {
1878 case NFP_NET_RSS_IPV4:
1879 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1881 case NFP_NET_RSS_IPV6:
1882 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1884 case NFP_NET_RSS_IPV6_EX:
1885 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1887 case NFP_NET_RSS_IPV4_TCP:
1888 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1890 case NFP_NET_RSS_IPV6_TCP:
1891 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1893 case NFP_NET_RSS_IPV4_UDP:
1894 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1896 case NFP_NET_RSS_IPV6_UDP:
1897 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1900 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1905 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1907 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1910 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1915 * There are some decissions to take:
1916 * 1) How to check DD RX descriptors bit
1917 * 2) How and when to allocate new mbufs
1919 * Current implementation checks just one single DD bit each loop. As each
1920 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1921 * a single cache line instead. Tests with this change have not shown any
1922 * performance improvement but it requires further investigation. For example,
1923 * depending on which descriptor is next, the number of descriptors could be
1924 * less than 8 for just checking those in the same cache line. This implies
1925 * extra work which could be counterproductive by itself. Indeed, last firmware
1926 * changes are just doing this: writing several descriptors with the DD bit
1927 * for saving PCIe bandwidth and DMA operations from the NFP.
1929 * Mbuf allocation is done when a new packet is received. Then the descriptor
1930 * is automatically linked with the new mbuf and the old one is given to the
1931 * user. The main drawback with this design is mbuf allocation is heavier than
1932 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1933 * cache point of view it does not seem allocating the mbuf early on as we are
1934 * doing now have any benefit at all. Again, tests with this change have not
1935 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1936 * so looking at the implications of this type of allocation should be studied
1941 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1943 struct nfp_net_rxq *rxq;
1944 struct nfp_net_rx_desc *rxds;
1945 struct nfp_net_rx_buff *rxb;
1946 struct nfp_net_hw *hw;
1947 struct rte_mbuf *mb;
1948 struct rte_mbuf *new_mb;
1954 if (unlikely(rxq == NULL)) {
1956 * DPDK just checks the queue is lower than max queues
1957 * enabled. But the queue needs to be configured
1959 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1967 while (avail < nb_pkts) {
1968 rxb = &rxq->rxbufs[rxq->rd_p];
1969 if (unlikely(rxb == NULL)) {
1970 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1974 rxds = &rxq->rxds[rxq->rd_p];
1975 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1979 * Memory barrier to ensure that we won't do other
1980 * reads before the DD bit.
1985 * We got a packet. Let's alloc a new mbuff for refilling the
1986 * free descriptor ring as soon as possible
1988 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1989 if (unlikely(new_mb == NULL)) {
1990 RTE_LOG_DP(DEBUG, PMD,
1991 "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1992 rxq->port_id, (unsigned int)rxq->qidx);
1993 nfp_net_mbuf_alloc_failed(rxq);
2000 * Grab the mbuff and refill the descriptor with the
2001 * previously allocated mbuff
2006 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
2007 rxds->rxd.data_len, rxq->mbuf_size);
2009 /* Size of this segment */
2010 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2011 /* Size of the whole packet. We just support 1 segment */
2012 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2014 if (unlikely((mb->data_len + hw->rx_offset) >
2017 * This should not happen and the user has the
2018 * responsibility of avoiding it. But we have
2019 * to give some info about the error
2021 RTE_LOG_DP(ERR, PMD,
2022 "mbuf overflow likely due to the RX offset.\n"
2023 "\t\tYour mbuf size should have extra space for"
2024 " RX offset=%u bytes.\n"
2025 "\t\tCurrently you just have %u bytes available"
2026 " but the received packet is %u bytes long",
2028 rxq->mbuf_size - hw->rx_offset,
2033 /* Filling the received mbuff with packet info */
2035 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2037 mb->data_off = RTE_PKTMBUF_HEADROOM +
2038 NFP_DESC_META_LEN(rxds);
2040 /* No scatter mode supported */
2044 mb->port = rxq->port_id;
2046 /* Checking the RSS flag */
2047 nfp_net_set_hash(rxq, rxds, mb);
2049 /* Checking the checksum flag */
2050 nfp_net_rx_cksum(rxq, rxds, mb);
2052 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2053 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2054 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2055 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2058 /* Adding the mbuff to the mbuff array passed by the app */
2059 rx_pkts[avail++] = mb;
2061 /* Now resetting and updating the descriptor */
2064 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2066 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2067 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2070 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2077 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received",
2078 rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2080 nb_hold += rxq->nb_rx_hold;
2083 * FL descriptors needs to be written before incrementing the
2084 * FL queue WR pointer
2087 if (nb_hold > rxq->rx_free_thresh) {
2088 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2089 rxq->port_id, (unsigned int)rxq->qidx,
2090 (unsigned)nb_hold, (unsigned)avail);
2091 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2094 rxq->nb_rx_hold = nb_hold;
2100 * nfp_net_tx_free_bufs - Check for descriptors with a complete
2102 * @txq: TX queue to work with
2103 * Returns number of descriptors freed
2106 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2111 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2112 " status", txq->qidx);
2114 /* Work out how many packets have been sent */
2115 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2117 if (qcp_rd_p == txq->rd_p) {
2118 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2119 "packets (%u, %u)", txq->qidx,
2120 qcp_rd_p, txq->rd_p);
2124 if (qcp_rd_p > txq->rd_p)
2125 todo = qcp_rd_p - txq->rd_p;
2127 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2129 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2130 qcp_rd_p, txq->rd_p, txq->rd_p);
2136 if (unlikely(txq->rd_p >= txq->tx_count))
2137 txq->rd_p -= txq->tx_count;
2142 /* Leaving always free descriptors for avoiding wrapping confusion */
2144 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2146 if (txq->wr_p >= txq->rd_p)
2147 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2149 return txq->rd_p - txq->wr_p - 8;
2153 * nfp_net_txq_full - Check if the TX queue free descriptors
2154 * is below tx_free_threshold
2156 * @txq: TX queue to check
2158 * This function uses the host copy* of read/write pointers
2161 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2163 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2167 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2169 struct nfp_net_txq *txq;
2170 struct nfp_net_hw *hw;
2171 struct nfp_net_tx_desc *txds, txd;
2172 struct rte_mbuf *pkt;
2174 int pkt_size, dma_size;
2175 uint16_t free_descs, issued_descs;
2176 struct rte_mbuf **lmbuf;
2181 txds = &txq->txds[txq->wr_p];
2183 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2184 txq->qidx, txq->wr_p, nb_pkts);
2186 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2187 nfp_net_tx_free_bufs(txq);
2189 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2190 if (unlikely(free_descs == 0))
2197 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2198 txq->qidx, nb_pkts);
2199 /* Sending packets */
2200 while ((i < nb_pkts) && free_descs) {
2201 /* Grabbing the mbuf linked to the current descriptor */
2202 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2203 /* Warming the cache for releasing the mbuf later on */
2204 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2206 pkt = *(tx_pkts + i);
2208 if (unlikely((pkt->nb_segs > 1) &&
2209 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2210 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2211 rte_panic("Multisegment packet unsupported\n");
2214 /* Checking if we have enough descriptors */
2215 if (unlikely(pkt->nb_segs > free_descs))
2219 * Checksum and VLAN flags just in the first descriptor for a
2220 * multisegment packet, but TSO info needs to be in all of them.
2222 txd.data_len = pkt->pkt_len;
2223 nfp_net_tx_tso(txq, &txd, pkt);
2224 nfp_net_tx_cksum(txq, &txd, pkt);
2226 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2227 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2228 txd.flags |= PCIE_DESC_TX_VLAN;
2229 txd.vlan = pkt->vlan_tci;
2233 * mbuf data_len is the data in one segment and pkt_len data
2234 * in the whole packet. When the packet is just one segment,
2235 * then data_len = pkt_len
2237 pkt_size = pkt->pkt_len;
2240 /* Copying TSO, VLAN and cksum info */
2243 /* Releasing mbuf used by this descriptor previously*/
2245 rte_pktmbuf_free_seg(*lmbuf);
2248 * Linking mbuf with descriptor for being released
2249 * next time descriptor is used
2253 dma_size = pkt->data_len;
2254 dma_addr = rte_mbuf_data_iova(pkt);
2255 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2256 "%" PRIx64 "", dma_addr);
2258 /* Filling descriptors fields */
2259 txds->dma_len = dma_size;
2260 txds->data_len = txd.data_len;
2261 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2262 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2263 ASSERT(free_descs > 0);
2267 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2270 pkt_size -= dma_size;
2273 * Making the EOP, packets with just one segment
2276 if (likely(!pkt_size))
2277 txds->offset_eop = PCIE_DESC_TX_EOP;
2279 txds->offset_eop = 0;
2282 /* Referencing next free TX descriptor */
2283 txds = &txq->txds[txq->wr_p];
2284 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2291 /* Increment write pointers. Force memory write before we let HW know */
2293 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2299 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2301 uint32_t new_ctrl, update;
2302 struct nfp_net_hw *hw;
2305 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2309 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2310 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2311 " ETH_VLAN_EXTEND_OFFLOAD");
2313 /* Enable vlan strip if it is not configured yet */
2314 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2315 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2316 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2318 /* Disable vlan strip just if it is configured */
2319 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2320 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2321 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2326 update = NFP_NET_CFG_UPDATE_GEN;
2328 ret = nfp_net_reconfig(hw, new_ctrl, update);
2330 hw->ctrl = new_ctrl;
2336 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2337 struct rte_eth_rss_reta_entry64 *reta_conf,
2340 uint32_t reta, mask;
2343 struct nfp_net_hw *hw =
2344 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2347 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2348 "(%d) doesn't match the number hardware can supported "
2349 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2354 * Update Redirection Table. There are 128 8bit-entries which can be
2355 * manage as 32 32bit-entries
2357 for (i = 0; i < reta_size; i += 4) {
2358 /* Handling 4 RSS entries per loop */
2359 idx = i / RTE_RETA_GROUP_SIZE;
2360 shift = i % RTE_RETA_GROUP_SIZE;
2361 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2367 /* If all 4 entries were set, don't need read RETA register */
2369 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2371 for (j = 0; j < 4; j++) {
2372 if (!(mask & (0x1 << j)))
2375 /* Clearing the entry bits */
2376 reta &= ~(0xFF << (8 * j));
2377 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2379 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2385 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2387 nfp_net_reta_update(struct rte_eth_dev *dev,
2388 struct rte_eth_rss_reta_entry64 *reta_conf,
2391 struct nfp_net_hw *hw =
2392 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2399 ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2403 update = NFP_NET_CFG_UPDATE_RSS;
2405 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2411 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2413 nfp_net_reta_query(struct rte_eth_dev *dev,
2414 struct rte_eth_rss_reta_entry64 *reta_conf,
2420 struct nfp_net_hw *hw;
2422 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2427 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2428 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2429 "(%d) doesn't match the number hardware can supported "
2430 "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2435 * Reading Redirection Table. There are 128 8bit-entries which can be
2436 * manage as 32 32bit-entries
2438 for (i = 0; i < reta_size; i += 4) {
2439 /* Handling 4 RSS entries per loop */
2440 idx = i / RTE_RETA_GROUP_SIZE;
2441 shift = i % RTE_RETA_GROUP_SIZE;
2442 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2447 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2449 for (j = 0; j < 4; j++) {
2450 if (!(mask & (0x1 << j)))
2452 reta_conf->reta[shift + j] =
2453 (uint8_t)((reta >> (8 * j)) & 0xF);
2460 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2461 struct rte_eth_rss_conf *rss_conf)
2463 struct nfp_net_hw *hw;
2465 uint32_t cfg_rss_ctrl = 0;
2469 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471 /* Writing the key byte a byte */
2472 for (i = 0; i < rss_conf->rss_key_len; i++) {
2473 memcpy(&key, &rss_conf->rss_key[i], 1);
2474 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2477 rss_hf = rss_conf->rss_hf;
2479 if (rss_hf & ETH_RSS_IPV4)
2480 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2482 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2483 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2485 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2486 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2488 if (rss_hf & ETH_RSS_IPV6)
2489 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2491 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2492 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2494 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2495 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2497 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2498 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2500 /* configuring where to apply the RSS hash */
2501 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2503 /* Writing the key size */
2504 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2510 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2511 struct rte_eth_rss_conf *rss_conf)
2515 struct nfp_net_hw *hw;
2517 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519 rss_hf = rss_conf->rss_hf;
2521 /* Checking if RSS is enabled */
2522 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2523 if (rss_hf != 0) { /* Enable RSS? */
2524 PMD_DRV_LOG(ERR, "RSS unsupported");
2527 return 0; /* Nothing to do */
2530 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2531 PMD_DRV_LOG(ERR, "hash key too long");
2535 nfp_net_rss_hash_write(dev, rss_conf);
2537 update = NFP_NET_CFG_UPDATE_RSS;
2539 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2546 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2547 struct rte_eth_rss_conf *rss_conf)
2550 uint32_t cfg_rss_ctrl;
2553 struct nfp_net_hw *hw;
2555 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2560 rss_hf = rss_conf->rss_hf;
2561 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2563 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2564 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2566 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2567 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2569 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2570 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2572 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2573 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2575 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2576 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2578 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2579 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2581 /* Reading the key size */
2582 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2584 /* Reading the key byte a byte */
2585 for (i = 0; i < rss_conf->rss_key_len; i++) {
2586 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2587 memcpy(&rss_conf->rss_key[i], &key, 1);
2594 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2596 struct rte_eth_conf *dev_conf;
2597 struct rte_eth_rss_conf rss_conf;
2598 struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2599 uint16_t rx_queues = dev->data->nb_rx_queues;
2603 PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2606 nfp_reta_conf[0].mask = ~0x0;
2607 nfp_reta_conf[1].mask = ~0x0;
2610 for (i = 0; i < 0x40; i += 8) {
2611 for (j = i; j < (i + 8); j++) {
2612 nfp_reta_conf[0].reta[j] = queue;
2613 nfp_reta_conf[1].reta[j] = queue++;
2617 ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2621 dev_conf = &dev->data->dev_conf;
2623 PMD_DRV_LOG(INFO, "wrong rss conf");
2626 rss_conf = dev_conf->rx_adv_conf.rss_conf;
2628 ret = nfp_net_rss_hash_write(dev, &rss_conf);
2634 /* Initialise and register driver with DPDK Application */
2635 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2636 .dev_configure = nfp_net_configure,
2637 .dev_start = nfp_net_start,
2638 .dev_stop = nfp_net_stop,
2639 .dev_close = nfp_net_close,
2640 .promiscuous_enable = nfp_net_promisc_enable,
2641 .promiscuous_disable = nfp_net_promisc_disable,
2642 .link_update = nfp_net_link_update,
2643 .stats_get = nfp_net_stats_get,
2644 .stats_reset = nfp_net_stats_reset,
2645 .dev_infos_get = nfp_net_infos_get,
2646 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2647 .mtu_set = nfp_net_dev_mtu_set,
2648 .mac_addr_set = nfp_set_mac_addr,
2649 .vlan_offload_set = nfp_net_vlan_offload_set,
2650 .reta_update = nfp_net_reta_update,
2651 .reta_query = nfp_net_reta_query,
2652 .rss_hash_update = nfp_net_rss_hash_update,
2653 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2654 .rx_queue_setup = nfp_net_rx_queue_setup,
2655 .rx_queue_release = nfp_net_rx_queue_release,
2656 .rx_queue_count = nfp_net_rx_queue_count,
2657 .tx_queue_setup = nfp_net_tx_queue_setup,
2658 .tx_queue_release = nfp_net_tx_queue_release,
2659 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2660 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2664 * All eth_dev created got its private data, but before nfp_net_init, that
2665 * private data is referencing private data for all the PF ports. This is due
2666 * to how the vNIC bars are mapped based on first port, so all ports need info
2667 * about port 0 private data. Inside nfp_net_init the private data pointer is
2668 * changed to the right address for each port once the bars have been mapped.
2670 * This functions helps to find out which port and therefore which offset
2671 * inside the private data array to use.
2674 get_pf_port_number(char *name)
2676 char *pf_str = name;
2679 while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2684 * This should not happen at all and it would mean major
2685 * implementation fault.
2687 rte_panic("nfp_net: problem with pf device name\n");
2689 /* Expecting _portX with X within [0,7] */
2692 return (int)strtol(pf_str, NULL, 10);
2696 nfp_net_init(struct rte_eth_dev *eth_dev)
2698 struct rte_pci_device *pci_dev;
2699 struct nfp_net_hw *hw, *hwport0;
2701 uint64_t tx_bar_off = 0, rx_bar_off = 0;
2707 PMD_INIT_FUNC_TRACE();
2709 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2711 /* NFP can not handle DMA addresses requiring more than 40 bits */
2712 if (rte_mem_check_dma_mask(40)) {
2713 RTE_LOG(ERR, PMD, "device %s can not be used:",
2714 pci_dev->device.name);
2715 RTE_LOG(ERR, PMD, "\trestricted dma mask to 40 bits!\n");
2719 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2720 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2721 port = get_pf_port_number(eth_dev->data->name);
2722 if (port < 0 || port > 7) {
2723 PMD_DRV_LOG(ERR, "Port value is wrong");
2727 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2729 /* This points to port 0 private data */
2730 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2732 /* This points to the specific port private data */
2733 hw = &hwport0[port];
2735 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2739 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2740 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2741 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2743 /* For secondary processes, the primary has done all the work */
2744 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2747 rte_eth_copy_pci_info(eth_dev, pci_dev);
2749 hw->device_id = pci_dev->id.device_id;
2750 hw->vendor_id = pci_dev->id.vendor_id;
2751 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2752 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2754 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2755 pci_dev->id.vendor_id, pci_dev->id.device_id,
2756 pci_dev->addr.domain, pci_dev->addr.bus,
2757 pci_dev->addr.devid, pci_dev->addr.function);
2759 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2760 if (hw->ctrl_bar == NULL) {
2762 "hw->ctrl_bar is NULL. BAR0 not configured");
2766 if (hw->is_pf && port == 0) {
2767 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2768 hw->total_ports * 32768,
2770 if (!hw->ctrl_bar) {
2771 printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2775 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2779 if (!hwport0->ctrl_bar)
2782 /* address based on port0 offset */
2783 hw->ctrl_bar = hwport0->ctrl_bar +
2784 (port * NFP_PF_CSR_SLICE_SIZE);
2787 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2789 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2790 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2792 /* Work out where in the BAR the queues start. */
2793 switch (pci_dev->id.device_id) {
2794 case PCI_DEVICE_ID_NFP4000_PF_NIC:
2795 case PCI_DEVICE_ID_NFP6000_PF_NIC:
2796 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2797 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2798 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2799 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2800 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2803 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2805 goto dev_err_ctrl_map;
2808 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2809 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2811 if (hw->is_pf && port == 0) {
2812 /* configure access to tx/rx vNIC BARs */
2813 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2815 NFP_QCP_QUEUE_AREA_SZ,
2816 &hw->hwqueues_area);
2818 if (!hwport0->hw_queues) {
2819 printf("nfp_rtsym_map fails for net.qc");
2821 goto dev_err_ctrl_map;
2824 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2825 hwport0->hw_queues);
2829 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2830 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2831 eth_dev->data->dev_private = hw;
2833 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2835 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2839 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2840 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2842 nfp_net_cfg_queue_setup(hw);
2844 /* Get some of the read-only fields from the config BAR */
2845 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2846 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2847 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2848 hw->mtu = ETHER_MTU;
2850 /* VLAN insertion is incompatible with LSOv2 */
2851 if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2852 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2854 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2855 hw->rx_offset = NFP_NET_RX_OFFSET;
2857 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2859 PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2860 NFD_CFG_MAJOR_VERSION_of(hw->ver),
2861 NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2863 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2864 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2865 hw->cap & NFP_NET_CFG_CTRL_L2BC ? "L2BCFILT " : "",
2866 hw->cap & NFP_NET_CFG_CTRL_L2MC ? "L2MCFILT " : "",
2867 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2868 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2869 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2870 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2871 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2872 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2873 hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",
2874 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2875 hw->cap & NFP_NET_CFG_CTRL_LSO2 ? "TSOv2 " : "",
2876 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "",
2877 hw->cap & NFP_NET_CFG_CTRL_RSS2 ? "RSSv2 " : "");
2881 hw->stride_rx = stride;
2882 hw->stride_tx = stride;
2884 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2885 hw->max_rx_queues, hw->max_tx_queues);
2887 /* Initializing spinlock for reconfigs */
2888 rte_spinlock_init(&hw->reconfig_lock);
2890 /* Allocating memory for mac addr */
2891 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2892 if (eth_dev->data->mac_addrs == NULL) {
2893 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2895 goto dev_err_queues_map;
2899 nfp_net_pf_read_mac(hwport0, port);
2900 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2902 nfp_net_vf_read_mac(hw);
2905 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2906 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2908 /* Using random mac addresses for VFs */
2909 eth_random_addr(&hw->mac_addr[0]);
2910 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2913 /* Copying mac address to DPDK eth_dev struct */
2914 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2915 ð_dev->data->mac_addrs[0]);
2917 if (!(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
2918 eth_dev->data->dev_flags |= RTE_ETH_DEV_NOLIVE_MAC_ADDR;
2920 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2921 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2922 eth_dev->data->port_id, pci_dev->id.vendor_id,
2923 pci_dev->id.device_id,
2924 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2925 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2927 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2928 /* Registering LSC interrupt handler */
2929 rte_intr_callback_register(&pci_dev->intr_handle,
2930 nfp_net_dev_interrupt_handler,
2932 /* Telling the firmware about the LSC interrupt entry */
2933 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2934 /* Recording current stats counters values */
2935 nfp_net_stats_reset(eth_dev);
2941 nfp_cpp_area_free(hw->hwqueues_area);
2943 nfp_cpp_area_free(hw->ctrl_area);
2949 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2950 struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2951 int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2953 struct rte_eth_dev *eth_dev;
2954 struct nfp_net_hw *hw;
2958 port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2963 sprintf(port_name, "%s_port%d", dev->device.name, port);
2965 sprintf(port_name, "%s", dev->device.name);
2968 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2969 eth_dev = rte_eth_dev_allocate(port_name);
2971 rte_free(port_name);
2975 *priv = rte_zmalloc(port_name,
2976 sizeof(struct nfp_net_adapter) *
2977 ports, RTE_CACHE_LINE_SIZE);
2979 rte_free(port_name);
2980 rte_eth_dev_release_port(eth_dev);
2984 eth_dev->data->dev_private = *priv;
2987 * dev_private pointing to port0 dev_private because we need
2988 * to configure vNIC bars based on port0 at nfp_net_init.
2989 * Then dev_private is adjusted per port.
2991 hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2993 hw->hwinfo = hwinfo;
2994 hw->sym_tbl = sym_tbl;
2995 hw->pf_port_idx = phys_port;
2998 hw->pf_multiport_enabled = 1;
3000 hw->total_ports = ports;
3002 eth_dev = rte_eth_dev_attach_secondary(port_name);
3004 RTE_LOG(ERR, EAL, "secondary process attach failed, "
3005 "ethdev doesn't exist");
3006 rte_free(port_name);
3009 eth_dev->process_private = cpp;
3012 eth_dev->device = &dev->device;
3013 rte_eth_copy_pci_info(eth_dev, dev);
3015 retval = nfp_net_init(eth_dev);
3021 rte_eth_dev_probing_finish(eth_dev);
3024 rte_free(port_name);
3029 rte_free(port_name);
3030 /* free ports private data if primary process */
3031 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3032 rte_free(eth_dev->data->dev_private);
3034 rte_eth_dev_release_port(eth_dev);
3039 #define DEFAULT_FW_PATH "/lib/firmware/netronome"
3042 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
3044 struct nfp_cpp *cpp = nsp->cpp;
3049 struct stat file_stat;
3052 /* Looking for firmware file in order of priority */
3054 /* First try to find a firmware image specific for this device */
3055 sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3056 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3057 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3058 cpp->interface & 0xff);
3060 sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3062 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3063 fw_f = open(fw_name, O_RDONLY);
3067 /* Then try the PCI name */
3068 sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3070 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3071 fw_f = open(fw_name, O_RDONLY);
3075 /* Finally try the card type and media */
3076 sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3077 PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3078 fw_f = open(fw_name, O_RDONLY);
3080 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3085 if (fstat(fw_f, &file_stat) < 0) {
3086 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3091 fsize = file_stat.st_size;
3092 PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3093 fw_name, (uint64_t)fsize);
3095 fw_buf = malloc((size_t)fsize);
3097 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3101 memset(fw_buf, 0, fsize);
3103 bytes = read(fw_f, fw_buf, fsize);
3104 if (bytes != fsize) {
3105 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3106 "Just %" PRIu64 " of %" PRIu64 " bytes read",
3107 (uint64_t)bytes, (uint64_t)fsize);
3113 PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3114 nfp_nsp_load_fw(nsp, fw_buf, bytes);
3115 PMD_DRV_LOG(INFO, "Done");
3124 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3125 struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3127 struct nfp_nsp *nsp;
3128 const char *nfp_fw_model;
3129 char card_desc[100];
3132 nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3135 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3137 PMD_DRV_LOG(ERR, "firmware model NOT found");
3141 if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3142 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3143 nfp_eth_table->count);
3147 PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3148 nfp_eth_table->count);
3150 PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3152 sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3153 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3155 nsp = nfp_nsp_open(cpp);
3157 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3161 nfp_nsp_device_soft_reset(nsp);
3162 err = nfp_fw_upload(dev, nsp, card_desc);
3168 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3169 struct rte_pci_device *dev)
3171 struct nfp_cpp *cpp;
3172 struct nfp_hwinfo *hwinfo;
3173 struct nfp_rtsym_table *sym_tbl;
3174 struct nfp_eth_table *nfp_eth_table = NULL;
3185 * When device bound to UIO, the device could be used, by mistake,
3186 * by two DPDK apps, and the UIO driver does not avoid it. This
3187 * could lead to a serious problem when configuring the NFP CPP
3188 * interface. Here we avoid this telling to the CPP init code to
3189 * use a lock file if UIO is being used.
3191 if (dev->kdrv == RTE_KDRV_VFIO)
3192 cpp = nfp_cpp_from_device_name(dev, 0);
3194 cpp = nfp_cpp_from_device_name(dev, 1);
3197 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3202 hwinfo = nfp_hwinfo_read(cpp);
3204 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3208 nfp_eth_table = nfp_eth_read_ports(cpp);
3209 if (!nfp_eth_table) {
3210 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3214 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3215 if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3216 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3222 /* Now the symbol table should be there */
3223 sym_tbl = nfp_rtsym_table_read(cpp);
3225 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3231 total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3232 if (total_ports != (int)nfp_eth_table->count) {
3233 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3237 PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3239 if (total_ports <= 0 || total_ports > 8) {
3240 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3245 for (i = 0; i < total_ports; i++) {
3246 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3247 nfp_eth_table->ports[i].index,
3254 free(nfp_eth_table);
3258 int nfp_logtype_init;
3259 int nfp_logtype_driver;
3261 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3263 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3264 PCI_DEVICE_ID_NFP4000_PF_NIC)
3267 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3268 PCI_DEVICE_ID_NFP6000_PF_NIC)
3275 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3277 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3278 PCI_DEVICE_ID_NFP6000_VF_NIC)
3285 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3286 struct rte_pci_device *pci_dev)
3288 return rte_eth_dev_pci_generic_probe(pci_dev,
3289 sizeof(struct nfp_net_adapter), nfp_net_init);
3292 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3294 struct rte_eth_dev *eth_dev;
3295 struct nfp_net_hw *hw, *hwport0;
3298 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3299 if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3300 (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3301 port = get_pf_port_number(eth_dev->data->name);
3303 * hotplug is not possible with multiport PF although freeing
3304 * data structures can be done for first port.
3308 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3309 hw = &hwport0[port];
3310 nfp_cpp_area_free(hw->ctrl_area);
3311 nfp_cpp_area_free(hw->hwqueues_area);
3314 nfp_cpp_free(hw->cpp);
3316 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3318 /* hotplug is not possible with multiport PF */
3319 if (hw->pf_multiport_enabled)
3321 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3324 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3325 .id_table = pci_id_nfp_pf_net_map,
3326 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3327 RTE_PCI_DRV_IOVA_AS_VA,
3328 .probe = nfp_pf_pci_probe,
3329 .remove = eth_nfp_pci_remove,
3332 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3333 .id_table = pci_id_nfp_vf_net_map,
3334 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3335 RTE_PCI_DRV_IOVA_AS_VA,
3336 .probe = eth_nfp_pci_probe,
3337 .remove = eth_nfp_pci_remove,
3340 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3341 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3342 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3343 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3344 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3345 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3347 RTE_INIT(nfp_init_log)
3349 nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3350 if (nfp_logtype_init >= 0)
3351 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3352 nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3353 if (nfp_logtype_driver >= 0)
3354 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3358 * c-file-style: "Linux"
3359 * indent-tabs-mode: t