4 * Copyright (C) Cavium Inc. 2017. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_cycles.h>
38 #include <rte_malloc.h>
39 #include <rte_memory.h>
41 #include <rte_spinlock.h>
43 #include "../octeontx_logs.h"
44 #include "octeontx_io.h"
45 #include "octeontx_pkovf.h"
47 struct octeontx_pko_iomem {
53 #define PKO_IOMEM_NULL (struct octeontx_pko_iomem){0, 0, 0}
55 struct octeontx_pko_fc_ctl_s {
57 int64_t padding[(PKO_DQ_FC_STRIDE / 8) - 1];
60 struct octeontx_pkovf {
67 struct octeontx_pko_vf_ctl_s {
70 struct octeontx_pko_iomem fc_iomem;
71 struct octeontx_pko_fc_ctl_s *fc_ctl;
72 struct octeontx_pkovf pko[PKO_VF_MAX];
75 } dq_map[PKO_VF_MAX * PKO_VF_NUM_DQ];
78 static struct octeontx_pko_vf_ctl_s pko_vf_ctl;
81 octeontx_pkovf_setup(void)
83 static bool init_once;
88 rte_spinlock_init(&pko_vf_ctl.lock);
90 pko_vf_ctl.fc_iomem = PKO_IOMEM_NULL;
91 pko_vf_ctl.fc_ctl = NULL;
93 for (i = 0; i < PKO_VF_MAX; i++) {
94 pko_vf_ctl.pko[i].bar0 = NULL;
95 pko_vf_ctl.pko[i].bar2 = NULL;
96 pko_vf_ctl.pko[i].domain = ~(uint16_t)0;
97 pko_vf_ctl.pko[i].vfid = ~(uint16_t)0;
100 for (i = 0; i < (PKO_VF_MAX * PKO_VF_NUM_DQ); i++)
101 pko_vf_ctl.dq_map[i].chanid = 0;
107 /* PKOVF pcie device*/
109 pkovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
116 struct octeontx_pkovf *res;
118 RTE_SET_USED(pci_drv);
120 /* For secondary processes, the primary has done all the work */
121 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
124 if (pci_dev->mem_resource[0].addr == NULL ||
125 pci_dev->mem_resource[2].addr == NULL) {
126 octeontx_log_err("Empty bars %p %p",
127 pci_dev->mem_resource[0].addr,
128 pci_dev->mem_resource[2].addr);
131 bar0 = pci_dev->mem_resource[0].addr;
132 bar2 = pci_dev->mem_resource[2].addr;
134 octeontx_pkovf_setup();
136 /* get vfid and domain */
137 val = octeontx_read64(bar0 + PKO_VF_DQ_FC_CONFIG);
138 domain = (val >> 7) & 0xffff;
139 vfid = (val >> 23) & 0xffff;
141 if (unlikely(vfid >= PKO_VF_MAX)) {
142 octeontx_log_err("pko: Invalid vfid %d", vfid);
146 res = &pko_vf_ctl.pko[vfid];
148 res->domain = domain;
152 octeontx_log_dbg("Domain=%d group=%d", res->domain, res->vfid);
156 #define PCI_VENDOR_ID_CAVIUM 0x177D
157 #define PCI_DEVICE_ID_OCTEONTX_PKO_VF 0xA049
159 static const struct rte_pci_id pci_pkovf_map[] = {
161 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
162 PCI_DEVICE_ID_OCTEONTX_PKO_VF)
169 static struct rte_pci_driver pci_pkovf = {
170 .id_table = pci_pkovf_map,
171 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
172 .probe = pkovf_probe,
175 RTE_PMD_REGISTER_PCI(octeontx_pkovf, pci_pkovf);