1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
15 #include "otx2_ethdev_sec.h"
17 static inline uint64_t
18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
22 if (otx2_dev_is_vf(dev) ||
23 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
24 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
29 static inline uint64_t
30 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
34 /* TSO not supported for earlier chip revisions */
35 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
36 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
37 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
38 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
39 DEV_TX_OFFLOAD_GRE_TNL_TSO);
43 static const struct otx2_dev_ops otx2_dev_ops = {
44 .link_status_update = otx2_eth_dev_link_status_update,
45 .ptp_info_update = otx2_eth_dev_ptp_info_update
49 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
51 struct otx2_mbox *mbox = dev->mbox;
52 struct nix_lf_alloc_req *req;
53 struct nix_lf_alloc_rsp *rsp;
56 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
60 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
61 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
62 req->xqe_sz = NIX_XQESZ_W16;
63 req->rss_sz = dev->rss_info.rss_size;
64 req->rss_grps = NIX_RSS_GRPS;
65 req->npa_func = otx2_npa_pf_func_get();
66 req->sso_func = otx2_sso_pf_func_get();
67 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
68 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
69 DEV_RX_OFFLOAD_UDP_CKSUM)) {
70 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
71 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
73 req->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) |
74 BIT_ULL(33 /* Outer L2 Length */) |
75 BIT_ULL(38 /* Inner L4 UDP Length */) |
76 BIT_ULL(39 /* Inner L3 Length */) |
77 BIT_ULL(40 /* Outer L4 UDP Length */) |
78 BIT_ULL(41 /* Outer L3 Length */));
80 if (dev->rss_tag_as_xor == 0)
81 req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
83 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
87 dev->sqb_size = rsp->sqb_size;
88 dev->tx_chan_base = rsp->tx_chan_base;
89 dev->rx_chan_base = rsp->rx_chan_base;
90 dev->rx_chan_cnt = rsp->rx_chan_cnt;
91 dev->tx_chan_cnt = rsp->tx_chan_cnt;
92 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
93 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
94 dev->lf_tx_stats = rsp->lf_tx_stats;
95 dev->lf_rx_stats = rsp->lf_rx_stats;
96 dev->cints = rsp->cints;
97 dev->qints = rsp->qints;
98 dev->npc_flow.channel = dev->rx_chan_base;
99 dev->ptp_en = rsp->hw_rx_tstamp_en;
105 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
107 struct otx2_mbox *mbox = dev->mbox;
108 struct npc_set_pkind *req;
109 struct msg_resp *rsp;
112 if (dev->npc_flow.switch_header_type == 0)
115 if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B &&
116 !otx2_dev_is_sdp(dev)) {
117 otx2_err("chlen90b is not supported on non-SDP device");
121 /* Notify AF about higig2 config */
122 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
123 req->mode = dev->npc_flow.switch_header_type;
125 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
127 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
130 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
131 req->mode = dev->npc_flow.switch_header_type;
133 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
135 return otx2_mbox_process_msg(mbox, (void *)&rsp);
139 nix_lf_free(struct otx2_eth_dev *dev)
141 struct otx2_mbox *mbox = dev->mbox;
142 struct nix_lf_free_req *req;
143 struct ndc_sync_op *ndc_req;
146 /* Sync NDC-NIX for LF */
147 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
148 ndc_req->nix_lf_tx_sync = 1;
149 ndc_req->nix_lf_rx_sync = 1;
150 rc = otx2_mbox_process(mbox);
152 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
154 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
155 /* Let AF driver free all this nix lf's
156 * NPC entries allocated using NPC MBOX.
160 return otx2_mbox_process(mbox);
164 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
166 struct otx2_mbox *mbox = dev->mbox;
168 if (otx2_dev_is_vf_or_sdp(dev))
171 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
173 return otx2_mbox_process(mbox);
177 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
179 struct otx2_mbox *mbox = dev->mbox;
181 if (otx2_dev_is_vf_or_sdp(dev))
184 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
186 return otx2_mbox_process(mbox);
190 npc_rx_enable(struct otx2_eth_dev *dev)
192 struct otx2_mbox *mbox = dev->mbox;
194 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
196 return otx2_mbox_process(mbox);
200 npc_rx_disable(struct otx2_eth_dev *dev)
202 struct otx2_mbox *mbox = dev->mbox;
204 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
206 return otx2_mbox_process(mbox);
210 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
212 struct otx2_mbox *mbox = dev->mbox;
214 if (otx2_dev_is_vf_or_sdp(dev))
217 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
219 return otx2_mbox_process(mbox);
223 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
225 struct otx2_mbox *mbox = dev->mbox;
227 if (en && otx2_dev_is_vf_or_sdp(dev))
231 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
233 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
235 return otx2_mbox_process(mbox);
239 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
241 struct otx2_mbox *mbox = dev->mbox;
243 if (otx2_dev_is_vf_or_sdp(dev))
246 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
248 return otx2_mbox_process(mbox);
252 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
258 static inline uint32_t
259 nix_qsize_to_val(enum nix_q_size_e qsize)
261 return (16UL << (qsize * 2));
264 static inline enum nix_q_size_e
265 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
269 if (otx2_ethdev_fixup_is_min_4k_q(dev))
274 for (; i < nix_q_size_max; i++)
275 if (val <= nix_qsize_to_val(i))
278 if (i >= nix_q_size_max)
279 i = nix_q_size_max - 1;
285 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
286 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
288 struct otx2_mbox *mbox = dev->mbox;
289 const struct rte_memzone *rz;
290 uint32_t ring_size, cq_size;
291 struct nix_aq_enq_req *aq;
296 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
297 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
298 NIX_CQ_ALIGN, dev->node);
300 otx2_err("Failed to allocate mem for cq hw ring");
304 memset(rz->addr, 0, rz->len);
305 rxq->desc = (uintptr_t)rz->addr;
306 rxq->qmask = cq_size - 1;
308 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
310 aq->ctype = NIX_AQ_CTYPE_CQ;
311 aq->op = NIX_AQ_INSTOP_INIT;
315 aq->cq.qsize = rxq->qsize;
316 aq->cq.base = rz->iova;
317 aq->cq.avg_level = 0xff;
318 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
319 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
321 /* Many to one reduction */
322 aq->cq.qint_idx = qid % dev->qints;
323 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
324 aq->cq.cint_idx = qid;
326 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
327 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
328 uint16_t min_rx_drop;
330 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
331 aq->cq.drop = min_rx_drop;
333 rxq->cq_drop = min_rx_drop;
335 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
336 aq->cq.drop = rxq->cq_drop;
340 /* TX pause frames enable flowctrl on RX side */
341 if (dev->fc_info.tx_pause) {
342 /* Single bpid is allocated for all rx channels for now */
343 aq->cq.bpid = dev->fc_info.bpid[0];
344 aq->cq.bp = rxq->cq_drop;
348 rc = otx2_mbox_process(mbox);
350 otx2_err("Failed to init cq context");
354 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
356 aq->ctype = NIX_AQ_CTYPE_RQ;
357 aq->op = NIX_AQ_INSTOP_INIT;
361 if (rxq->offloads & DEV_RX_OFFLOAD_SECURITY)
362 aq->rq.ipsech_ena = 1;
364 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
366 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
367 first_skip = (sizeof(struct rte_mbuf));
368 first_skip += RTE_PKTMBUF_HEADROOM;
369 first_skip += rte_pktmbuf_priv_size(mp);
370 rxq->data_off = first_skip;
372 first_skip /= 8; /* Expressed in number of dwords */
373 aq->rq.first_skip = first_skip;
374 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
375 aq->rq.flow_tagw = 32; /* 32-bits */
376 aq->rq.lpb_sizem1 = mp->elt_size / 8;
377 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
379 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
380 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
381 aq->rq.rq_int_ena = 0;
382 /* Many to one reduction */
383 aq->rq.qint_idx = qid % dev->qints;
385 aq->rq.xqe_drop_ena = 1;
387 rc = otx2_mbox_process(mbox);
389 otx2_err("Failed to init rq context");
399 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
400 struct otx2_eth_rxq *rxq, const bool enb)
402 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
403 struct otx2_mbox *mbox = dev->mbox;
404 struct nix_aq_enq_req *aq;
406 /* Pkts will be dropped silently if RQ is disabled */
407 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
409 aq->ctype = NIX_AQ_CTYPE_RQ;
410 aq->op = NIX_AQ_INSTOP_WRITE;
413 aq->rq_mask.ena = ~(aq->rq_mask.ena);
415 return otx2_mbox_process(mbox);
419 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
421 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
422 struct otx2_mbox *mbox = dev->mbox;
423 struct nix_aq_enq_req *aq;
426 /* RQ is already disabled */
428 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
430 aq->ctype = NIX_AQ_CTYPE_CQ;
431 aq->op = NIX_AQ_INSTOP_WRITE;
434 aq->cq_mask.ena = ~(aq->cq_mask.ena);
436 rc = otx2_mbox_process(mbox);
438 otx2_err("Failed to disable cq context");
446 nix_get_data_off(struct otx2_eth_dev *dev)
448 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
452 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
454 struct rte_mbuf mb_def;
457 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
458 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
459 offsetof(struct rte_mbuf, data_off) != 2);
460 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
461 offsetof(struct rte_mbuf, data_off) != 4);
462 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
463 offsetof(struct rte_mbuf, data_off) != 6);
465 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
466 mb_def.port = port_id;
467 rte_mbuf_refcnt_set(&mb_def, 1);
469 /* Prevent compiler reordering: rearm_data covers previous fields */
470 rte_compiler_barrier();
471 tmp = (uint64_t *)&mb_def.rearm_data;
477 otx2_nix_rx_queue_release(void *rx_queue)
479 struct otx2_eth_rxq *rxq = rx_queue;
484 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
485 nix_cq_rq_uninit(rxq->eth_dev, rxq);
490 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
491 uint16_t nb_desc, unsigned int socket,
492 const struct rte_eth_rxconf *rx_conf,
493 struct rte_mempool *mp)
495 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
496 struct rte_mempool_ops *ops;
497 struct otx2_eth_rxq *rxq;
498 const char *platform_ops;
499 enum nix_q_size_e qsize;
505 /* Compile time check to make sure all fast path elements in a CL */
506 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
509 if (rx_conf->rx_deferred_start == 1) {
510 otx2_err("Deferred Rx start is not supported");
514 platform_ops = rte_mbuf_platform_mempool_ops();
515 /* This driver needs octeontx2_npa mempool ops to work */
516 ops = rte_mempool_get_ops(mp->ops_index);
517 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
518 otx2_err("mempool ops should be of octeontx2_npa type");
522 if (mp->pool_id == 0) {
523 otx2_err("Invalid pool_id");
527 /* Free memory prior to re-allocation if needed */
528 if (eth_dev->data->rx_queues[rq] != NULL) {
529 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
530 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
531 eth_dev->data->rx_queues[rq] = NULL;
534 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
535 dev->rx_offloads |= offloads;
537 /* Find the CQ queue size */
538 qsize = nix_qsize_clampup_get(dev, nb_desc);
539 /* Allocate rxq memory */
540 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
542 otx2_err("Failed to allocate rq=%d", rq);
547 rxq->eth_dev = eth_dev;
549 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
550 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
551 rxq->wdata = (uint64_t)rq << 32;
552 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
553 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
554 eth_dev->data->port_id);
555 rxq->offloads = offloads;
557 rxq->qlen = nix_qsize_to_val(qsize);
559 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
560 rxq->tstamp = &dev->tstamp;
562 /* Alloc completion queue */
563 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
565 otx2_err("Failed to allocate rxq=%u", rq);
569 rxq->qconf.socket_id = socket;
570 rxq->qconf.nb_desc = nb_desc;
571 rxq->qconf.mempool = mp;
572 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
574 nix_rx_queue_reset(rxq);
575 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
576 rq, mp->name, qsize, nb_desc, rxq->qlen);
578 eth_dev->data->rx_queues[rq] = rxq;
579 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
581 /* Calculating delta and freq mult between PTP HI clock and tsc.
582 * These are needed in deriving raw clock value from tsc counter.
583 * read_clock eth op returns raw clock value.
585 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
586 otx2_ethdev_is_ptp_en(dev)) {
587 rc = otx2_nix_raw_clock_tsc_conv(dev);
589 otx2_err("Failed to calculate delta and freq mult");
597 otx2_nix_rx_queue_release(rxq);
602 static inline uint8_t
603 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
606 * Maximum three segments can be supported with W8, Choose
607 * NIX_MAXSQESZ_W16 for multi segment offload.
609 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
610 return NIX_MAXSQESZ_W16;
612 return NIX_MAXSQESZ_W8;
616 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
618 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
619 struct rte_eth_dev_data *data = eth_dev->data;
620 struct rte_eth_conf *conf = &data->dev_conf;
621 struct rte_eth_rxmode *rxmode = &conf->rxmode;
624 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
625 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
626 flags |= NIX_RX_OFFLOAD_RSS_F;
628 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
629 DEV_RX_OFFLOAD_UDP_CKSUM))
630 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
632 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
633 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
634 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
636 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
637 flags |= NIX_RX_MULTI_SEG_F;
639 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
640 DEV_RX_OFFLOAD_QINQ_STRIP))
641 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
643 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
644 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
646 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
647 flags |= NIX_RX_OFFLOAD_SECURITY_F;
649 if (!dev->ptype_disable)
650 flags |= NIX_RX_OFFLOAD_PTYPE_F;
656 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
658 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
659 uint64_t conf = dev->tx_offloads;
662 /* Fastpath is dependent on these enums */
663 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
664 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
665 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
666 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
667 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
668 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
669 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
670 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
671 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
672 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
673 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
674 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
675 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
676 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
677 offsetof(struct rte_mbuf, buf_iova) + 8);
678 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
679 offsetof(struct rte_mbuf, buf_iova) + 16);
680 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
681 offsetof(struct rte_mbuf, ol_flags) + 12);
682 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
683 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
685 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
686 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
687 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
689 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
690 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
691 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
693 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
694 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
695 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
696 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
697 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
699 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
700 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
702 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
703 flags |= NIX_TX_MULTI_SEG_F;
705 /* Enable Inner checksum for TSO */
706 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
707 flags |= (NIX_TX_OFFLOAD_TSO_F |
708 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
710 /* Enable Inner and Outer checksum for Tunnel TSO */
711 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
712 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
713 DEV_TX_OFFLOAD_GRE_TNL_TSO))
714 flags |= (NIX_TX_OFFLOAD_TSO_F |
715 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
716 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
718 if (conf & DEV_TX_OFFLOAD_SECURITY)
719 flags |= NIX_TX_OFFLOAD_SECURITY_F;
721 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
722 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
728 nix_sq_init(struct otx2_eth_txq *txq)
730 struct otx2_eth_dev *dev = txq->dev;
731 struct otx2_mbox *mbox = dev->mbox;
732 struct nix_aq_enq_req *sq;
737 if (txq->sqb_pool->pool_id == 0)
740 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
742 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
746 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
748 sq->ctype = NIX_AQ_CTYPE_SQ;
749 sq->op = NIX_AQ_INSTOP_INIT;
750 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
753 sq->sq.smq_rr_quantum = rr_quantum;
754 sq->sq.default_chan = dev->tx_chan_base;
755 sq->sq.sqe_stype = NIX_STYPE_STF;
757 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
758 sq->sq.sqe_stype = NIX_STYPE_STP;
760 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
761 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
762 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
763 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
764 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
766 /* Many to one reduction */
767 sq->sq.qint_idx = txq->sq % dev->qints;
769 return otx2_mbox_process(mbox);
773 nix_sq_uninit(struct otx2_eth_txq *txq)
775 struct otx2_eth_dev *dev = txq->dev;
776 struct otx2_mbox *mbox = dev->mbox;
777 struct ndc_sync_op *ndc_req;
778 struct nix_aq_enq_rsp *rsp;
779 struct nix_aq_enq_req *aq;
780 uint16_t sqes_per_sqb;
784 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
786 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
788 aq->ctype = NIX_AQ_CTYPE_SQ;
789 aq->op = NIX_AQ_INSTOP_READ;
791 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
795 /* Check if sq is already cleaned up */
800 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
802 aq->ctype = NIX_AQ_CTYPE_SQ;
803 aq->op = NIX_AQ_INSTOP_WRITE;
805 aq->sq_mask.ena = ~aq->sq_mask.ena;
808 rc = otx2_mbox_process(mbox);
812 /* Read SQ and free sqb's */
813 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
815 aq->ctype = NIX_AQ_CTYPE_SQ;
816 aq->op = NIX_AQ_INSTOP_READ;
818 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
823 otx2_err("SQ has pending sqe's");
825 count = aq->sq.sqb_count;
826 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
827 /* Free SQB's that are used */
828 sqb_buf = (void *)rsp->sq.head_sqb;
832 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
833 ((sqes_per_sqb - 1) *
834 nix_sq_max_sqe_sz(txq)));
835 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
841 /* Free next to use sqb */
842 if (rsp->sq.next_sqb)
843 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
846 /* Sync NDC-NIX-TX for LF */
847 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
848 ndc_req->nix_lf_tx_sync = 1;
849 rc = otx2_mbox_process(mbox);
851 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
857 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
859 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
860 struct npa_aq_enq_req *aura_req;
862 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
863 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
864 aura_req->ctype = NPA_AQ_CTYPE_AURA;
865 aura_req->op = NPA_AQ_INSTOP_WRITE;
867 aura_req->aura.limit = nb_sqb_bufs;
868 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
870 return otx2_mbox_process(npa_lf->mbox);
874 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
876 struct otx2_eth_dev *dev = txq->dev;
877 uint16_t sqes_per_sqb, nb_sqb_bufs;
878 char name[RTE_MEMPOOL_NAMESIZE];
879 struct rte_mempool_objsz sz;
880 struct npa_aura_s *aura;
881 uint32_t tmp, blk_sz;
883 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
884 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
885 blk_sz = dev->sqb_size;
887 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
888 sqes_per_sqb = (dev->sqb_size / 8) / 16;
890 sqes_per_sqb = (dev->sqb_size / 8) / 8;
892 nb_sqb_bufs = nb_desc / sqes_per_sqb;
893 /* Clamp up to devarg passed SQB count */
894 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
895 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
897 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
899 MEMPOOL_F_NO_SPREAD);
900 txq->nb_sqb_bufs = nb_sqb_bufs;
901 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
902 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
903 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
904 txq->nb_sqb_bufs_adj =
905 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
907 if (txq->sqb_pool == NULL) {
908 otx2_err("Failed to allocate sqe mempool");
912 memset(aura, 0, sizeof(*aura));
914 aura->fc_addr = txq->fc_iova;
915 aura->fc_hyst_bits = 0; /* Store count on all updates */
916 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
917 otx2_err("Failed to set ops for sqe mempool");
920 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
921 otx2_err("Failed to populate sqe mempool");
925 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
926 if (dev->sqb_size != sz.elt_size) {
927 otx2_err("sqe pool block size is not expected %d != %d",
932 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
940 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
942 struct nix_send_ext_s *send_hdr_ext;
943 struct nix_send_hdr_s *send_hdr;
944 struct nix_send_mem_s *send_mem;
945 union nix_send_sg_s *sg;
947 /* Initialize the fields based on basic single segment packet */
948 memset(&txq->cmd, 0, sizeof(txq->cmd));
950 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
951 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
952 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
953 send_hdr->w0.sizem1 = 2;
955 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
956 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
957 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
958 /* Default: one seg packet would have:
959 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
962 send_hdr->w0.sizem1 = 3;
963 send_hdr_ext->w0.tstmp = 1;
965 /* To calculate the offset for send_mem,
966 * send_hdr->w0.sizem1 * 2
968 send_mem = (struct nix_send_mem_s *)(txq->cmd +
969 (send_hdr->w0.sizem1 << 1));
970 send_mem->subdc = NIX_SUBDC_MEM;
971 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
972 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
974 sg = (union nix_send_sg_s *)&txq->cmd[4];
976 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
977 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
978 send_hdr->w0.sizem1 = 1;
979 sg = (union nix_send_sg_s *)&txq->cmd[2];
982 send_hdr->w0.sq = txq->sq;
983 sg->subdc = NIX_SUBDC_SG;
985 sg->ld_type = NIX_SENDLDTYPE_LDD;
991 otx2_nix_tx_queue_release(void *_txq)
993 struct otx2_eth_txq *txq = _txq;
994 struct rte_eth_dev *eth_dev;
999 eth_dev = txq->dev->eth_dev;
1001 otx2_nix_dbg("Releasing txq %u", txq->sq);
1003 /* Flush and disable tm */
1004 otx2_nix_sq_flush_pre(txq, eth_dev->data->dev_started);
1006 /* Free sqb's and disable sq */
1009 if (txq->sqb_pool) {
1010 rte_mempool_free(txq->sqb_pool);
1011 txq->sqb_pool = NULL;
1013 otx2_nix_sq_flush_post(txq);
1019 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
1020 uint16_t nb_desc, unsigned int socket_id,
1021 const struct rte_eth_txconf *tx_conf)
1023 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1024 const struct rte_memzone *fc;
1025 struct otx2_eth_txq *txq;
1031 /* Compile time check to make sure all fast path elements in a CL */
1032 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1034 if (tx_conf->tx_deferred_start) {
1035 otx2_err("Tx deferred start is not supported");
1039 /* Free memory prior to re-allocation if needed. */
1040 if (eth_dev->data->tx_queues[sq] != NULL) {
1041 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1042 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1043 eth_dev->data->tx_queues[sq] = NULL;
1046 /* Find the expected offloads for this queue */
1047 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1049 /* Allocating tx queue data structure */
1050 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1051 OTX2_ALIGN, socket_id);
1053 otx2_err("Failed to alloc txq=%d", sq);
1059 txq->sqb_pool = NULL;
1060 txq->offloads = offloads;
1061 dev->tx_offloads |= offloads;
1064 * Allocate memory for flow control updates from HW.
1065 * Alloc one cache line, so that fits all FC_STYPE modes.
1067 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1068 OTX2_ALIGN + sizeof(struct npa_aura_s),
1069 OTX2_ALIGN, dev->node);
1071 otx2_err("Failed to allocate mem for fcmem");
1075 txq->fc_iova = fc->iova;
1076 txq->fc_mem = fc->addr;
1078 /* Initialize the aura sqb pool */
1079 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1081 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1085 /* Initialize the SQ */
1086 rc = nix_sq_init(txq);
1088 otx2_err("Failed to init sq=%d context", sq);
1092 txq->fc_cache_pkts = 0;
1093 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1094 /* Evenly distribute LMT slot for each sq */
1095 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1097 txq->qconf.socket_id = socket_id;
1098 txq->qconf.nb_desc = nb_desc;
1099 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1101 otx2_nix_form_default_desc(txq);
1103 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1104 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1105 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1106 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1107 eth_dev->data->tx_queues[sq] = txq;
1108 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1112 otx2_nix_tx_queue_release(txq);
1118 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1120 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1121 struct otx2_eth_qconf *tx_qconf = NULL;
1122 struct otx2_eth_qconf *rx_qconf = NULL;
1123 struct otx2_eth_txq **txq;
1124 struct otx2_eth_rxq **rxq;
1125 int i, nb_rxq, nb_txq;
1127 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1128 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1130 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1131 if (tx_qconf == NULL) {
1132 otx2_err("Failed to allocate memory for tx_qconf");
1136 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1137 if (rx_qconf == NULL) {
1138 otx2_err("Failed to allocate memory for rx_qconf");
1142 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1143 for (i = 0; i < nb_txq; i++) {
1144 if (txq[i] == NULL) {
1145 tx_qconf[i].valid = false;
1146 otx2_info("txq[%d] is already released", i);
1149 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1150 tx_qconf[i].valid = true;
1151 otx2_nix_tx_queue_release(txq[i]);
1152 eth_dev->data->tx_queues[i] = NULL;
1155 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1156 for (i = 0; i < nb_rxq; i++) {
1157 if (rxq[i] == NULL) {
1158 rx_qconf[i].valid = false;
1159 otx2_info("rxq[%d] is already released", i);
1162 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1163 rx_qconf[i].valid = true;
1164 otx2_nix_rx_queue_release(rxq[i]);
1165 eth_dev->data->rx_queues[i] = NULL;
1168 dev->tx_qconf = tx_qconf;
1169 dev->rx_qconf = rx_qconf;
1182 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1184 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1185 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1186 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1187 struct otx2_eth_txq **txq;
1188 struct otx2_eth_rxq **rxq;
1189 int rc, i, nb_rxq, nb_txq;
1191 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1192 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1195 /* Setup tx & rx queues with previous configuration so
1196 * that the queues can be functional in cases like ports
1197 * are started without re configuring queues.
1199 * Usual re config sequence is like below:
1200 * port_configure() {
1205 * queue_configure() {
1212 * In some application's control path, queue_configure() would
1213 * NOT be invoked for TXQs/RXQs in port_configure().
1214 * In such cases, queues can be functional after start as the
1215 * queues are already setup in port_configure().
1217 for (i = 0; i < nb_txq; i++) {
1218 if (!tx_qconf[i].valid)
1220 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1221 tx_qconf[i].socket_id,
1222 &tx_qconf[i].conf.tx);
1224 otx2_err("Failed to setup tx queue rc=%d", rc);
1225 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1226 for (i -= 1; i >= 0; i--)
1227 otx2_nix_tx_queue_release(txq[i]);
1232 free(tx_qconf); tx_qconf = NULL;
1234 for (i = 0; i < nb_rxq; i++) {
1235 if (!rx_qconf[i].valid)
1237 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1238 rx_qconf[i].socket_id,
1239 &rx_qconf[i].conf.rx,
1240 rx_qconf[i].mempool);
1242 otx2_err("Failed to setup rx queue rc=%d", rc);
1243 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1244 for (i -= 1; i >= 0; i--)
1245 otx2_nix_rx_queue_release(rxq[i]);
1246 goto release_tx_queues;
1250 free(rx_qconf); rx_qconf = NULL;
1255 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1256 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1257 otx2_nix_tx_queue_release(txq[i]);
1268 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1270 RTE_SET_USED(queue);
1271 RTE_SET_USED(mbufs);
1278 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1280 /* These dummy functions are required for supporting
1281 * some applications which reconfigure queues without
1282 * stopping tx burst and rx burst threads(eg kni app)
1283 * When the queues context is saved, txq/rxqs are released
1284 * which caused app crash since rx/tx burst is still
1285 * on different lcores
1287 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1288 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1293 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1295 volatile struct nix_lso_format *field;
1297 /* Format works only with TCP packet marked by OL3/OL4 */
1298 field = (volatile struct nix_lso_format *)&req->fields[0];
1299 req->field_mask = NIX_LSO_FIELD_MASK;
1300 /* Outer IPv4/IPv6 */
1301 field->layer = NIX_TXLAYER_OL3;
1302 field->offset = v4 ? 2 : 4;
1303 field->sizem1 = 1; /* 2B */
1304 field->alg = NIX_LSOALG_ADD_PAYLEN;
1308 field->layer = NIX_TXLAYER_OL3;
1311 /* Incremented linearly per segment */
1312 field->alg = NIX_LSOALG_ADD_SEGNUM;
1316 /* TCP sequence number update */
1317 field->layer = NIX_TXLAYER_OL4;
1319 field->sizem1 = 3; /* 4 bytes */
1320 field->alg = NIX_LSOALG_ADD_OFFSET;
1322 /* TCP flags field */
1323 field->layer = NIX_TXLAYER_OL4;
1326 field->alg = NIX_LSOALG_TCP_FLAGS;
1331 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1332 bool outer_v4, bool inner_v4)
1334 volatile struct nix_lso_format *field;
1336 field = (volatile struct nix_lso_format *)&req->fields[0];
1337 req->field_mask = NIX_LSO_FIELD_MASK;
1338 /* Outer IPv4/IPv6 len */
1339 field->layer = NIX_TXLAYER_OL3;
1340 field->offset = outer_v4 ? 2 : 4;
1341 field->sizem1 = 1; /* 2B */
1342 field->alg = NIX_LSOALG_ADD_PAYLEN;
1346 field->layer = NIX_TXLAYER_OL3;
1349 /* Incremented linearly per segment */
1350 field->alg = NIX_LSOALG_ADD_SEGNUM;
1354 /* Outer UDP length */
1355 field->layer = NIX_TXLAYER_OL4;
1358 field->alg = NIX_LSOALG_ADD_PAYLEN;
1361 /* Inner IPv4/IPv6 */
1362 field->layer = NIX_TXLAYER_IL3;
1363 field->offset = inner_v4 ? 2 : 4;
1364 field->sizem1 = 1; /* 2B */
1365 field->alg = NIX_LSOALG_ADD_PAYLEN;
1369 field->layer = NIX_TXLAYER_IL3;
1372 /* Incremented linearly per segment */
1373 field->alg = NIX_LSOALG_ADD_SEGNUM;
1377 /* TCP sequence number update */
1378 field->layer = NIX_TXLAYER_IL4;
1380 field->sizem1 = 3; /* 4 bytes */
1381 field->alg = NIX_LSOALG_ADD_OFFSET;
1384 /* TCP flags field */
1385 field->layer = NIX_TXLAYER_IL4;
1388 field->alg = NIX_LSOALG_TCP_FLAGS;
1393 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1394 bool outer_v4, bool inner_v4)
1396 volatile struct nix_lso_format *field;
1398 field = (volatile struct nix_lso_format *)&req->fields[0];
1399 req->field_mask = NIX_LSO_FIELD_MASK;
1400 /* Outer IPv4/IPv6 len */
1401 field->layer = NIX_TXLAYER_OL3;
1402 field->offset = outer_v4 ? 2 : 4;
1403 field->sizem1 = 1; /* 2B */
1404 field->alg = NIX_LSOALG_ADD_PAYLEN;
1408 field->layer = NIX_TXLAYER_OL3;
1411 /* Incremented linearly per segment */
1412 field->alg = NIX_LSOALG_ADD_SEGNUM;
1416 /* Inner IPv4/IPv6 */
1417 field->layer = NIX_TXLAYER_IL3;
1418 field->offset = inner_v4 ? 2 : 4;
1419 field->sizem1 = 1; /* 2B */
1420 field->alg = NIX_LSOALG_ADD_PAYLEN;
1424 field->layer = NIX_TXLAYER_IL3;
1427 /* Incremented linearly per segment */
1428 field->alg = NIX_LSOALG_ADD_SEGNUM;
1432 /* TCP sequence number update */
1433 field->layer = NIX_TXLAYER_IL4;
1435 field->sizem1 = 3; /* 4 bytes */
1436 field->alg = NIX_LSOALG_ADD_OFFSET;
1439 /* TCP flags field */
1440 field->layer = NIX_TXLAYER_IL4;
1443 field->alg = NIX_LSOALG_TCP_FLAGS;
1448 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1450 struct otx2_mbox *mbox = dev->mbox;
1451 struct nix_lso_format_cfg_rsp *rsp;
1452 struct nix_lso_format_cfg *req;
1456 /* Skip if TSO was not requested */
1457 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1462 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1463 nix_lso_tcp(req, true);
1464 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1468 base = rsp->lso_format_idx;
1469 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1471 dev->lso_base_idx = base;
1472 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1478 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1479 nix_lso_tcp(req, false);
1480 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1484 if (rsp->lso_format_idx != base + 1)
1486 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1489 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1491 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1492 nix_lso_udp_tun_tcp(req, true, true);
1493 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1497 if (rsp->lso_format_idx != base + 2)
1499 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1502 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1504 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1505 nix_lso_udp_tun_tcp(req, true, false);
1506 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1510 if (rsp->lso_format_idx != base + 3)
1512 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1515 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1517 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1518 nix_lso_udp_tun_tcp(req, false, true);
1519 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1523 if (rsp->lso_format_idx != base + 4)
1525 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1528 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1530 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1531 nix_lso_udp_tun_tcp(req, false, false);
1532 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1535 if (rsp->lso_format_idx != base + 5)
1537 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1540 * IPv4/TUN HDR/IPv4/TCP LSO
1542 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1543 nix_lso_tun_tcp(req, true, true);
1544 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1548 if (rsp->lso_format_idx != base + 6)
1550 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1553 * IPv4/TUN HDR/IPv6/TCP LSO
1555 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1556 nix_lso_tun_tcp(req, true, false);
1557 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1561 if (rsp->lso_format_idx != base + 7)
1563 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1566 * IPv6/TUN HDR/IPv4/TCP LSO
1568 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1569 nix_lso_tun_tcp(req, false, true);
1570 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1574 if (rsp->lso_format_idx != base + 8)
1576 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1579 * IPv6/TUN HDR/IPv6/TCP LSO
1581 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1582 nix_lso_tun_tcp(req, false, false);
1583 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1586 if (rsp->lso_format_idx != base + 9)
1588 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1593 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1595 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1596 struct rte_eth_dev_data *data = eth_dev->data;
1597 struct rte_eth_conf *conf = &data->dev_conf;
1598 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1599 struct rte_eth_txmode *txmode = &conf->txmode;
1600 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1601 struct rte_ether_addr *ea;
1602 uint8_t nb_rxq, nb_txq;
1608 if (rte_eal_has_hugepages() == 0) {
1609 otx2_err("Huge page is not configured");
1610 goto fail_configure;
1613 if (conf->dcb_capability_en == 1) {
1614 otx2_err("dcb enable is not supported");
1615 goto fail_configure;
1618 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1619 otx2_err("Flow director is not supported");
1620 goto fail_configure;
1623 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1624 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1625 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1626 goto fail_configure;
1629 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1630 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1631 goto fail_configure;
1634 if (otx2_dev_is_Ax(dev) &&
1635 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1636 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1637 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1638 otx2_err("Outer IP and SCTP checksum unsupported");
1639 goto fail_configure;
1642 /* Free the resources allocated from the previous configure */
1643 if (dev->configured == 1) {
1644 otx2_eth_sec_fini(eth_dev);
1645 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1646 otx2_nix_vlan_fini(eth_dev);
1647 otx2_nix_mc_addr_list_uninstall(eth_dev);
1648 otx2_flow_free_all_resources(dev);
1649 oxt2_nix_unregister_queue_irqs(eth_dev);
1650 if (eth_dev->data->dev_conf.intr_conf.rxq)
1651 oxt2_nix_unregister_cq_irqs(eth_dev);
1652 nix_set_nop_rxtx_function(eth_dev);
1653 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1655 goto fail_configure;
1656 otx2_nix_tm_fini(eth_dev);
1660 dev->rx_offloads = rxmode->offloads;
1661 dev->tx_offloads = txmode->offloads;
1662 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1663 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1664 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1666 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1667 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1669 /* Alloc a nix lf */
1670 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1672 otx2_err("Failed to init nix_lf rc=%d", rc);
1676 otx2_nix_err_intr_enb_dis(eth_dev, true);
1677 otx2_nix_ras_intr_enb_dis(eth_dev, true);
1680 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
1681 otx2_err("Both PTP and switch header enabled");
1685 rc = nix_lf_switch_header_type_enable(dev, true);
1687 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1691 rc = nix_setup_lso_formats(dev);
1693 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1698 rc = otx2_nix_rss_config(eth_dev);
1700 otx2_err("Failed to configure rss rc=%d", rc);
1704 /* Init the default TM scheduler hierarchy */
1705 rc = otx2_nix_tm_init_default(eth_dev);
1707 otx2_err("Failed to init traffic manager rc=%d", rc);
1711 rc = otx2_nix_vlan_offload_init(eth_dev);
1713 otx2_err("Failed to init vlan offload rc=%d", rc);
1717 /* Register queue IRQs */
1718 rc = oxt2_nix_register_queue_irqs(eth_dev);
1720 otx2_err("Failed to register queue interrupts rc=%d", rc);
1724 /* Register cq IRQs */
1725 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1726 if (eth_dev->data->nb_rx_queues > dev->cints) {
1727 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1731 /* Rx interrupt feature cannot work with vector mode because,
1732 * vector mode doesn't process packets unless min 4 pkts are
1733 * received, while cq interrupts are generated even for 1 pkt
1736 dev->scalar_ena = true;
1738 rc = oxt2_nix_register_cq_irqs(eth_dev);
1740 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1745 /* Configure loop back mode */
1746 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1748 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1752 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1754 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1758 /* Enable security */
1759 rc = otx2_eth_sec_init(eth_dev);
1763 rc = otx2_nix_flow_ctrl_init(eth_dev);
1765 otx2_err("Failed to init flow ctrl mode %d", rc);
1769 rc = otx2_nix_mc_addr_list_install(eth_dev);
1771 otx2_err("Failed to install mc address list rc=%d", rc);
1776 * Restore queue config when reconfigure followed by
1777 * reconfigure and no queue configure invoked from application case.
1779 if (dev->configured == 1) {
1780 rc = nix_restore_queue_cfg(eth_dev);
1782 goto uninstall_mc_list;
1785 /* Update the mac address */
1786 ea = eth_dev->data->mac_addrs;
1787 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1788 if (rte_is_zero_ether_addr(ea))
1789 rte_eth_random_addr((uint8_t *)ea);
1791 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1793 /* Apply new link configurations if changed */
1794 rc = otx2_apply_link_speed(eth_dev);
1796 otx2_err("Failed to set link configuration");
1797 goto uninstall_mc_list;
1800 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1801 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1802 " rx_flags=0x%x tx_flags=0x%x",
1803 eth_dev->data->port_id, ea_fmt, nb_rxq,
1804 nb_txq, dev->rx_offloads, dev->tx_offloads,
1805 dev->rx_offload_flags, dev->tx_offload_flags);
1808 dev->configured = 1;
1809 dev->configured_nb_rx_qs = data->nb_rx_queues;
1810 dev->configured_nb_tx_qs = data->nb_tx_queues;
1814 otx2_nix_mc_addr_list_uninstall(eth_dev);
1816 otx2_eth_sec_fini(eth_dev);
1818 oxt2_nix_unregister_cq_irqs(eth_dev);
1820 oxt2_nix_unregister_queue_irqs(eth_dev);
1822 otx2_nix_vlan_fini(eth_dev);
1824 otx2_nix_tm_fini(eth_dev);
1828 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1829 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1831 dev->configured = 0;
1836 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1838 struct rte_eth_dev_data *data = eth_dev->data;
1839 struct otx2_eth_txq *txq;
1842 txq = eth_dev->data->tx_queues[qidx];
1844 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1847 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1849 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1854 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1861 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1863 struct rte_eth_dev_data *data = eth_dev->data;
1864 struct otx2_eth_txq *txq;
1867 txq = eth_dev->data->tx_queues[qidx];
1869 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1872 txq->fc_cache_pkts = 0;
1874 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1876 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1881 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1888 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1890 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1891 struct rte_eth_dev_data *data = eth_dev->data;
1894 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1897 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1899 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1903 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1910 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1912 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1913 struct rte_eth_dev_data *data = eth_dev->data;
1916 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1919 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1921 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1925 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1932 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1934 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1935 struct rte_mbuf *rx_pkts[32];
1936 struct otx2_eth_rxq *rxq;
1937 int count, i, j, rc;
1939 nix_lf_switch_header_type_enable(dev, false);
1940 nix_cgx_stop_link_event(dev);
1941 npc_rx_disable(dev);
1943 /* Stop rx queues and free up pkts pending */
1944 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1945 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1949 rxq = eth_dev->data->rx_queues[i];
1950 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1952 for (j = 0; j < count; j++)
1953 rte_pktmbuf_free(rx_pkts[j]);
1954 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1958 /* Stop tx queues */
1959 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1960 otx2_nix_tx_queue_stop(eth_dev, i);
1964 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1966 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1969 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
1970 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
1973 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
1974 rc = otx2_nix_recalc_mtu(eth_dev);
1979 /* Start rx queues */
1980 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1981 rc = otx2_nix_rx_queue_start(eth_dev, i);
1986 /* Start tx queues */
1987 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1988 rc = otx2_nix_tx_queue_start(eth_dev, i);
1993 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1995 otx2_err("Failed to update flow ctrl mode %d", rc);
1999 /* Enable PTP if it was requested by the app or if it is already
2000 * enabled in PF owning this VF
2002 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
2003 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
2004 otx2_ethdev_is_ptp_en(dev))
2005 otx2_nix_timesync_enable(eth_dev);
2007 otx2_nix_timesync_disable(eth_dev);
2009 /* Update VF about data off shifted by 8 bytes if PTP already
2010 * enabled in PF owning this VF
2012 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
2013 otx2_nix_ptp_enable_vf(eth_dev);
2015 rc = npc_rx_enable(dev);
2017 otx2_err("Failed to enable NPC rx %d", rc);
2021 otx2_nix_toggle_flag_link_cfg(dev, true);
2023 rc = nix_cgx_start_link_event(dev);
2025 otx2_err("Failed to start cgx link event %d", rc);
2029 otx2_nix_toggle_flag_link_cfg(dev, false);
2030 otx2_eth_set_tx_function(eth_dev);
2031 otx2_eth_set_rx_function(eth_dev);
2036 npc_rx_disable(dev);
2037 otx2_nix_toggle_flag_link_cfg(dev, false);
2041 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
2042 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
2044 /* Initialize and register driver with DPDK Application */
2045 static const struct eth_dev_ops otx2_eth_dev_ops = {
2046 .dev_infos_get = otx2_nix_info_get,
2047 .dev_configure = otx2_nix_configure,
2048 .link_update = otx2_nix_link_update,
2049 .tx_queue_setup = otx2_nix_tx_queue_setup,
2050 .tx_queue_release = otx2_nix_tx_queue_release,
2051 .tm_ops_get = otx2_nix_tm_ops_get,
2052 .rx_queue_setup = otx2_nix_rx_queue_setup,
2053 .rx_queue_release = otx2_nix_rx_queue_release,
2054 .dev_start = otx2_nix_dev_start,
2055 .dev_stop = otx2_nix_dev_stop,
2056 .dev_close = otx2_nix_dev_close,
2057 .tx_queue_start = otx2_nix_tx_queue_start,
2058 .tx_queue_stop = otx2_nix_tx_queue_stop,
2059 .rx_queue_start = otx2_nix_rx_queue_start,
2060 .rx_queue_stop = otx2_nix_rx_queue_stop,
2061 .dev_set_link_up = otx2_nix_dev_set_link_up,
2062 .dev_set_link_down = otx2_nix_dev_set_link_down,
2063 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2064 .dev_ptypes_set = otx2_nix_ptypes_set,
2065 .dev_reset = otx2_nix_dev_reset,
2066 .stats_get = otx2_nix_dev_stats_get,
2067 .stats_reset = otx2_nix_dev_stats_reset,
2068 .get_reg = otx2_nix_dev_get_reg,
2069 .mtu_set = otx2_nix_mtu_set,
2070 .mac_addr_add = otx2_nix_mac_addr_add,
2071 .mac_addr_remove = otx2_nix_mac_addr_del,
2072 .mac_addr_set = otx2_nix_mac_addr_set,
2073 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2074 .promiscuous_enable = otx2_nix_promisc_enable,
2075 .promiscuous_disable = otx2_nix_promisc_disable,
2076 .allmulticast_enable = otx2_nix_allmulticast_enable,
2077 .allmulticast_disable = otx2_nix_allmulticast_disable,
2078 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2079 .reta_update = otx2_nix_dev_reta_update,
2080 .reta_query = otx2_nix_dev_reta_query,
2081 .rss_hash_update = otx2_nix_rss_hash_update,
2082 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2083 .xstats_get = otx2_nix_xstats_get,
2084 .xstats_get_names = otx2_nix_xstats_get_names,
2085 .xstats_reset = otx2_nix_xstats_reset,
2086 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2087 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2088 .rxq_info_get = otx2_nix_rxq_info_get,
2089 .txq_info_get = otx2_nix_txq_info_get,
2090 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2091 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2092 .rx_queue_count = otx2_nix_rx_queue_count,
2093 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2094 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2095 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2096 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2097 .set_queue_rate_limit = otx2_nix_tm_set_queue_rate_limit,
2098 .pool_ops_supported = otx2_nix_pool_ops_supported,
2099 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2100 .get_module_info = otx2_nix_get_module_info,
2101 .get_module_eeprom = otx2_nix_get_module_eeprom,
2102 .fw_version_get = otx2_nix_fw_version_get,
2103 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2104 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2105 .timesync_enable = otx2_nix_timesync_enable,
2106 .timesync_disable = otx2_nix_timesync_disable,
2107 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2108 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2109 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2110 .timesync_read_time = otx2_nix_timesync_read_time,
2111 .timesync_write_time = otx2_nix_timesync_write_time,
2112 .vlan_offload_set = otx2_nix_vlan_offload_set,
2113 .vlan_filter_set = otx2_nix_vlan_filter_set,
2114 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2115 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2116 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2117 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2118 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2119 .read_clock = otx2_nix_read_clock,
2123 nix_lf_attach(struct otx2_eth_dev *dev)
2125 struct otx2_mbox *mbox = dev->mbox;
2126 struct rsrc_attach_req *req;
2128 /* Attach NIX(lf) */
2129 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2133 return otx2_mbox_process(mbox);
2137 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2139 struct otx2_mbox *mbox = dev->mbox;
2140 struct msix_offset_rsp *msix_rsp;
2143 /* Get NPA and NIX MSIX vector offsets */
2144 otx2_mbox_alloc_msg_msix_offset(mbox);
2146 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2148 dev->nix_msixoff = msix_rsp->nix_msixoff;
2154 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2156 struct rsrc_detach_req *req;
2158 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2160 /* Detach all except npa lf */
2161 req->partial = true;
2168 return otx2_mbox_process(mbox);
2172 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2174 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2175 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2181 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2183 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2184 struct rte_pci_device *pci_dev;
2185 int rc, max_entries;
2187 eth_dev->dev_ops = &otx2_eth_dev_ops;
2189 /* For secondary processes, the primary has done all the work */
2190 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2191 /* Setup callbacks for secondary process */
2192 otx2_eth_set_tx_function(eth_dev);
2193 otx2_eth_set_rx_function(eth_dev);
2197 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2199 rte_eth_copy_pci_info(eth_dev, pci_dev);
2200 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2202 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2203 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2204 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2206 /* Parse devargs string */
2207 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2209 otx2_err("Failed to parse devargs rc=%d", rc);
2213 if (!dev->mbox_active) {
2214 /* Initialize the base otx2_dev object
2215 * only if already present
2217 rc = otx2_dev_init(pci_dev, dev);
2219 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2223 if (otx2_eth_dev_is_sdp(pci_dev))
2224 dev->sdp_link = true;
2226 dev->sdp_link = false;
2227 /* Device generic callbacks */
2228 dev->ops = &otx2_dev_ops;
2229 dev->eth_dev = eth_dev;
2231 /* Grab the NPA LF if required */
2232 rc = otx2_npa_lf_init(pci_dev, dev);
2234 goto otx2_dev_uninit;
2236 dev->configured = 0;
2237 dev->drv_inited = true;
2238 dev->ptype_disable = 0;
2239 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2240 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2243 rc = nix_lf_attach(dev);
2245 goto otx2_npa_uninit;
2247 /* Get NIX MSIX offset */
2248 rc = nix_lf_get_msix_offset(dev);
2250 goto otx2_npa_uninit;
2252 /* Register LF irq handlers */
2253 rc = otx2_nix_register_irqs(eth_dev);
2257 /* Get maximum number of supported MAC entries */
2258 max_entries = otx2_cgx_mac_max_entries_get(dev);
2259 if (max_entries < 0) {
2260 otx2_err("Failed to get max entries for mac addr");
2262 goto unregister_irq;
2265 /* For VFs, returned max_entries will be 0. But to keep default MAC
2266 * address, one entry must be allocated. So setting up to 1.
2268 if (max_entries == 0)
2271 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2272 RTE_ETHER_ADDR_LEN, 0);
2273 if (eth_dev->data->mac_addrs == NULL) {
2274 otx2_err("Failed to allocate memory for mac addr");
2276 goto unregister_irq;
2279 dev->max_mac_entries = max_entries;
2281 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2283 goto free_mac_addrs;
2285 /* Update the mac address */
2286 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2288 /* Also sync same MAC address to CGX table */
2289 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2291 /* Initialize the tm data structures */
2292 otx2_nix_tm_conf_init(eth_dev);
2294 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2295 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2297 if (otx2_dev_is_96xx_A0(dev) ||
2298 otx2_dev_is_95xx_Ax(dev)) {
2299 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2300 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2303 /* Create security ctx */
2304 rc = otx2_eth_sec_ctx_create(eth_dev);
2306 goto free_mac_addrs;
2307 dev->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2308 dev->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
2310 /* Initialize rte-flow */
2311 rc = otx2_flow_init(dev);
2313 goto sec_ctx_destroy;
2315 otx2_nix_mc_filter_init(dev);
2317 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2318 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2319 eth_dev->data->port_id, dev->pf, dev->vf,
2320 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2321 dev->rx_offload_capa, dev->tx_offload_capa);
2325 otx2_eth_sec_ctx_destroy(eth_dev);
2327 rte_free(eth_dev->data->mac_addrs);
2329 otx2_nix_unregister_irqs(eth_dev);
2331 otx2_eth_dev_lf_detach(dev->mbox);
2335 otx2_dev_fini(pci_dev, dev);
2337 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2342 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2344 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2345 struct rte_pci_device *pci_dev;
2348 /* Nothing to be done for secondary processes */
2349 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2352 /* Clear the flag since we are closing down */
2353 dev->configured = 0;
2355 /* Disable nix bpid config */
2356 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2358 npc_rx_disable(dev);
2360 /* Disable vlan offloads */
2361 otx2_nix_vlan_fini(eth_dev);
2363 /* Disable other rte_flow entries */
2364 otx2_flow_fini(dev);
2366 /* Free multicast filter list */
2367 otx2_nix_mc_filter_fini(dev);
2369 /* Disable PTP if already enabled */
2370 if (otx2_ethdev_is_ptp_en(dev))
2371 otx2_nix_timesync_disable(eth_dev);
2373 nix_cgx_stop_link_event(dev);
2376 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2377 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2378 eth_dev->data->tx_queues[i] = NULL;
2380 eth_dev->data->nb_tx_queues = 0;
2382 /* Free up RQ's and CQ's */
2383 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2384 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2385 eth_dev->data->rx_queues[i] = NULL;
2387 eth_dev->data->nb_rx_queues = 0;
2389 /* Free tm resources */
2390 rc = otx2_nix_tm_fini(eth_dev);
2392 otx2_err("Failed to cleanup tm, rc=%d", rc);
2394 /* Unregister queue irqs */
2395 oxt2_nix_unregister_queue_irqs(eth_dev);
2397 /* Unregister cq irqs */
2398 if (eth_dev->data->dev_conf.intr_conf.rxq)
2399 oxt2_nix_unregister_cq_irqs(eth_dev);
2401 rc = nix_lf_free(dev);
2403 otx2_err("Failed to free nix lf, rc=%d", rc);
2405 rc = otx2_npa_lf_fini();
2407 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2409 /* Disable security */
2410 otx2_eth_sec_fini(eth_dev);
2412 /* Destroy security ctx */
2413 otx2_eth_sec_ctx_destroy(eth_dev);
2415 rte_free(eth_dev->data->mac_addrs);
2416 eth_dev->data->mac_addrs = NULL;
2417 dev->drv_inited = false;
2419 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2420 otx2_nix_unregister_irqs(eth_dev);
2422 rc = otx2_eth_dev_lf_detach(dev->mbox);
2424 otx2_err("Failed to detach resources, rc=%d", rc);
2426 /* Check if mbox close is needed */
2430 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2431 /* Will be freed later by PMD */
2432 eth_dev->data->dev_private = NULL;
2436 otx2_dev_fini(pci_dev, dev);
2441 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2443 otx2_eth_dev_uninit(eth_dev, true);
2447 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2451 rc = otx2_eth_dev_uninit(eth_dev, false);
2455 return otx2_eth_dev_init(eth_dev);
2459 nix_remove(struct rte_pci_device *pci_dev)
2461 struct rte_eth_dev *eth_dev;
2462 struct otx2_idev_cfg *idev;
2463 struct otx2_dev *otx2_dev;
2466 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2468 /* Cleanup eth dev */
2469 rc = otx2_eth_dev_uninit(eth_dev, true);
2473 rte_eth_dev_pci_release(eth_dev);
2476 /* Nothing to be done for secondary processes */
2477 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2480 /* Check for common resources */
2481 idev = otx2_intra_dev_get_cfg();
2482 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2485 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2487 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2490 /* Safe to cleanup mbox as no more users */
2491 otx2_dev_fini(pci_dev, otx2_dev);
2496 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2501 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2505 RTE_SET_USED(pci_drv);
2507 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2510 /* On error on secondary, recheck if port exists in primary or
2511 * in mid of detach state.
2513 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2514 if (!rte_eth_dev_allocated(pci_dev->device.name))
2519 static const struct rte_pci_id pci_nix_map[] = {
2521 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2524 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2527 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2528 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2531 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2532 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2535 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2536 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2543 static struct rte_pci_driver pci_nix = {
2544 .id_table = pci_nix_map,
2545 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2546 RTE_PCI_DRV_INTR_LSC,
2548 .remove = nix_remove,
2551 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2552 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2553 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");