1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
18 otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
20 RTE_SET_USED(eth_dev);
24 otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)
26 RTE_SET_USED(eth_dev);
29 static inline uint64_t
30 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
34 if (otx2_dev_is_vf(dev))
35 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
40 static inline uint64_t
41 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
45 return NIX_TX_OFFLOAD_CAPA;
48 static const struct otx2_dev_ops otx2_dev_ops = {
49 .link_status_update = otx2_eth_dev_link_status_update,
53 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
55 struct otx2_mbox *mbox = dev->mbox;
56 struct nix_lf_alloc_req *req;
57 struct nix_lf_alloc_rsp *rsp;
60 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
64 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
65 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
66 req->xqe_sz = NIX_XQESZ_W16;
67 req->rss_sz = dev->rss_info.rss_size;
68 req->rss_grps = NIX_RSS_GRPS;
69 req->npa_func = otx2_npa_pf_func_get();
70 req->sso_func = otx2_sso_pf_func_get();
71 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
72 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
73 DEV_RX_OFFLOAD_UDP_CKSUM)) {
74 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
75 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
78 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
82 dev->sqb_size = rsp->sqb_size;
83 dev->tx_chan_base = rsp->tx_chan_base;
84 dev->rx_chan_base = rsp->rx_chan_base;
85 dev->rx_chan_cnt = rsp->rx_chan_cnt;
86 dev->tx_chan_cnt = rsp->tx_chan_cnt;
87 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
88 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
89 dev->lf_tx_stats = rsp->lf_tx_stats;
90 dev->lf_rx_stats = rsp->lf_rx_stats;
91 dev->cints = rsp->cints;
92 dev->qints = rsp->qints;
93 dev->npc_flow.channel = dev->rx_chan_base;
99 nix_lf_free(struct otx2_eth_dev *dev)
101 struct otx2_mbox *mbox = dev->mbox;
102 struct nix_lf_free_req *req;
103 struct ndc_sync_op *ndc_req;
106 /* Sync NDC-NIX for LF */
107 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
108 ndc_req->nix_lf_tx_sync = 1;
109 ndc_req->nix_lf_rx_sync = 1;
110 rc = otx2_mbox_process(mbox);
112 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
114 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
115 /* Let AF driver free all this nix lf's
116 * NPC entries allocated using NPC MBOX.
120 return otx2_mbox_process(mbox);
124 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
130 static inline uint32_t
131 nix_qsize_to_val(enum nix_q_size_e qsize)
133 return (16UL << (qsize * 2));
136 static inline enum nix_q_size_e
137 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
141 if (otx2_ethdev_fixup_is_min_4k_q(dev))
146 for (; i < nix_q_size_max; i++)
147 if (val <= nix_qsize_to_val(i))
150 if (i >= nix_q_size_max)
151 i = nix_q_size_max - 1;
157 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
158 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
160 struct otx2_mbox *mbox = dev->mbox;
161 const struct rte_memzone *rz;
162 uint32_t ring_size, cq_size;
163 struct nix_aq_enq_req *aq;
168 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
169 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
170 NIX_CQ_ALIGN, dev->node);
172 otx2_err("Failed to allocate mem for cq hw ring");
176 memset(rz->addr, 0, rz->len);
177 rxq->desc = (uintptr_t)rz->addr;
178 rxq->qmask = cq_size - 1;
180 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
182 aq->ctype = NIX_AQ_CTYPE_CQ;
183 aq->op = NIX_AQ_INSTOP_INIT;
187 aq->cq.qsize = rxq->qsize;
188 aq->cq.base = rz->iova;
189 aq->cq.avg_level = 0xff;
190 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
191 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
193 /* Many to one reduction */
194 aq->cq.qint_idx = qid % dev->qints;
196 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
197 uint16_t min_rx_drop;
198 const float rx_cq_skid = 1024 * 256;
200 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
201 aq->cq.drop = min_rx_drop;
205 rc = otx2_mbox_process(mbox);
207 otx2_err("Failed to init cq context");
211 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
213 aq->ctype = NIX_AQ_CTYPE_RQ;
214 aq->op = NIX_AQ_INSTOP_INIT;
217 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
219 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
220 first_skip = (sizeof(struct rte_mbuf));
221 first_skip += RTE_PKTMBUF_HEADROOM;
222 first_skip += rte_pktmbuf_priv_size(mp);
223 rxq->data_off = first_skip;
225 first_skip /= 8; /* Expressed in number of dwords */
226 aq->rq.first_skip = first_skip;
227 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
228 aq->rq.flow_tagw = 32; /* 32-bits */
229 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
230 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
231 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
232 aq->rq.lpb_sizem1 /= 8;
233 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
235 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
236 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
237 aq->rq.rq_int_ena = 0;
238 /* Many to one reduction */
239 aq->rq.qint_idx = qid % dev->qints;
241 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
242 aq->rq.xqe_drop_ena = 1;
244 rc = otx2_mbox_process(mbox);
246 otx2_err("Failed to init rq context");
256 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
258 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
259 struct otx2_mbox *mbox = dev->mbox;
260 struct nix_aq_enq_req *aq;
263 /* RQ is already disabled */
265 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
267 aq->ctype = NIX_AQ_CTYPE_CQ;
268 aq->op = NIX_AQ_INSTOP_WRITE;
271 aq->cq_mask.ena = ~(aq->cq_mask.ena);
273 rc = otx2_mbox_process(mbox);
275 otx2_err("Failed to disable cq context");
283 nix_get_data_off(struct otx2_eth_dev *dev)
291 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
293 struct rte_mbuf mb_def;
296 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
297 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
298 offsetof(struct rte_mbuf, data_off) != 2);
299 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
300 offsetof(struct rte_mbuf, data_off) != 4);
301 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
302 offsetof(struct rte_mbuf, data_off) != 6);
304 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
305 mb_def.port = port_id;
306 rte_mbuf_refcnt_set(&mb_def, 1);
308 /* Prevent compiler reordering: rearm_data covers previous fields */
309 rte_compiler_barrier();
310 tmp = (uint64_t *)&mb_def.rearm_data;
316 otx2_nix_rx_queue_release(void *rx_queue)
318 struct otx2_eth_rxq *rxq = rx_queue;
323 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
324 nix_cq_rq_uninit(rxq->eth_dev, rxq);
329 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
330 uint16_t nb_desc, unsigned int socket,
331 const struct rte_eth_rxconf *rx_conf,
332 struct rte_mempool *mp)
334 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
335 struct rte_mempool_ops *ops;
336 struct otx2_eth_rxq *rxq;
337 const char *platform_ops;
338 enum nix_q_size_e qsize;
344 /* Compile time check to make sure all fast path elements in a CL */
345 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
348 if (rx_conf->rx_deferred_start == 1) {
349 otx2_err("Deferred Rx start is not supported");
353 platform_ops = rte_mbuf_platform_mempool_ops();
354 /* This driver needs octeontx2_npa mempool ops to work */
355 ops = rte_mempool_get_ops(mp->ops_index);
356 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
357 otx2_err("mempool ops should be of octeontx2_npa type");
361 if (mp->pool_id == 0) {
362 otx2_err("Invalid pool_id");
366 /* Free memory prior to re-allocation if needed */
367 if (eth_dev->data->rx_queues[rq] != NULL) {
368 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
369 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
370 eth_dev->data->rx_queues[rq] = NULL;
373 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
374 dev->rx_offloads |= offloads;
376 /* Find the CQ queue size */
377 qsize = nix_qsize_clampup_get(dev, nb_desc);
378 /* Allocate rxq memory */
379 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
381 otx2_err("Failed to allocate rq=%d", rq);
386 rxq->eth_dev = eth_dev;
388 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
389 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
390 rxq->wdata = (uint64_t)rq << 32;
391 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
392 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
393 eth_dev->data->port_id);
394 rxq->offloads = offloads;
396 rxq->qlen = nix_qsize_to_val(qsize);
399 /* Alloc completion queue */
400 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
402 otx2_err("Failed to allocate rxq=%u", rq);
406 rxq->qconf.socket_id = socket;
407 rxq->qconf.nb_desc = nb_desc;
408 rxq->qconf.mempool = mp;
409 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
411 nix_rx_queue_reset(rxq);
412 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
413 rq, mp->name, qsize, nb_desc, rxq->qlen);
415 eth_dev->data->rx_queues[rq] = rxq;
416 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
420 otx2_nix_rx_queue_release(rxq);
425 static inline uint8_t
426 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
429 * Maximum three segments can be supported with W8, Choose
430 * NIX_MAXSQESZ_W16 for multi segment offload.
432 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
433 return NIX_MAXSQESZ_W16;
435 return NIX_MAXSQESZ_W8;
439 nix_sq_init(struct otx2_eth_txq *txq)
441 struct otx2_eth_dev *dev = txq->dev;
442 struct otx2_mbox *mbox = dev->mbox;
443 struct nix_aq_enq_req *sq;
445 if (txq->sqb_pool->pool_id == 0)
448 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
450 sq->ctype = NIX_AQ_CTYPE_SQ;
451 sq->op = NIX_AQ_INSTOP_INIT;
452 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
454 sq->sq.default_chan = dev->tx_chan_base;
455 sq->sq.sqe_stype = NIX_STYPE_STF;
457 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
458 sq->sq.sqe_stype = NIX_STYPE_STP;
460 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
461 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
462 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
463 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
464 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
466 /* Many to one reduction */
467 sq->sq.qint_idx = txq->sq % dev->qints;
469 return otx2_mbox_process(mbox);
473 nix_sq_uninit(struct otx2_eth_txq *txq)
475 struct otx2_eth_dev *dev = txq->dev;
476 struct otx2_mbox *mbox = dev->mbox;
477 struct ndc_sync_op *ndc_req;
478 struct nix_aq_enq_rsp *rsp;
479 struct nix_aq_enq_req *aq;
480 uint16_t sqes_per_sqb;
484 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
486 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
488 aq->ctype = NIX_AQ_CTYPE_SQ;
489 aq->op = NIX_AQ_INSTOP_READ;
491 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
495 /* Check if sq is already cleaned up */
500 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
502 aq->ctype = NIX_AQ_CTYPE_SQ;
503 aq->op = NIX_AQ_INSTOP_WRITE;
505 aq->sq_mask.ena = ~aq->sq_mask.ena;
508 rc = otx2_mbox_process(mbox);
512 /* Read SQ and free sqb's */
513 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
515 aq->ctype = NIX_AQ_CTYPE_SQ;
516 aq->op = NIX_AQ_INSTOP_READ;
518 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
523 otx2_err("SQ has pending sqe's");
525 count = aq->sq.sqb_count;
526 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
527 /* Free SQB's that are used */
528 sqb_buf = (void *)rsp->sq.head_sqb;
532 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
533 nix_sq_max_sqe_sz(txq)));
534 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
540 /* Free next to use sqb */
541 if (rsp->sq.next_sqb)
542 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
545 /* Sync NDC-NIX-TX for LF */
546 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
547 ndc_req->nix_lf_tx_sync = 1;
548 rc = otx2_mbox_process(mbox);
550 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
556 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
558 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
559 struct npa_aq_enq_req *aura_req;
561 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
562 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
563 aura_req->ctype = NPA_AQ_CTYPE_AURA;
564 aura_req->op = NPA_AQ_INSTOP_WRITE;
566 aura_req->aura.limit = nb_sqb_bufs;
567 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
569 return otx2_mbox_process(npa_lf->mbox);
573 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
575 struct otx2_eth_dev *dev = txq->dev;
576 uint16_t sqes_per_sqb, nb_sqb_bufs;
577 char name[RTE_MEMPOOL_NAMESIZE];
578 struct rte_mempool_objsz sz;
579 struct npa_aura_s *aura;
580 uint32_t tmp, blk_sz;
582 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
583 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
584 blk_sz = dev->sqb_size;
586 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
587 sqes_per_sqb = (dev->sqb_size / 8) / 16;
589 sqes_per_sqb = (dev->sqb_size / 8) / 8;
591 nb_sqb_bufs = nb_desc / sqes_per_sqb;
592 /* Clamp up to devarg passed SQB count */
593 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
594 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
596 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
598 MEMPOOL_F_NO_SPREAD);
599 txq->nb_sqb_bufs = nb_sqb_bufs;
600 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
601 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
602 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
603 txq->nb_sqb_bufs_adj =
604 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
606 if (txq->sqb_pool == NULL) {
607 otx2_err("Failed to allocate sqe mempool");
611 memset(aura, 0, sizeof(*aura));
613 aura->fc_addr = txq->fc_iova;
614 aura->fc_hyst_bits = 0; /* Store count on all updates */
615 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
616 otx2_err("Failed to set ops for sqe mempool");
619 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
620 otx2_err("Failed to populate sqe mempool");
624 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
625 if (dev->sqb_size != sz.elt_size) {
626 otx2_err("sqe pool block size is not expected %d != %d",
631 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
639 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
641 struct nix_send_ext_s *send_hdr_ext;
642 struct nix_send_hdr_s *send_hdr;
643 struct nix_send_mem_s *send_mem;
644 union nix_send_sg_s *sg;
646 /* Initialize the fields based on basic single segment packet */
647 memset(&txq->cmd, 0, sizeof(txq->cmd));
649 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
650 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
651 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
652 send_hdr->w0.sizem1 = 2;
654 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
655 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
656 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
657 /* Default: one seg packet would have:
658 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
661 send_hdr->w0.sizem1 = 3;
662 send_hdr_ext->w0.tstmp = 1;
664 /* To calculate the offset for send_mem,
665 * send_hdr->w0.sizem1 * 2
667 send_mem = (struct nix_send_mem_s *)(txq->cmd +
668 (send_hdr->w0.sizem1 << 1));
669 send_mem->subdc = NIX_SUBDC_MEM;
671 send_mem->wmem = 0x1;
672 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
674 sg = (union nix_send_sg_s *)&txq->cmd[4];
676 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
677 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
678 send_hdr->w0.sizem1 = 1;
679 sg = (union nix_send_sg_s *)&txq->cmd[2];
682 send_hdr->w0.sq = txq->sq;
683 sg->subdc = NIX_SUBDC_SG;
685 sg->ld_type = NIX_SENDLDTYPE_LDD;
691 otx2_nix_tx_queue_release(void *_txq)
693 struct otx2_eth_txq *txq = _txq;
698 otx2_nix_dbg("Releasing txq %u", txq->sq);
700 /* Free sqb's and disable sq */
704 rte_mempool_free(txq->sqb_pool);
705 txq->sqb_pool = NULL;
712 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
713 uint16_t nb_desc, unsigned int socket_id,
714 const struct rte_eth_txconf *tx_conf)
716 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
717 const struct rte_memzone *fc;
718 struct otx2_eth_txq *txq;
724 /* Compile time check to make sure all fast path elements in a CL */
725 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
727 if (tx_conf->tx_deferred_start) {
728 otx2_err("Tx deferred start is not supported");
732 /* Free memory prior to re-allocation if needed. */
733 if (eth_dev->data->tx_queues[sq] != NULL) {
734 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
735 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
736 eth_dev->data->tx_queues[sq] = NULL;
739 /* Find the expected offloads for this queue */
740 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
742 /* Allocating tx queue data structure */
743 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
744 OTX2_ALIGN, socket_id);
746 otx2_err("Failed to alloc txq=%d", sq);
752 txq->sqb_pool = NULL;
753 txq->offloads = offloads;
754 dev->tx_offloads |= offloads;
757 * Allocate memory for flow control updates from HW.
758 * Alloc one cache line, so that fits all FC_STYPE modes.
760 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
761 OTX2_ALIGN + sizeof(struct npa_aura_s),
762 OTX2_ALIGN, dev->node);
764 otx2_err("Failed to allocate mem for fcmem");
768 txq->fc_iova = fc->iova;
769 txq->fc_mem = fc->addr;
771 /* Initialize the aura sqb pool */
772 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
774 otx2_err("Failed to alloc sqe pool rc=%d", rc);
778 /* Initialize the SQ */
779 rc = nix_sq_init(txq);
781 otx2_err("Failed to init sq=%d context", sq);
785 txq->fc_cache_pkts = 0;
786 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
787 /* Evenly distribute LMT slot for each sq */
788 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
790 txq->qconf.socket_id = socket_id;
791 txq->qconf.nb_desc = nb_desc;
792 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
794 otx2_nix_form_default_desc(txq);
796 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
797 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
798 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
799 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
800 eth_dev->data->tx_queues[sq] = txq;
801 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
805 otx2_nix_tx_queue_release(txq);
811 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
813 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
814 struct otx2_eth_qconf *tx_qconf = NULL;
815 struct otx2_eth_qconf *rx_qconf = NULL;
816 struct otx2_eth_txq **txq;
817 struct otx2_eth_rxq **rxq;
818 int i, nb_rxq, nb_txq;
820 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
821 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
823 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
824 if (tx_qconf == NULL) {
825 otx2_err("Failed to allocate memory for tx_qconf");
829 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
830 if (rx_qconf == NULL) {
831 otx2_err("Failed to allocate memory for rx_qconf");
835 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
836 for (i = 0; i < nb_txq; i++) {
837 if (txq[i] == NULL) {
838 otx2_err("txq[%d] is already released", i);
841 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
842 otx2_nix_tx_queue_release(txq[i]);
843 eth_dev->data->tx_queues[i] = NULL;
846 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
847 for (i = 0; i < nb_rxq; i++) {
848 if (rxq[i] == NULL) {
849 otx2_err("rxq[%d] is already released", i);
852 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
853 otx2_nix_rx_queue_release(rxq[i]);
854 eth_dev->data->rx_queues[i] = NULL;
857 dev->tx_qconf = tx_qconf;
858 dev->rx_qconf = rx_qconf;
871 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
873 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
874 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
875 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
876 struct otx2_eth_txq **txq;
877 struct otx2_eth_rxq **rxq;
878 int rc, i, nb_rxq, nb_txq;
880 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
881 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
884 /* Setup tx & rx queues with previous configuration so
885 * that the queues can be functional in cases like ports
886 * are started without re configuring queues.
888 * Usual re config sequence is like below:
894 * queue_configure() {
901 * In some application's control path, queue_configure() would
902 * NOT be invoked for TXQs/RXQs in port_configure().
903 * In such cases, queues can be functional after start as the
904 * queues are already setup in port_configure().
906 for (i = 0; i < nb_txq; i++) {
907 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
908 tx_qconf[i].socket_id,
909 &tx_qconf[i].conf.tx);
911 otx2_err("Failed to setup tx queue rc=%d", rc);
912 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
913 for (i -= 1; i >= 0; i--)
914 otx2_nix_tx_queue_release(txq[i]);
919 free(tx_qconf); tx_qconf = NULL;
921 for (i = 0; i < nb_rxq; i++) {
922 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
923 rx_qconf[i].socket_id,
924 &rx_qconf[i].conf.rx,
925 rx_qconf[i].mempool);
927 otx2_err("Failed to setup rx queue rc=%d", rc);
928 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
929 for (i -= 1; i >= 0; i--)
930 otx2_nix_rx_queue_release(rxq[i]);
931 goto release_tx_queues;
935 free(rx_qconf); rx_qconf = NULL;
940 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
941 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
942 otx2_nix_tx_queue_release(txq[i]);
953 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
963 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
965 /* These dummy functions are required for supporting
966 * some applications which reconfigure queues without
967 * stopping tx burst and rx burst threads(eg kni app)
968 * When the queues context is saved, txq/rxqs are released
969 * which caused app crash since rx/tx burst is still
970 * on different lcores
972 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
973 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
978 otx2_nix_configure(struct rte_eth_dev *eth_dev)
980 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
981 struct rte_eth_dev_data *data = eth_dev->data;
982 struct rte_eth_conf *conf = &data->dev_conf;
983 struct rte_eth_rxmode *rxmode = &conf->rxmode;
984 struct rte_eth_txmode *txmode = &conf->txmode;
985 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
986 struct rte_ether_addr *ea;
987 uint8_t nb_rxq, nb_txq;
993 if (rte_eal_has_hugepages() == 0) {
994 otx2_err("Huge page is not configured");
998 if (rte_eal_iova_mode() != RTE_IOVA_VA) {
999 otx2_err("iova mode should be va");
1003 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1004 otx2_err("Setting link speed/duplex not supported");
1008 if (conf->dcb_capability_en == 1) {
1009 otx2_err("dcb enable is not supported");
1013 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1014 otx2_err("Flow director is not supported");
1018 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1019 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1020 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1024 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1025 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1029 /* Free the resources allocated from the previous configure */
1030 if (dev->configured == 1) {
1031 oxt2_nix_unregister_queue_irqs(eth_dev);
1032 nix_set_nop_rxtx_function(eth_dev);
1033 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1039 if (otx2_dev_is_A0(dev) &&
1040 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1041 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1042 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1043 otx2_err("Outer IP and SCTP checksum unsupported");
1048 dev->rx_offloads = rxmode->offloads;
1049 dev->tx_offloads = txmode->offloads;
1050 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1052 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1053 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1055 /* Alloc a nix lf */
1056 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1058 otx2_err("Failed to init nix_lf rc=%d", rc);
1063 rc = otx2_nix_rss_config(eth_dev);
1065 otx2_err("Failed to configure rss rc=%d", rc);
1069 /* Register queue IRQs */
1070 rc = oxt2_nix_register_queue_irqs(eth_dev);
1072 otx2_err("Failed to register queue interrupts rc=%d", rc);
1077 * Restore queue config when reconfigure followed by
1078 * reconfigure and no queue configure invoked from application case.
1080 if (dev->configured == 1) {
1081 rc = nix_restore_queue_cfg(eth_dev);
1086 /* Update the mac address */
1087 ea = eth_dev->data->mac_addrs;
1088 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1089 if (rte_is_zero_ether_addr(ea))
1090 rte_eth_random_addr((uint8_t *)ea);
1092 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1094 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1095 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1096 " rx_flags=0x%x tx_flags=0x%x",
1097 eth_dev->data->port_id, ea_fmt, nb_rxq,
1098 nb_txq, dev->rx_offloads, dev->tx_offloads,
1099 dev->rx_offload_flags, dev->tx_offload_flags);
1102 dev->configured = 1;
1103 dev->configured_nb_rx_qs = data->nb_rx_queues;
1104 dev->configured_nb_tx_qs = data->nb_tx_queues;
1108 rc = nix_lf_free(dev);
1113 /* Initialize and register driver with DPDK Application */
1114 static const struct eth_dev_ops otx2_eth_dev_ops = {
1115 .dev_infos_get = otx2_nix_info_get,
1116 .dev_configure = otx2_nix_configure,
1117 .link_update = otx2_nix_link_update,
1118 .tx_queue_setup = otx2_nix_tx_queue_setup,
1119 .tx_queue_release = otx2_nix_tx_queue_release,
1120 .rx_queue_setup = otx2_nix_rx_queue_setup,
1121 .rx_queue_release = otx2_nix_rx_queue_release,
1122 .stats_get = otx2_nix_dev_stats_get,
1123 .stats_reset = otx2_nix_dev_stats_reset,
1124 .get_reg = otx2_nix_dev_get_reg,
1125 .mac_addr_add = otx2_nix_mac_addr_add,
1126 .mac_addr_remove = otx2_nix_mac_addr_del,
1127 .mac_addr_set = otx2_nix_mac_addr_set,
1128 .promiscuous_enable = otx2_nix_promisc_enable,
1129 .promiscuous_disable = otx2_nix_promisc_disable,
1130 .allmulticast_enable = otx2_nix_allmulticast_enable,
1131 .allmulticast_disable = otx2_nix_allmulticast_disable,
1132 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1133 .reta_update = otx2_nix_dev_reta_update,
1134 .reta_query = otx2_nix_dev_reta_query,
1135 .rss_hash_update = otx2_nix_rss_hash_update,
1136 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1137 .xstats_get = otx2_nix_xstats_get,
1138 .xstats_get_names = otx2_nix_xstats_get_names,
1139 .xstats_reset = otx2_nix_xstats_reset,
1140 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1141 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1145 nix_lf_attach(struct otx2_eth_dev *dev)
1147 struct otx2_mbox *mbox = dev->mbox;
1148 struct rsrc_attach_req *req;
1150 /* Attach NIX(lf) */
1151 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1155 return otx2_mbox_process(mbox);
1159 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1161 struct otx2_mbox *mbox = dev->mbox;
1162 struct msix_offset_rsp *msix_rsp;
1165 /* Get NPA and NIX MSIX vector offsets */
1166 otx2_mbox_alloc_msg_msix_offset(mbox);
1168 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1170 dev->nix_msixoff = msix_rsp->nix_msixoff;
1176 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1178 struct rsrc_detach_req *req;
1180 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1182 /* Detach all except npa lf */
1183 req->partial = true;
1190 return otx2_mbox_process(mbox);
1194 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1196 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1197 struct rte_pci_device *pci_dev;
1198 int rc, max_entries;
1200 eth_dev->dev_ops = &otx2_eth_dev_ops;
1202 /* For secondary processes, the primary has done all the work */
1203 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1204 /* Setup callbacks for secondary process */
1205 otx2_eth_set_tx_function(eth_dev);
1206 otx2_eth_set_rx_function(eth_dev);
1210 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1212 rte_eth_copy_pci_info(eth_dev, pci_dev);
1213 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1215 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1216 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1217 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1219 /* Parse devargs string */
1220 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1222 otx2_err("Failed to parse devargs rc=%d", rc);
1226 if (!dev->mbox_active) {
1227 /* Initialize the base otx2_dev object
1228 * only if already present
1230 rc = otx2_dev_init(pci_dev, dev);
1232 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1236 /* Device generic callbacks */
1237 dev->ops = &otx2_dev_ops;
1238 dev->eth_dev = eth_dev;
1240 /* Grab the NPA LF if required */
1241 rc = otx2_npa_lf_init(pci_dev, dev);
1243 goto otx2_dev_uninit;
1245 dev->configured = 0;
1246 dev->drv_inited = true;
1247 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1248 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1251 rc = nix_lf_attach(dev);
1253 goto otx2_npa_uninit;
1255 /* Get NIX MSIX offset */
1256 rc = nix_lf_get_msix_offset(dev);
1258 goto otx2_npa_uninit;
1260 /* Register LF irq handlers */
1261 rc = otx2_nix_register_irqs(eth_dev);
1265 /* Get maximum number of supported MAC entries */
1266 max_entries = otx2_cgx_mac_max_entries_get(dev);
1267 if (max_entries < 0) {
1268 otx2_err("Failed to get max entries for mac addr");
1270 goto unregister_irq;
1273 /* For VFs, returned max_entries will be 0. But to keep default MAC
1274 * address, one entry must be allocated. So setting up to 1.
1276 if (max_entries == 0)
1279 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1280 RTE_ETHER_ADDR_LEN, 0);
1281 if (eth_dev->data->mac_addrs == NULL) {
1282 otx2_err("Failed to allocate memory for mac addr");
1284 goto unregister_irq;
1287 dev->max_mac_entries = max_entries;
1289 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1291 goto free_mac_addrs;
1293 /* Update the mac address */
1294 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1296 /* Also sync same MAC address to CGX table */
1297 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1299 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1300 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1302 if (otx2_dev_is_A0(dev)) {
1303 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1304 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1307 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1308 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1309 eth_dev->data->port_id, dev->pf, dev->vf,
1310 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1311 dev->rx_offload_capa, dev->tx_offload_capa);
1315 rte_free(eth_dev->data->mac_addrs);
1317 otx2_nix_unregister_irqs(eth_dev);
1319 otx2_eth_dev_lf_detach(dev->mbox);
1323 otx2_dev_fini(pci_dev, dev);
1325 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1330 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1332 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1333 struct rte_pci_device *pci_dev;
1336 /* Nothing to be done for secondary processes */
1337 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1341 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1342 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1343 eth_dev->data->tx_queues[i] = NULL;
1345 eth_dev->data->nb_tx_queues = 0;
1347 /* Free up RQ's and CQ's */
1348 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1349 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1350 eth_dev->data->rx_queues[i] = NULL;
1352 eth_dev->data->nb_rx_queues = 0;
1354 /* Unregister queue irqs */
1355 oxt2_nix_unregister_queue_irqs(eth_dev);
1357 rc = nix_lf_free(dev);
1359 otx2_err("Failed to free nix lf, rc=%d", rc);
1361 rc = otx2_npa_lf_fini();
1363 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1365 rte_free(eth_dev->data->mac_addrs);
1366 eth_dev->data->mac_addrs = NULL;
1367 dev->drv_inited = false;
1369 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1370 otx2_nix_unregister_irqs(eth_dev);
1372 rc = otx2_eth_dev_lf_detach(dev->mbox);
1374 otx2_err("Failed to detach resources, rc=%d", rc);
1376 /* Check if mbox close is needed */
1380 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1381 /* Will be freed later by PMD */
1382 eth_dev->data->dev_private = NULL;
1386 otx2_dev_fini(pci_dev, dev);
1391 nix_remove(struct rte_pci_device *pci_dev)
1393 struct rte_eth_dev *eth_dev;
1394 struct otx2_idev_cfg *idev;
1395 struct otx2_dev *otx2_dev;
1398 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1400 /* Cleanup eth dev */
1401 rc = otx2_eth_dev_uninit(eth_dev, true);
1405 rte_eth_dev_pci_release(eth_dev);
1408 /* Nothing to be done for secondary processes */
1409 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1412 /* Check for common resources */
1413 idev = otx2_intra_dev_get_cfg();
1414 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1417 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1419 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1422 /* Safe to cleanup mbox as no more users */
1423 otx2_dev_fini(pci_dev, otx2_dev);
1428 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1433 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1437 RTE_SET_USED(pci_drv);
1439 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
1442 /* On error on secondary, recheck if port exists in primary or
1443 * in mid of detach state.
1445 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1446 if (!rte_eth_dev_allocated(pci_dev->device.name))
1451 static const struct rte_pci_id pci_nix_map[] = {
1453 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
1456 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
1459 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1460 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
1467 static struct rte_pci_driver pci_nix = {
1468 .id_table = pci_nix_map,
1469 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
1470 RTE_PCI_DRV_INTR_LSC,
1472 .remove = nix_remove,
1475 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
1476 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
1477 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");