1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
18 otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
20 RTE_SET_USED(eth_dev);
24 otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)
26 RTE_SET_USED(eth_dev);
29 static inline uint64_t
30 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
34 if (otx2_dev_is_vf(dev))
35 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
40 static inline uint64_t
41 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
45 return NIX_TX_OFFLOAD_CAPA;
48 static const struct otx2_dev_ops otx2_dev_ops = {
49 .link_status_update = otx2_eth_dev_link_status_update,
53 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
55 struct otx2_mbox *mbox = dev->mbox;
56 struct nix_lf_alloc_req *req;
57 struct nix_lf_alloc_rsp *rsp;
60 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
64 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
65 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
66 req->xqe_sz = NIX_XQESZ_W16;
67 req->rss_sz = dev->rss_info.rss_size;
68 req->rss_grps = NIX_RSS_GRPS;
69 req->npa_func = otx2_npa_pf_func_get();
70 req->sso_func = otx2_sso_pf_func_get();
71 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
72 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
73 DEV_RX_OFFLOAD_UDP_CKSUM)) {
74 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
75 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
78 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
82 dev->sqb_size = rsp->sqb_size;
83 dev->tx_chan_base = rsp->tx_chan_base;
84 dev->rx_chan_base = rsp->rx_chan_base;
85 dev->rx_chan_cnt = rsp->rx_chan_cnt;
86 dev->tx_chan_cnt = rsp->tx_chan_cnt;
87 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
88 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
89 dev->lf_tx_stats = rsp->lf_tx_stats;
90 dev->lf_rx_stats = rsp->lf_rx_stats;
91 dev->cints = rsp->cints;
92 dev->qints = rsp->qints;
93 dev->npc_flow.channel = dev->rx_chan_base;
99 nix_lf_free(struct otx2_eth_dev *dev)
101 struct otx2_mbox *mbox = dev->mbox;
102 struct nix_lf_free_req *req;
103 struct ndc_sync_op *ndc_req;
106 /* Sync NDC-NIX for LF */
107 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
108 ndc_req->nix_lf_tx_sync = 1;
109 ndc_req->nix_lf_rx_sync = 1;
110 rc = otx2_mbox_process(mbox);
112 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
114 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
115 /* Let AF driver free all this nix lf's
116 * NPC entries allocated using NPC MBOX.
120 return otx2_mbox_process(mbox);
124 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
130 static inline uint32_t
131 nix_qsize_to_val(enum nix_q_size_e qsize)
133 return (16UL << (qsize * 2));
136 static inline enum nix_q_size_e
137 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
141 if (otx2_ethdev_fixup_is_min_4k_q(dev))
146 for (; i < nix_q_size_max; i++)
147 if (val <= nix_qsize_to_val(i))
150 if (i >= nix_q_size_max)
151 i = nix_q_size_max - 1;
157 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
158 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
160 struct otx2_mbox *mbox = dev->mbox;
161 const struct rte_memzone *rz;
162 uint32_t ring_size, cq_size;
163 struct nix_aq_enq_req *aq;
168 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
169 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
170 NIX_CQ_ALIGN, dev->node);
172 otx2_err("Failed to allocate mem for cq hw ring");
176 memset(rz->addr, 0, rz->len);
177 rxq->desc = (uintptr_t)rz->addr;
178 rxq->qmask = cq_size - 1;
180 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
182 aq->ctype = NIX_AQ_CTYPE_CQ;
183 aq->op = NIX_AQ_INSTOP_INIT;
187 aq->cq.qsize = rxq->qsize;
188 aq->cq.base = rz->iova;
189 aq->cq.avg_level = 0xff;
190 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
191 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
193 /* Many to one reduction */
194 aq->cq.qint_idx = qid % dev->qints;
196 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
197 uint16_t min_rx_drop;
198 const float rx_cq_skid = 1024 * 256;
200 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
201 aq->cq.drop = min_rx_drop;
205 rc = otx2_mbox_process(mbox);
207 otx2_err("Failed to init cq context");
211 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
213 aq->ctype = NIX_AQ_CTYPE_RQ;
214 aq->op = NIX_AQ_INSTOP_INIT;
217 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
219 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
220 first_skip = (sizeof(struct rte_mbuf));
221 first_skip += RTE_PKTMBUF_HEADROOM;
222 first_skip += rte_pktmbuf_priv_size(mp);
223 rxq->data_off = first_skip;
225 first_skip /= 8; /* Expressed in number of dwords */
226 aq->rq.first_skip = first_skip;
227 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
228 aq->rq.flow_tagw = 32; /* 32-bits */
229 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
230 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
231 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
232 aq->rq.lpb_sizem1 /= 8;
233 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
235 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
236 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
237 aq->rq.rq_int_ena = 0;
238 /* Many to one reduction */
239 aq->rq.qint_idx = qid % dev->qints;
241 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
242 aq->rq.xqe_drop_ena = 1;
244 rc = otx2_mbox_process(mbox);
246 otx2_err("Failed to init rq context");
256 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
257 struct otx2_eth_rxq *rxq, const bool enb)
259 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
260 struct otx2_mbox *mbox = dev->mbox;
261 struct nix_aq_enq_req *aq;
263 /* Pkts will be dropped silently if RQ is disabled */
264 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
266 aq->ctype = NIX_AQ_CTYPE_RQ;
267 aq->op = NIX_AQ_INSTOP_WRITE;
270 aq->rq_mask.ena = ~(aq->rq_mask.ena);
272 return otx2_mbox_process(mbox);
276 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
278 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
279 struct otx2_mbox *mbox = dev->mbox;
280 struct nix_aq_enq_req *aq;
283 /* RQ is already disabled */
285 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
287 aq->ctype = NIX_AQ_CTYPE_CQ;
288 aq->op = NIX_AQ_INSTOP_WRITE;
291 aq->cq_mask.ena = ~(aq->cq_mask.ena);
293 rc = otx2_mbox_process(mbox);
295 otx2_err("Failed to disable cq context");
303 nix_get_data_off(struct otx2_eth_dev *dev)
311 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
313 struct rte_mbuf mb_def;
316 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
317 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
318 offsetof(struct rte_mbuf, data_off) != 2);
319 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
320 offsetof(struct rte_mbuf, data_off) != 4);
321 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
322 offsetof(struct rte_mbuf, data_off) != 6);
324 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
325 mb_def.port = port_id;
326 rte_mbuf_refcnt_set(&mb_def, 1);
328 /* Prevent compiler reordering: rearm_data covers previous fields */
329 rte_compiler_barrier();
330 tmp = (uint64_t *)&mb_def.rearm_data;
336 otx2_nix_rx_queue_release(void *rx_queue)
338 struct otx2_eth_rxq *rxq = rx_queue;
343 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
344 nix_cq_rq_uninit(rxq->eth_dev, rxq);
349 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
350 uint16_t nb_desc, unsigned int socket,
351 const struct rte_eth_rxconf *rx_conf,
352 struct rte_mempool *mp)
354 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
355 struct rte_mempool_ops *ops;
356 struct otx2_eth_rxq *rxq;
357 const char *platform_ops;
358 enum nix_q_size_e qsize;
364 /* Compile time check to make sure all fast path elements in a CL */
365 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
368 if (rx_conf->rx_deferred_start == 1) {
369 otx2_err("Deferred Rx start is not supported");
373 platform_ops = rte_mbuf_platform_mempool_ops();
374 /* This driver needs octeontx2_npa mempool ops to work */
375 ops = rte_mempool_get_ops(mp->ops_index);
376 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
377 otx2_err("mempool ops should be of octeontx2_npa type");
381 if (mp->pool_id == 0) {
382 otx2_err("Invalid pool_id");
386 /* Free memory prior to re-allocation if needed */
387 if (eth_dev->data->rx_queues[rq] != NULL) {
388 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
389 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
390 eth_dev->data->rx_queues[rq] = NULL;
393 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
394 dev->rx_offloads |= offloads;
396 /* Find the CQ queue size */
397 qsize = nix_qsize_clampup_get(dev, nb_desc);
398 /* Allocate rxq memory */
399 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
401 otx2_err("Failed to allocate rq=%d", rq);
406 rxq->eth_dev = eth_dev;
408 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
409 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
410 rxq->wdata = (uint64_t)rq << 32;
411 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
412 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
413 eth_dev->data->port_id);
414 rxq->offloads = offloads;
416 rxq->qlen = nix_qsize_to_val(qsize);
419 /* Alloc completion queue */
420 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
422 otx2_err("Failed to allocate rxq=%u", rq);
426 rxq->qconf.socket_id = socket;
427 rxq->qconf.nb_desc = nb_desc;
428 rxq->qconf.mempool = mp;
429 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
431 nix_rx_queue_reset(rxq);
432 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
433 rq, mp->name, qsize, nb_desc, rxq->qlen);
435 eth_dev->data->rx_queues[rq] = rxq;
436 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
440 otx2_nix_rx_queue_release(rxq);
445 static inline uint8_t
446 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
449 * Maximum three segments can be supported with W8, Choose
450 * NIX_MAXSQESZ_W16 for multi segment offload.
452 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
453 return NIX_MAXSQESZ_W16;
455 return NIX_MAXSQESZ_W8;
459 nix_sq_init(struct otx2_eth_txq *txq)
461 struct otx2_eth_dev *dev = txq->dev;
462 struct otx2_mbox *mbox = dev->mbox;
463 struct nix_aq_enq_req *sq;
465 if (txq->sqb_pool->pool_id == 0)
468 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
470 sq->ctype = NIX_AQ_CTYPE_SQ;
471 sq->op = NIX_AQ_INSTOP_INIT;
472 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
474 sq->sq.default_chan = dev->tx_chan_base;
475 sq->sq.sqe_stype = NIX_STYPE_STF;
477 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
478 sq->sq.sqe_stype = NIX_STYPE_STP;
480 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
481 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
482 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
483 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
484 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
486 /* Many to one reduction */
487 sq->sq.qint_idx = txq->sq % dev->qints;
489 return otx2_mbox_process(mbox);
493 nix_sq_uninit(struct otx2_eth_txq *txq)
495 struct otx2_eth_dev *dev = txq->dev;
496 struct otx2_mbox *mbox = dev->mbox;
497 struct ndc_sync_op *ndc_req;
498 struct nix_aq_enq_rsp *rsp;
499 struct nix_aq_enq_req *aq;
500 uint16_t sqes_per_sqb;
504 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
506 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
508 aq->ctype = NIX_AQ_CTYPE_SQ;
509 aq->op = NIX_AQ_INSTOP_READ;
511 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
515 /* Check if sq is already cleaned up */
520 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
522 aq->ctype = NIX_AQ_CTYPE_SQ;
523 aq->op = NIX_AQ_INSTOP_WRITE;
525 aq->sq_mask.ena = ~aq->sq_mask.ena;
528 rc = otx2_mbox_process(mbox);
532 /* Read SQ and free sqb's */
533 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
535 aq->ctype = NIX_AQ_CTYPE_SQ;
536 aq->op = NIX_AQ_INSTOP_READ;
538 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
543 otx2_err("SQ has pending sqe's");
545 count = aq->sq.sqb_count;
546 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
547 /* Free SQB's that are used */
548 sqb_buf = (void *)rsp->sq.head_sqb;
552 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
553 nix_sq_max_sqe_sz(txq)));
554 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
560 /* Free next to use sqb */
561 if (rsp->sq.next_sqb)
562 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
565 /* Sync NDC-NIX-TX for LF */
566 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
567 ndc_req->nix_lf_tx_sync = 1;
568 rc = otx2_mbox_process(mbox);
570 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
576 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
578 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
579 struct npa_aq_enq_req *aura_req;
581 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
582 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
583 aura_req->ctype = NPA_AQ_CTYPE_AURA;
584 aura_req->op = NPA_AQ_INSTOP_WRITE;
586 aura_req->aura.limit = nb_sqb_bufs;
587 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
589 return otx2_mbox_process(npa_lf->mbox);
593 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
595 struct otx2_eth_dev *dev = txq->dev;
596 uint16_t sqes_per_sqb, nb_sqb_bufs;
597 char name[RTE_MEMPOOL_NAMESIZE];
598 struct rte_mempool_objsz sz;
599 struct npa_aura_s *aura;
600 uint32_t tmp, blk_sz;
602 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
603 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
604 blk_sz = dev->sqb_size;
606 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
607 sqes_per_sqb = (dev->sqb_size / 8) / 16;
609 sqes_per_sqb = (dev->sqb_size / 8) / 8;
611 nb_sqb_bufs = nb_desc / sqes_per_sqb;
612 /* Clamp up to devarg passed SQB count */
613 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
614 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
616 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
618 MEMPOOL_F_NO_SPREAD);
619 txq->nb_sqb_bufs = nb_sqb_bufs;
620 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
621 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
622 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
623 txq->nb_sqb_bufs_adj =
624 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
626 if (txq->sqb_pool == NULL) {
627 otx2_err("Failed to allocate sqe mempool");
631 memset(aura, 0, sizeof(*aura));
633 aura->fc_addr = txq->fc_iova;
634 aura->fc_hyst_bits = 0; /* Store count on all updates */
635 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
636 otx2_err("Failed to set ops for sqe mempool");
639 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
640 otx2_err("Failed to populate sqe mempool");
644 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
645 if (dev->sqb_size != sz.elt_size) {
646 otx2_err("sqe pool block size is not expected %d != %d",
651 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
659 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
661 struct nix_send_ext_s *send_hdr_ext;
662 struct nix_send_hdr_s *send_hdr;
663 struct nix_send_mem_s *send_mem;
664 union nix_send_sg_s *sg;
666 /* Initialize the fields based on basic single segment packet */
667 memset(&txq->cmd, 0, sizeof(txq->cmd));
669 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
670 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
671 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
672 send_hdr->w0.sizem1 = 2;
674 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
675 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
676 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
677 /* Default: one seg packet would have:
678 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
681 send_hdr->w0.sizem1 = 3;
682 send_hdr_ext->w0.tstmp = 1;
684 /* To calculate the offset for send_mem,
685 * send_hdr->w0.sizem1 * 2
687 send_mem = (struct nix_send_mem_s *)(txq->cmd +
688 (send_hdr->w0.sizem1 << 1));
689 send_mem->subdc = NIX_SUBDC_MEM;
691 send_mem->wmem = 0x1;
692 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
694 sg = (union nix_send_sg_s *)&txq->cmd[4];
696 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
697 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
698 send_hdr->w0.sizem1 = 1;
699 sg = (union nix_send_sg_s *)&txq->cmd[2];
702 send_hdr->w0.sq = txq->sq;
703 sg->subdc = NIX_SUBDC_SG;
705 sg->ld_type = NIX_SENDLDTYPE_LDD;
711 otx2_nix_tx_queue_release(void *_txq)
713 struct otx2_eth_txq *txq = _txq;
718 otx2_nix_dbg("Releasing txq %u", txq->sq);
720 /* Free sqb's and disable sq */
724 rte_mempool_free(txq->sqb_pool);
725 txq->sqb_pool = NULL;
732 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
733 uint16_t nb_desc, unsigned int socket_id,
734 const struct rte_eth_txconf *tx_conf)
736 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
737 const struct rte_memzone *fc;
738 struct otx2_eth_txq *txq;
744 /* Compile time check to make sure all fast path elements in a CL */
745 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
747 if (tx_conf->tx_deferred_start) {
748 otx2_err("Tx deferred start is not supported");
752 /* Free memory prior to re-allocation if needed. */
753 if (eth_dev->data->tx_queues[sq] != NULL) {
754 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
755 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
756 eth_dev->data->tx_queues[sq] = NULL;
759 /* Find the expected offloads for this queue */
760 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
762 /* Allocating tx queue data structure */
763 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
764 OTX2_ALIGN, socket_id);
766 otx2_err("Failed to alloc txq=%d", sq);
772 txq->sqb_pool = NULL;
773 txq->offloads = offloads;
774 dev->tx_offloads |= offloads;
777 * Allocate memory for flow control updates from HW.
778 * Alloc one cache line, so that fits all FC_STYPE modes.
780 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
781 OTX2_ALIGN + sizeof(struct npa_aura_s),
782 OTX2_ALIGN, dev->node);
784 otx2_err("Failed to allocate mem for fcmem");
788 txq->fc_iova = fc->iova;
789 txq->fc_mem = fc->addr;
791 /* Initialize the aura sqb pool */
792 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
794 otx2_err("Failed to alloc sqe pool rc=%d", rc);
798 /* Initialize the SQ */
799 rc = nix_sq_init(txq);
801 otx2_err("Failed to init sq=%d context", sq);
805 txq->fc_cache_pkts = 0;
806 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
807 /* Evenly distribute LMT slot for each sq */
808 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
810 txq->qconf.socket_id = socket_id;
811 txq->qconf.nb_desc = nb_desc;
812 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
814 otx2_nix_form_default_desc(txq);
816 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
817 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
818 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
819 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
820 eth_dev->data->tx_queues[sq] = txq;
821 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
825 otx2_nix_tx_queue_release(txq);
831 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
833 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
834 struct otx2_eth_qconf *tx_qconf = NULL;
835 struct otx2_eth_qconf *rx_qconf = NULL;
836 struct otx2_eth_txq **txq;
837 struct otx2_eth_rxq **rxq;
838 int i, nb_rxq, nb_txq;
840 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
841 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
843 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
844 if (tx_qconf == NULL) {
845 otx2_err("Failed to allocate memory for tx_qconf");
849 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
850 if (rx_qconf == NULL) {
851 otx2_err("Failed to allocate memory for rx_qconf");
855 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
856 for (i = 0; i < nb_txq; i++) {
857 if (txq[i] == NULL) {
858 otx2_err("txq[%d] is already released", i);
861 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
862 otx2_nix_tx_queue_release(txq[i]);
863 eth_dev->data->tx_queues[i] = NULL;
866 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
867 for (i = 0; i < nb_rxq; i++) {
868 if (rxq[i] == NULL) {
869 otx2_err("rxq[%d] is already released", i);
872 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
873 otx2_nix_rx_queue_release(rxq[i]);
874 eth_dev->data->rx_queues[i] = NULL;
877 dev->tx_qconf = tx_qconf;
878 dev->rx_qconf = rx_qconf;
891 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
893 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
894 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
895 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
896 struct otx2_eth_txq **txq;
897 struct otx2_eth_rxq **rxq;
898 int rc, i, nb_rxq, nb_txq;
900 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
901 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
904 /* Setup tx & rx queues with previous configuration so
905 * that the queues can be functional in cases like ports
906 * are started without re configuring queues.
908 * Usual re config sequence is like below:
914 * queue_configure() {
921 * In some application's control path, queue_configure() would
922 * NOT be invoked for TXQs/RXQs in port_configure().
923 * In such cases, queues can be functional after start as the
924 * queues are already setup in port_configure().
926 for (i = 0; i < nb_txq; i++) {
927 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
928 tx_qconf[i].socket_id,
929 &tx_qconf[i].conf.tx);
931 otx2_err("Failed to setup tx queue rc=%d", rc);
932 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
933 for (i -= 1; i >= 0; i--)
934 otx2_nix_tx_queue_release(txq[i]);
939 free(tx_qconf); tx_qconf = NULL;
941 for (i = 0; i < nb_rxq; i++) {
942 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
943 rx_qconf[i].socket_id,
944 &rx_qconf[i].conf.rx,
945 rx_qconf[i].mempool);
947 otx2_err("Failed to setup rx queue rc=%d", rc);
948 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
949 for (i -= 1; i >= 0; i--)
950 otx2_nix_rx_queue_release(rxq[i]);
951 goto release_tx_queues;
955 free(rx_qconf); rx_qconf = NULL;
960 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
961 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
962 otx2_nix_tx_queue_release(txq[i]);
973 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
983 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
985 /* These dummy functions are required for supporting
986 * some applications which reconfigure queues without
987 * stopping tx burst and rx burst threads(eg kni app)
988 * When the queues context is saved, txq/rxqs are released
989 * which caused app crash since rx/tx burst is still
990 * on different lcores
992 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
993 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
998 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1000 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1001 struct rte_eth_dev_data *data = eth_dev->data;
1002 struct rte_eth_conf *conf = &data->dev_conf;
1003 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1004 struct rte_eth_txmode *txmode = &conf->txmode;
1005 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1006 struct rte_ether_addr *ea;
1007 uint8_t nb_rxq, nb_txq;
1013 if (rte_eal_has_hugepages() == 0) {
1014 otx2_err("Huge page is not configured");
1018 if (rte_eal_iova_mode() != RTE_IOVA_VA) {
1019 otx2_err("iova mode should be va");
1023 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1024 otx2_err("Setting link speed/duplex not supported");
1028 if (conf->dcb_capability_en == 1) {
1029 otx2_err("dcb enable is not supported");
1033 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1034 otx2_err("Flow director is not supported");
1038 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1039 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1040 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1044 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1045 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1049 /* Free the resources allocated from the previous configure */
1050 if (dev->configured == 1) {
1051 oxt2_nix_unregister_queue_irqs(eth_dev);
1052 nix_set_nop_rxtx_function(eth_dev);
1053 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1056 otx2_nix_tm_fini(eth_dev);
1060 if (otx2_dev_is_A0(dev) &&
1061 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1062 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1063 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1064 otx2_err("Outer IP and SCTP checksum unsupported");
1069 dev->rx_offloads = rxmode->offloads;
1070 dev->tx_offloads = txmode->offloads;
1071 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1073 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1074 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1076 /* Alloc a nix lf */
1077 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1079 otx2_err("Failed to init nix_lf rc=%d", rc);
1084 rc = otx2_nix_rss_config(eth_dev);
1086 otx2_err("Failed to configure rss rc=%d", rc);
1090 /* Init the default TM scheduler hierarchy */
1091 rc = otx2_nix_tm_init_default(eth_dev);
1093 otx2_err("Failed to init traffic manager rc=%d", rc);
1097 /* Register queue IRQs */
1098 rc = oxt2_nix_register_queue_irqs(eth_dev);
1100 otx2_err("Failed to register queue interrupts rc=%d", rc);
1105 * Restore queue config when reconfigure followed by
1106 * reconfigure and no queue configure invoked from application case.
1108 if (dev->configured == 1) {
1109 rc = nix_restore_queue_cfg(eth_dev);
1114 /* Update the mac address */
1115 ea = eth_dev->data->mac_addrs;
1116 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1117 if (rte_is_zero_ether_addr(ea))
1118 rte_eth_random_addr((uint8_t *)ea);
1120 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1122 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1123 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1124 " rx_flags=0x%x tx_flags=0x%x",
1125 eth_dev->data->port_id, ea_fmt, nb_rxq,
1126 nb_txq, dev->rx_offloads, dev->tx_offloads,
1127 dev->rx_offload_flags, dev->tx_offload_flags);
1130 dev->configured = 1;
1131 dev->configured_nb_rx_qs = data->nb_rx_queues;
1132 dev->configured_nb_tx_qs = data->nb_tx_queues;
1136 rc = nix_lf_free(dev);
1142 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1144 struct rte_eth_dev_data *data = eth_dev->data;
1146 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1149 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1154 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1156 struct rte_eth_dev_data *data = eth_dev->data;
1158 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1161 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1166 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1168 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1169 struct rte_eth_dev_data *data = eth_dev->data;
1172 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1175 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1177 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1181 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1188 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1190 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1191 struct rte_eth_dev_data *data = eth_dev->data;
1194 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1197 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1199 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1203 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1209 /* Initialize and register driver with DPDK Application */
1210 static const struct eth_dev_ops otx2_eth_dev_ops = {
1211 .dev_infos_get = otx2_nix_info_get,
1212 .dev_configure = otx2_nix_configure,
1213 .link_update = otx2_nix_link_update,
1214 .tx_queue_setup = otx2_nix_tx_queue_setup,
1215 .tx_queue_release = otx2_nix_tx_queue_release,
1216 .rx_queue_setup = otx2_nix_rx_queue_setup,
1217 .rx_queue_release = otx2_nix_rx_queue_release,
1218 .tx_queue_start = otx2_nix_tx_queue_start,
1219 .tx_queue_stop = otx2_nix_tx_queue_stop,
1220 .rx_queue_start = otx2_nix_rx_queue_start,
1221 .rx_queue_stop = otx2_nix_rx_queue_stop,
1222 .stats_get = otx2_nix_dev_stats_get,
1223 .stats_reset = otx2_nix_dev_stats_reset,
1224 .get_reg = otx2_nix_dev_get_reg,
1225 .mac_addr_add = otx2_nix_mac_addr_add,
1226 .mac_addr_remove = otx2_nix_mac_addr_del,
1227 .mac_addr_set = otx2_nix_mac_addr_set,
1228 .promiscuous_enable = otx2_nix_promisc_enable,
1229 .promiscuous_disable = otx2_nix_promisc_disable,
1230 .allmulticast_enable = otx2_nix_allmulticast_enable,
1231 .allmulticast_disable = otx2_nix_allmulticast_disable,
1232 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1233 .reta_update = otx2_nix_dev_reta_update,
1234 .reta_query = otx2_nix_dev_reta_query,
1235 .rss_hash_update = otx2_nix_rss_hash_update,
1236 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1237 .xstats_get = otx2_nix_xstats_get,
1238 .xstats_get_names = otx2_nix_xstats_get_names,
1239 .xstats_reset = otx2_nix_xstats_reset,
1240 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1241 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1245 nix_lf_attach(struct otx2_eth_dev *dev)
1247 struct otx2_mbox *mbox = dev->mbox;
1248 struct rsrc_attach_req *req;
1250 /* Attach NIX(lf) */
1251 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1255 return otx2_mbox_process(mbox);
1259 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1261 struct otx2_mbox *mbox = dev->mbox;
1262 struct msix_offset_rsp *msix_rsp;
1265 /* Get NPA and NIX MSIX vector offsets */
1266 otx2_mbox_alloc_msg_msix_offset(mbox);
1268 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1270 dev->nix_msixoff = msix_rsp->nix_msixoff;
1276 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1278 struct rsrc_detach_req *req;
1280 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1282 /* Detach all except npa lf */
1283 req->partial = true;
1290 return otx2_mbox_process(mbox);
1294 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1296 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1297 struct rte_pci_device *pci_dev;
1298 int rc, max_entries;
1300 eth_dev->dev_ops = &otx2_eth_dev_ops;
1302 /* For secondary processes, the primary has done all the work */
1303 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1304 /* Setup callbacks for secondary process */
1305 otx2_eth_set_tx_function(eth_dev);
1306 otx2_eth_set_rx_function(eth_dev);
1310 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1312 rte_eth_copy_pci_info(eth_dev, pci_dev);
1313 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1315 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1316 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1317 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1319 /* Parse devargs string */
1320 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1322 otx2_err("Failed to parse devargs rc=%d", rc);
1326 if (!dev->mbox_active) {
1327 /* Initialize the base otx2_dev object
1328 * only if already present
1330 rc = otx2_dev_init(pci_dev, dev);
1332 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1336 /* Device generic callbacks */
1337 dev->ops = &otx2_dev_ops;
1338 dev->eth_dev = eth_dev;
1340 /* Grab the NPA LF if required */
1341 rc = otx2_npa_lf_init(pci_dev, dev);
1343 goto otx2_dev_uninit;
1345 dev->configured = 0;
1346 dev->drv_inited = true;
1347 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1348 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1351 rc = nix_lf_attach(dev);
1353 goto otx2_npa_uninit;
1355 /* Get NIX MSIX offset */
1356 rc = nix_lf_get_msix_offset(dev);
1358 goto otx2_npa_uninit;
1360 /* Register LF irq handlers */
1361 rc = otx2_nix_register_irqs(eth_dev);
1365 /* Get maximum number of supported MAC entries */
1366 max_entries = otx2_cgx_mac_max_entries_get(dev);
1367 if (max_entries < 0) {
1368 otx2_err("Failed to get max entries for mac addr");
1370 goto unregister_irq;
1373 /* For VFs, returned max_entries will be 0. But to keep default MAC
1374 * address, one entry must be allocated. So setting up to 1.
1376 if (max_entries == 0)
1379 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1380 RTE_ETHER_ADDR_LEN, 0);
1381 if (eth_dev->data->mac_addrs == NULL) {
1382 otx2_err("Failed to allocate memory for mac addr");
1384 goto unregister_irq;
1387 dev->max_mac_entries = max_entries;
1389 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1391 goto free_mac_addrs;
1393 /* Update the mac address */
1394 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1396 /* Also sync same MAC address to CGX table */
1397 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1399 /* Initialize the tm data structures */
1400 otx2_nix_tm_conf_init(eth_dev);
1402 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1403 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1405 if (otx2_dev_is_A0(dev)) {
1406 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1407 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1410 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1411 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1412 eth_dev->data->port_id, dev->pf, dev->vf,
1413 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1414 dev->rx_offload_capa, dev->tx_offload_capa);
1418 rte_free(eth_dev->data->mac_addrs);
1420 otx2_nix_unregister_irqs(eth_dev);
1422 otx2_eth_dev_lf_detach(dev->mbox);
1426 otx2_dev_fini(pci_dev, dev);
1428 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1433 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1435 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1436 struct rte_pci_device *pci_dev;
1439 /* Nothing to be done for secondary processes */
1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1444 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1445 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1446 eth_dev->data->tx_queues[i] = NULL;
1448 eth_dev->data->nb_tx_queues = 0;
1450 /* Free up RQ's and CQ's */
1451 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1452 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1453 eth_dev->data->rx_queues[i] = NULL;
1455 eth_dev->data->nb_rx_queues = 0;
1457 /* Free tm resources */
1458 rc = otx2_nix_tm_fini(eth_dev);
1460 otx2_err("Failed to cleanup tm, rc=%d", rc);
1462 /* Unregister queue irqs */
1463 oxt2_nix_unregister_queue_irqs(eth_dev);
1465 rc = nix_lf_free(dev);
1467 otx2_err("Failed to free nix lf, rc=%d", rc);
1469 rc = otx2_npa_lf_fini();
1471 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1473 rte_free(eth_dev->data->mac_addrs);
1474 eth_dev->data->mac_addrs = NULL;
1475 dev->drv_inited = false;
1477 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1478 otx2_nix_unregister_irqs(eth_dev);
1480 rc = otx2_eth_dev_lf_detach(dev->mbox);
1482 otx2_err("Failed to detach resources, rc=%d", rc);
1484 /* Check if mbox close is needed */
1488 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1489 /* Will be freed later by PMD */
1490 eth_dev->data->dev_private = NULL;
1494 otx2_dev_fini(pci_dev, dev);
1499 nix_remove(struct rte_pci_device *pci_dev)
1501 struct rte_eth_dev *eth_dev;
1502 struct otx2_idev_cfg *idev;
1503 struct otx2_dev *otx2_dev;
1506 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1508 /* Cleanup eth dev */
1509 rc = otx2_eth_dev_uninit(eth_dev, true);
1513 rte_eth_dev_pci_release(eth_dev);
1516 /* Nothing to be done for secondary processes */
1517 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1520 /* Check for common resources */
1521 idev = otx2_intra_dev_get_cfg();
1522 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1525 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1527 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1530 /* Safe to cleanup mbox as no more users */
1531 otx2_dev_fini(pci_dev, otx2_dev);
1536 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1541 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1545 RTE_SET_USED(pci_drv);
1547 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
1550 /* On error on secondary, recheck if port exists in primary or
1551 * in mid of detach state.
1553 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1554 if (!rte_eth_dev_allocated(pci_dev->device.name))
1559 static const struct rte_pci_id pci_nix_map[] = {
1561 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
1564 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
1567 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1568 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
1575 static struct rte_pci_driver pci_nix = {
1576 .id_table = pci_nix_map,
1577 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
1578 RTE_PCI_DRV_INTR_LSC,
1580 .remove = nix_remove,
1583 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
1584 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
1585 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");