1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
10 #include <rte_common.h>
11 #include <rte_ethdev.h>
12 #include <rte_kvargs.h>
14 #include "otx2_common.h"
17 #include "otx2_mempool.h"
20 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
22 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
24 /* Minimum CQ size should be 4K */
25 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
26 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
27 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
28 /* Limit CQ being full */
29 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
30 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
31 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
33 /* Used for struct otx2_eth_dev::flags */
34 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
36 #define NIX_MAX_SQB 512
37 #define NIX_MIN_SQB 32
38 #define NIX_RSS_RETA_SIZE 64
40 #define NIX_TX_OFFLOAD_CAPA ( \
41 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
42 DEV_TX_OFFLOAD_MT_LOCKFREE | \
43 DEV_TX_OFFLOAD_VLAN_INSERT | \
44 DEV_TX_OFFLOAD_QINQ_INSERT | \
45 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
46 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
47 DEV_TX_OFFLOAD_TCP_CKSUM | \
48 DEV_TX_OFFLOAD_UDP_CKSUM | \
49 DEV_TX_OFFLOAD_SCTP_CKSUM | \
50 DEV_TX_OFFLOAD_MULTI_SEGS | \
51 DEV_TX_OFFLOAD_IPV4_CKSUM)
53 #define NIX_RX_OFFLOAD_CAPA ( \
54 DEV_RX_OFFLOAD_CHECKSUM | \
55 DEV_RX_OFFLOAD_SCTP_CKSUM | \
56 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
57 DEV_RX_OFFLOAD_SCATTER | \
58 DEV_RX_OFFLOAD_JUMBO_FRAME | \
59 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
60 DEV_RX_OFFLOAD_VLAN_STRIP | \
61 DEV_RX_OFFLOAD_VLAN_FILTER | \
62 DEV_RX_OFFLOAD_QINQ_STRIP | \
63 DEV_RX_OFFLOAD_TIMESTAMP)
65 struct otx2_rss_info {
69 struct otx2_npc_flow_info {
70 uint16_t flow_prealloc_size;
71 uint16_t flow_max_priority;
75 OTX2_DEV; /* Base class */
76 MARKER otx2_eth_dev_data_start;
78 uint16_t rx_chan_base;
79 uint16_t tx_chan_base;
82 uint8_t lso_tsov4_idx;
83 uint8_t lso_tsov6_idx;
84 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
85 uint8_t max_mac_entries;
91 uint16_t max_sqb_count;
92 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
94 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
96 uint64_t rx_offload_capa;
97 uint64_t tx_offload_capa;
98 struct otx2_rss_info rss_info;
99 struct otx2_npc_flow_info npc_flow;
100 } __rte_cache_aligned;
102 static inline struct otx2_eth_dev *
103 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
105 return eth_dev->data->dev_private;
109 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
110 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
113 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
114 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
115 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
116 struct rte_ether_addr *addr);
118 /* Mac address handling */
119 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
120 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
123 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
124 struct otx2_eth_dev *dev);
126 #endif /* __OTX2_ETHDEV_H__ */