1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_mbuf_pool_ops.h>
7 #include "otx2_ethdev.h"
10 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
12 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
13 struct otx2_mbox *mbox = dev->mbox;
15 if (otx2_dev_is_vf(dev))
19 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
21 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
23 otx2_mbox_process(mbox);
27 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
29 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
30 struct otx2_mbox *mbox = dev->mbox;
31 struct nix_rx_mode *req;
33 if (otx2_dev_is_vf(dev))
36 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
39 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
41 otx2_mbox_process(mbox);
42 eth_dev->data->promiscuous = en;
46 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
48 otx2_nix_promisc_config(eth_dev, 1);
49 nix_cgx_promisc_config(eth_dev, 1);
53 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
55 otx2_nix_promisc_config(eth_dev, 0);
56 nix_cgx_promisc_config(eth_dev, 0);
60 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
62 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
63 struct otx2_mbox *mbox = dev->mbox;
64 struct nix_rx_mode *req;
66 if (otx2_dev_is_vf(dev))
69 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
72 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
73 else if (eth_dev->data->promiscuous)
74 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
76 otx2_mbox_process(mbox);
80 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
82 nix_allmulticast_config(eth_dev, 1);
86 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
88 nix_allmulticast_config(eth_dev, 0);
92 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
93 struct rte_eth_rxq_info *qinfo)
95 struct otx2_eth_rxq *rxq;
97 rxq = eth_dev->data->rx_queues[queue_id];
99 qinfo->mp = rxq->pool;
100 qinfo->scattered_rx = eth_dev->data->scattered_rx;
101 qinfo->nb_desc = rxq->qconf.nb_desc;
103 qinfo->conf.rx_free_thresh = 0;
104 qinfo->conf.rx_drop_en = 0;
105 qinfo->conf.rx_deferred_start = 0;
106 qinfo->conf.offloads = rxq->offloads;
110 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
111 struct rte_eth_txq_info *qinfo)
113 struct otx2_eth_txq *txq;
115 txq = eth_dev->data->tx_queues[queue_id];
117 qinfo->nb_desc = txq->qconf.nb_desc;
119 qinfo->conf.tx_thresh.pthresh = 0;
120 qinfo->conf.tx_thresh.hthresh = 0;
121 qinfo->conf.tx_thresh.wthresh = 0;
123 qinfo->conf.tx_free_thresh = 0;
124 qinfo->conf.tx_rs_thresh = 0;
125 qinfo->conf.offloads = txq->offloads;
126 qinfo->conf.tx_deferred_start = 0;
130 nix_rx_head_tail_get(struct otx2_eth_dev *dev,
131 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
135 if (head == NULL || tail == NULL)
138 reg = (((uint64_t)queue_idx) << 32);
139 val = otx2_atomic64_add_nosync(reg, (int64_t *)
140 (dev->base + NIX_LF_CQ_OP_STATUS));
141 if (val & (OP_ERR | CQ_ERR))
144 *tail = (uint32_t)(val & 0xFFFFF);
145 *head = (uint32_t)((val >> 20) & 0xFFFFF);
149 otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t queue_idx)
151 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[queue_idx];
152 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
155 nix_rx_head_tail_get(dev, &head, &tail, queue_idx);
156 return (tail - head) % rxq->qlen;
160 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)
162 /* Check given offset(queue index) has packet filled by HW */
163 if (tail > head && offset <= tail && offset >= head)
165 /* Wrap around case */
166 if (head > tail && (offset >= head || offset <= tail))
173 otx2_nix_rx_descriptor_done(void *rx_queue, uint16_t offset)
175 struct otx2_eth_rxq *rxq = rx_queue;
178 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
179 &head, &tail, rxq->rq);
181 return nix_offset_has_packet(head, tail, offset);
185 otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)
187 struct otx2_eth_rxq *rxq = rx_queue;
190 if (rxq->qlen >= offset)
193 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
194 &head, &tail, rxq->rq);
196 if (nix_offset_has_packet(head, tail, offset))
197 return RTE_ETH_RX_DESC_DONE;
199 return RTE_ETH_RX_DESC_AVAIL;
202 /* It is a NOP for octeontx2 as HW frees the buffer on xmit */
204 otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
207 RTE_SET_USED(free_cnt);
213 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
215 RTE_SET_USED(eth_dev);
217 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
223 static struct cgx_fw_data *
224 nix_get_fwdata(struct otx2_eth_dev *dev)
226 struct otx2_mbox *mbox = dev->mbox;
227 struct cgx_fw_data *rsp = NULL;
229 otx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);
231 otx2_mbox_process_msg(mbox, (void *)&rsp);
237 otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
238 struct rte_eth_dev_module_info *modinfo)
240 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
241 struct cgx_fw_data *rsp;
243 rsp = nix_get_fwdata(dev);
247 modinfo->type = rsp->fwdata.sfp_eeprom.sff_id;
248 modinfo->eeprom_len = SFP_EEPROM_SIZE;
254 otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
255 struct rte_dev_eeprom_info *info)
257 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
258 struct cgx_fw_data *rsp;
260 if (!info->data || !info->length ||
261 (info->offset + info->length > SFP_EEPROM_SIZE))
264 rsp = nix_get_fwdata(dev);
268 otx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,
275 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
277 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
278 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
280 devinfo->min_rx_bufsize = NIX_MIN_FRS;
281 devinfo->max_rx_pktlen = NIX_MAX_FRS;
282 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
283 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
284 devinfo->max_mac_addrs = dev->max_mac_entries;
285 devinfo->max_vfs = pci_dev->max_vfs;
286 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
287 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
289 devinfo->rx_offload_capa = dev->rx_offload_capa;
290 devinfo->tx_offload_capa = dev->tx_offload_capa;
291 devinfo->rx_queue_offload_capa = 0;
292 devinfo->tx_queue_offload_capa = 0;
294 devinfo->reta_size = dev->rss_info.rss_size;
295 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
296 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
298 devinfo->default_rxconf = (struct rte_eth_rxconf) {
303 devinfo->default_txconf = (struct rte_eth_txconf) {
307 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
308 .nb_max = UINT16_MAX,
309 .nb_min = NIX_RX_MIN_DESC,
310 .nb_align = NIX_RX_MIN_DESC_ALIGN,
311 .nb_seg_max = NIX_RX_NB_SEG_MAX,
312 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
314 devinfo->rx_desc_lim.nb_max =
315 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
316 NIX_RX_MIN_DESC_ALIGN);
318 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
319 .nb_max = UINT16_MAX,
322 .nb_seg_max = NIX_TX_NB_SEG_MAX,
323 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
326 /* Auto negotiation disabled */
327 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
328 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
329 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
330 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
332 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
333 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;