2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 /* The above registers were updated in the past only in CMT mode. Since
75 * they were found to be useful MFW started updating them from 8.7.7.0.
76 * In older MFW versions they are set to 0 which means disabled.
79 if (p_hwfn->p_dev->num_hwfns > 1) {
80 DP_NOTICE(p_hwfn, false,
81 "BAR size not configured. Assuming BAR size");
82 DP_NOTICE(p_hwfn, false,
83 "of 256kB for GRC and 512kB for DB\n");
84 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size");
88 DP_NOTICE(p_hwfn, false,
89 "of 512kB for GRC and 512kB for DB\n");
94 return 1 << (val + 15);
97 void ecore_init_dp(struct ecore_dev *p_dev,
98 u32 dp_module, u8 dp_level, void *dp_ctx)
102 p_dev->dp_level = dp_level;
103 p_dev->dp_module = dp_module;
104 p_dev->dp_ctx = dp_ctx;
105 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
106 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
108 p_hwfn->dp_level = dp_level;
109 p_hwfn->dp_module = dp_module;
110 p_hwfn->dp_ctx = dp_ctx;
114 void ecore_init_struct(struct ecore_dev *p_dev)
118 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
119 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
121 p_hwfn->p_dev = p_dev;
123 p_hwfn->b_active = false;
125 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
126 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
129 /* hwfn 0 is always active */
130 p_dev->hwfns[0].b_active = true;
132 /* set the default cache alignment to 128 (may be overridden later) */
133 p_dev->cache_shift = 7;
136 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
138 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
141 qm_info->qm_pq_params = OSAL_NULL;
142 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
143 qm_info->qm_vport_params = OSAL_NULL;
144 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
145 qm_info->qm_port_params = OSAL_NULL;
146 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
147 qm_info->wfq_data = OSAL_NULL;
150 void ecore_resc_free(struct ecore_dev *p_dev)
157 OSAL_FREE(p_dev, p_dev->fw_data);
158 p_dev->fw_data = OSAL_NULL;
160 OSAL_FREE(p_dev, p_dev->reset_stats);
162 for_each_hwfn(p_dev, i) {
163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
165 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
166 p_hwfn->p_tx_cids = OSAL_NULL;
167 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
168 p_hwfn->p_rx_cids = OSAL_NULL;
171 for_each_hwfn(p_dev, i) {
172 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
174 ecore_cxt_mngr_free(p_hwfn);
175 ecore_qm_info_free(p_hwfn);
176 ecore_spq_free(p_hwfn);
177 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
178 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
179 ecore_int_free(p_hwfn);
180 #ifdef CONFIG_ECORE_LL2
181 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
183 ecore_iov_free(p_hwfn);
184 ecore_dmae_info_free(p_hwfn);
185 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
186 /* @@@TBD Flush work-queue ? */
190 static enum _ecore_status_t ecore_init_qm_info(struct ecore_hwfn *p_hwfn,
193 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue;
194 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
195 struct init_qm_port_params *p_qm_port;
196 bool init_rdma_offload_pq = false;
197 bool init_pure_ack_pq = false;
198 bool init_ooo_pq = false;
199 u16 num_pqs, protocol_pqs;
205 /* @TMP - saving the existing min/max bw config before resetting the
206 * qm_info to restore them.
208 pf_rl = qm_info->pf_rl;
209 pf_wfq = qm_info->pf_wfq;
211 #ifdef CONFIG_ECORE_SRIOV
212 if (p_hwfn->p_dev->p_iov_info)
213 num_vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
215 OSAL_MEM_ZERO(qm_info, sizeof(*qm_info));
218 /* @TMP - Don't allocate QM queues for VFs on emulation */
219 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
220 DP_NOTICE(p_hwfn, false,
221 "Emulation - skip configuring QM queues for VFs\n");
226 /* ethernet PFs require a pq per tc. Even if only a subset of the TCs
227 * active, we want physical queues allocated for all of them, since we
228 * don't have a good recycle flow. Non ethernet PFs require only a
229 * single physical queue.
231 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
232 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
233 p_hwfn->hw_info.personality == ECORE_PCI_ETH)
234 protocol_pqs = p_hwfn->hw_info.num_hw_tc;
238 num_pqs = protocol_pqs + num_vfs + 1; /* The '1' is for pure-LB */
239 num_vports = (u8)RESC_NUM(p_hwfn, ECORE_VPORT);
241 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
242 num_pqs++; /* for RoCE queue */
243 init_rdma_offload_pq = true;
244 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) {
245 /* Due to FW assumption that rl==vport, we limit the
246 * number of rate limiters by the minimum between its
247 * allocated number and the allocated number of vports.
248 * Another limitation is the number of supported qps
249 * with rate limiters in FW.
252 (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
253 RESC_NUM(p_hwfn, ECORE_VPORT));
255 /* we subtract num_vfs because each one requires a rate
256 * limiter, and one default rate limiter.
258 if (num_pf_rls < num_vfs + 1) {
259 DP_ERR(p_hwfn, "No RL for DCQCN");
260 DP_ERR(p_hwfn, "[num_pf_rls %d num_vfs %d]\n",
261 num_pf_rls, num_vfs);
264 num_pf_rls -= num_vfs + 1;
267 num_pqs += num_pf_rls;
268 qm_info->num_pf_rls = (u8)num_pf_rls;
271 if (p_hwfn->hw_info.personality == ECORE_PCI_IWARP) {
272 num_pqs += 3; /* for iwarp queue / pure-ack / ooo */
273 init_rdma_offload_pq = true;
274 init_pure_ack_pq = true;
278 if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
279 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
280 init_pure_ack_pq = true;
284 /* Sanity checking that setup requires legal number of resources */
285 if (num_pqs > RESC_NUM(p_hwfn, ECORE_PQ)) {
287 "Need too many Physical queues - 0x%04x avail %04x",
288 num_pqs, RESC_NUM(p_hwfn, ECORE_PQ));
292 /* PQs will be arranged as follows: First per-TC PQ, then pure-LB queue,
293 * then special queues (iSCSI pure-ACK / RoCE), then per-VF PQ.
295 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev,
296 b_sleepable ? GFP_KERNEL :
298 sizeof(struct init_qm_pq_params) *
300 if (!qm_info->qm_pq_params)
303 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev,
304 b_sleepable ? GFP_KERNEL :
307 init_qm_vport_params) *
309 if (!qm_info->qm_vport_params)
312 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev,
313 b_sleepable ? GFP_KERNEL :
315 sizeof(struct init_qm_port_params)
317 if (!qm_info->qm_port_params)
320 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev,
321 b_sleepable ? GFP_KERNEL :
323 sizeof(struct ecore_wfq_data) *
326 if (!qm_info->wfq_data)
329 vport_id = (u8)RESC_START(p_hwfn, ECORE_VPORT);
331 /* First init rate limited queues ( Due to RoCE assumption of
334 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
335 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
336 qm_info->qm_pq_params[curr_queue].tc_id =
337 p_hwfn->hw_info.offload_tc;
338 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
339 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
343 for (i = 0; i < protocol_pqs; i++) {
344 struct init_qm_pq_params *params =
345 &qm_info->qm_pq_params[curr_queue++];
347 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE ||
348 p_hwfn->hw_info.personality == ECORE_PCI_IWARP ||
349 p_hwfn->hw_info.personality == ECORE_PCI_ETH) {
350 params->vport_id = vport_id;
352 /* Note: this assumes that if we had a configuration
353 * with N tcs and subsequently another configuration
354 * With Fewer TCs, the in flight traffic (in QM queues,
355 * in FW, from driver to FW) will still trickle out and
356 * not get "stuck" in the QM. This is determined by the
357 * NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ. Unused TCs are
358 * supposed to be cleared in this map, allowing traffic
359 * to flush out. If this is not the case, we would need
360 * to set the TC of unused queues to 0, and reconfigure
361 * QM every time num of TCs changes. Unused queues in
362 * this context would mean those intended for TCs where
363 * tc_id > hw_info.num_active_tcs.
365 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
367 params->vport_id = vport_id;
368 params->tc_id = p_hwfn->hw_info.offload_tc;
369 params->wrr_group = 1; /* @@@TBD ECORE_WRR_MEDIUM */
373 /* Then init pure-LB PQ */
374 qm_info->pure_lb_pq = curr_queue;
375 qm_info->qm_pq_params[curr_queue].vport_id =
376 (u8)RESC_START(p_hwfn, ECORE_VPORT);
377 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
378 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
381 qm_info->offload_pq = 0; /* Already initialized for iSCSI/FCoE */
382 if (init_rdma_offload_pq) {
383 qm_info->offload_pq = curr_queue;
384 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
385 qm_info->qm_pq_params[curr_queue].tc_id =
386 p_hwfn->hw_info.offload_tc;
387 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
391 if (init_pure_ack_pq) {
392 qm_info->pure_ack_pq = curr_queue;
393 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
394 qm_info->qm_pq_params[curr_queue].tc_id =
395 p_hwfn->hw_info.offload_tc;
396 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
401 qm_info->ooo_pq = curr_queue;
402 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
403 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
404 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
408 /* Then init per-VF PQs */
409 vf_offset = curr_queue;
410 for (i = 0; i < num_vfs; i++) {
411 /* First vport is used by the PF */
412 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
413 /* @@@TBD VF Multi-cos */
414 qm_info->qm_pq_params[curr_queue].tc_id = 0;
415 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
416 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
420 qm_info->vf_queues_offset = vf_offset;
421 qm_info->num_pqs = num_pqs;
422 qm_info->num_vports = num_vports;
424 /* Initialize qm port parameters */
425 num_ports = p_hwfn->p_dev->num_ports_in_engines;
426 for (i = 0; i < num_ports; i++) {
427 p_qm_port = &qm_info->qm_port_params[i];
428 p_qm_port->active = 1;
429 /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
433 p_qm_port->active_phys_tcs = 0xf;
435 p_qm_port->active_phys_tcs = 0x9f;
436 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
437 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
440 if (ECORE_IS_AH(p_hwfn->p_dev) && (num_ports == 4))
441 qm_info->max_phys_tcs_per_port = NUM_PHYS_TCS_4PORT_K2;
443 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
445 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
447 qm_info->num_vf_pqs = num_vfs;
448 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
450 for (i = 0; i < qm_info->num_vports; i++)
451 qm_info->qm_vport_params[i].vport_wfq = 1;
453 qm_info->vport_rl_en = 1;
454 qm_info->vport_wfq_en = 1;
455 qm_info->pf_rl = pf_rl;
456 qm_info->pf_wfq = pf_wfq;
458 return ECORE_SUCCESS;
461 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
462 ecore_qm_info_free(p_hwfn);
466 /* This function reconfigures the QM pf on the fly.
467 * For this purpose we:
468 * 1. reconfigure the QM database
469 * 2. set new values to runtime arrat
470 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
471 * 4. activate init tool in QM_PF stage
472 * 5. send an sdm_qm_cmd through rbc interface to release the QM
474 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
475 struct ecore_ptt *p_ptt)
477 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
479 enum _ecore_status_t rc;
481 /* qm_info is allocated in ecore_init_qm_info() which is already called
482 * from ecore_resc_alloc() or previous call of ecore_qm_reconf().
483 * The allocated size may change each init, so we free it before next
486 ecore_qm_info_free(p_hwfn);
488 /* initialize ecore's qm data structure */
489 rc = ecore_init_qm_info(p_hwfn, false);
490 if (rc != ECORE_SUCCESS)
493 /* stop PF's qm queues */
494 OSAL_SPIN_LOCK(&qm_lock);
495 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
496 qm_info->start_pq, qm_info->num_pqs);
497 OSAL_SPIN_UNLOCK(&qm_lock);
501 /* clear the QM_PF runtime phase leftovers from previous init */
502 ecore_init_clear_rt_data(p_hwfn);
504 /* prepare QM portion of runtime array */
505 ecore_qm_init_pf(p_hwfn);
507 /* activate init tool on runtime array */
508 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
509 p_hwfn->hw_info.hw_mode);
510 if (rc != ECORE_SUCCESS)
513 /* start PF's qm queues */
514 OSAL_SPIN_LOCK(&qm_lock);
515 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
516 qm_info->start_pq, qm_info->num_pqs);
517 OSAL_SPIN_UNLOCK(&qm_lock);
521 return ECORE_SUCCESS;
524 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
526 struct ecore_consq *p_consq;
527 struct ecore_eq *p_eq;
528 #ifdef CONFIG_ECORE_LL2
529 struct ecore_ll2_info *p_ll2_info;
531 enum _ecore_status_t rc = ECORE_SUCCESS;
537 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
538 sizeof(*p_dev->fw_data));
542 /* Allocate Memory for the Queue->CID mapping */
543 for_each_hwfn(p_dev, i) {
544 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
546 /* @@@TMP - resc management, change to actual required size */
547 int tx_size = sizeof(struct ecore_hw_cid_data) *
548 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
549 int rx_size = sizeof(struct ecore_hw_cid_data) *
550 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
552 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
554 if (!p_hwfn->p_tx_cids) {
555 DP_NOTICE(p_hwfn, true,
556 "Failed to allocate memory for Tx Cids\n");
560 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
562 if (!p_hwfn->p_rx_cids) {
563 DP_NOTICE(p_hwfn, true,
564 "Failed to allocate memory for Rx Cids\n");
569 for_each_hwfn(p_dev, i) {
570 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
571 u32 n_eqes, num_cons;
573 /* First allocate the context manager structure */
574 rc = ecore_cxt_mngr_alloc(p_hwfn);
578 /* Set the HW cid/tid numbers (in the contest manager)
579 * Must be done prior to any further computations.
581 rc = ecore_cxt_set_pf_params(p_hwfn);
585 /* Prepare and process QM requirements */
586 rc = ecore_init_qm_info(p_hwfn, true);
590 /* Compute the ILT client partition */
591 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
595 /* CID map / ILT shadow table / T2
596 * The talbes sizes are determined by the computations above
598 rc = ecore_cxt_tables_alloc(p_hwfn);
602 /* SPQ, must follow ILT because initializes SPQ context */
603 rc = ecore_spq_alloc(p_hwfn);
607 /* SP status block allocation */
608 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
611 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
615 rc = ecore_iov_alloc(p_hwfn);
620 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
621 if ((p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) ||
622 (p_hwfn->hw_info.personality == ECORE_PCI_IWARP)) {
623 /* Calculate the EQ size
624 * ---------------------
625 * Each ICID may generate up to one event at a time i.e.
626 * the event must be handled/cleared before a new one
627 * can be generated. We calculate the sum of events per
628 * protocol and create an EQ deep enough to handle the
630 * - Core - according to SPQ.
631 * - RoCE - per QP there are a couple of ICIDs, one
632 * responder and one requester, each can
633 * generate an EQE => n_eqes_qp = 2 * n_qp.
634 * Each CQ can generate an EQE. There are 2 CQs
635 * per QP => n_eqes_cq = 2 * n_qp.
636 * Hence the RoCE total is 4 * n_qp or
638 * - ENet - There can be up to two events per VF. One
639 * for VF-PF channel and another for VF FLR
640 * initial cleanup. The number of VFs is
641 * bounded by MAX_NUM_VFS_BB, and is much
642 * smaller than RoCE's so we avoid exact
645 if (p_hwfn->hw_info.personality == ECORE_PCI_ETH_ROCE) {
647 ecore_cxt_get_proto_cid_count(
653 num_cons = ecore_cxt_get_proto_cid_count(
658 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
659 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
661 ecore_cxt_get_proto_cid_count(p_hwfn,
662 PROTOCOLID_ISCSI, 0);
663 n_eqes += 2 * num_cons;
666 if (n_eqes > 0xFFFF) {
667 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
668 "The maximum of a u16 chain is 0x%x\n",
674 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
679 p_consq = ecore_consq_alloc(p_hwfn);
682 p_hwfn->p_consq = p_consq;
684 #ifdef CONFIG_ECORE_LL2
685 if (p_hwfn->using_ll2) {
686 p_ll2_info = ecore_ll2_alloc(p_hwfn);
689 p_hwfn->p_ll2_info = p_ll2_info;
693 /* DMA info initialization */
694 rc = ecore_dmae_info_alloc(p_hwfn);
696 DP_NOTICE(p_hwfn, true,
697 "Failed to allocate memory for dmae_info structure\n");
701 /* DCBX initialization */
702 rc = ecore_dcbx_info_alloc(p_hwfn);
704 DP_NOTICE(p_hwfn, true,
705 "Failed to allocate memory for dcbx structure\n");
710 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
711 sizeof(struct ecore_eth_stats));
712 if (!p_dev->reset_stats) {
713 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
717 return ECORE_SUCCESS;
722 ecore_resc_free(p_dev);
726 void ecore_resc_setup(struct ecore_dev *p_dev)
733 for_each_hwfn(p_dev, i) {
734 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
736 ecore_cxt_mngr_setup(p_hwfn);
737 ecore_spq_setup(p_hwfn);
738 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
739 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
741 /* Read shadow of current MFW mailbox */
742 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
743 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
744 p_hwfn->mcp_info->mfw_mb_cur,
745 p_hwfn->mcp_info->mfw_mb_length);
747 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
749 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
750 #ifdef CONFIG_ECORE_LL2
751 if (p_hwfn->using_ll2)
752 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
757 #define FINAL_CLEANUP_POLL_CNT (100)
758 #define FINAL_CLEANUP_POLL_TIME (10)
759 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
760 struct ecore_ptt *p_ptt,
763 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
764 enum _ecore_status_t rc = ECORE_TIMEOUT;
767 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
768 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
769 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
770 return ECORE_SUCCESS;
774 addr = GTT_BAR0_MAP_REG_USDM_RAM +
775 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
780 command |= X_FINAL_CLEANUP_AGG_INT <<
781 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
782 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
783 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
784 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
786 /* Make sure notification is not set before initiating final cleanup */
788 if (REG_RD(p_hwfn, addr)) {
789 DP_NOTICE(p_hwfn, false,
790 "Unexpected; Found final cleanup notification");
791 DP_NOTICE(p_hwfn, false,
792 " before initiating final cleanup\n");
793 REG_WR(p_hwfn, addr, 0);
796 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
797 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
798 id, OSAL_CPU_TO_LE32(command));
800 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN,
801 OSAL_CPU_TO_LE32(command));
803 /* Poll until completion */
804 while (!REG_RD(p_hwfn, addr) && count--)
805 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
807 if (REG_RD(p_hwfn, addr))
810 DP_NOTICE(p_hwfn, true,
811 "Failed to receive FW final cleanup notification\n");
813 /* Cleanup afterwards */
814 REG_WR(p_hwfn, addr, 0);
819 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
823 if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
824 hw_mode |= 1 << MODE_BB_A0;
825 } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
826 hw_mode |= 1 << MODE_BB_B0;
827 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
828 hw_mode |= 1 << MODE_K2;
830 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
831 p_hwfn->p_dev->type);
835 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
836 switch (p_hwfn->p_dev->num_ports_in_engines) {
838 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
841 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
844 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
847 DP_NOTICE(p_hwfn, true,
848 "num_ports_in_engine = %d not supported\n",
849 p_hwfn->p_dev->num_ports_in_engines);
853 switch (p_hwfn->p_dev->mf_mode) {
854 case ECORE_MF_DEFAULT:
856 hw_mode |= 1 << MODE_MF_SI;
859 hw_mode |= 1 << MODE_MF_SD;
862 DP_NOTICE(p_hwfn, true,
863 "Unsupported MF mode, init as DEFAULT\n");
864 hw_mode |= 1 << MODE_MF_SI;
868 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
869 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
870 hw_mode |= 1 << MODE_FPGA;
872 if (p_hwfn->p_dev->b_is_emul_full)
873 hw_mode |= 1 << MODE_EMUL_FULL;
875 hw_mode |= 1 << MODE_EMUL_REDUCED;
879 hw_mode |= 1 << MODE_ASIC;
881 #ifndef REAL_ASIC_ONLY
882 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn))
883 hw_mode |= 1 << MODE_EAGLE_ENG1_WORKAROUND;
886 if (p_hwfn->p_dev->num_hwfns > 1)
887 hw_mode |= 1 << MODE_100G;
889 p_hwfn->hw_info.hw_mode = hw_mode;
891 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
892 "Configuring function for hw_mode: 0x%08x\n",
893 p_hwfn->hw_info.hw_mode);
895 return ECORE_SUCCESS;
899 /* MFW-replacement initializations for non-ASIC */
900 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
901 struct ecore_ptt *p_ptt)
906 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
909 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
911 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
912 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
914 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
915 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
916 if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
917 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0, 4);
919 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
920 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
921 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
922 (p_hwfn->p_dev->num_ports_in_engines >> 1));
924 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
925 p_hwfn->p_dev->num_ports_in_engines == 4 ? 0 : 3);
929 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
930 for (i = 0; i < 100; i++) {
932 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
936 DP_NOTICE(p_hwfn, true,
937 "RBC done failed to complete in PSWRQ2\n");
939 return ECORE_SUCCESS;
943 /* Init run time data for all PFs and their VFs on an engine.
944 * TBD - for VFs - Once we have parent PF info for each VF in
945 * shmem available as CAU requires knowledge of parent PF for each VF.
947 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
949 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
952 for_each_hwfn(p_dev, i) {
953 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
954 struct ecore_igu_info *p_igu_info;
955 struct ecore_igu_block *p_block;
956 struct cau_sb_entry sb_entry;
958 p_igu_info = p_hwfn->hw_info.p_igu_info;
960 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
962 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
967 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
968 p_block->function_id, 0, 0);
969 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
974 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
975 struct ecore_ptt *p_ptt,
978 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
979 struct ecore_dev *p_dev = p_hwfn->p_dev;
980 u8 vf_id, max_num_vfs;
983 enum _ecore_status_t rc = ECORE_SUCCESS;
985 ecore_init_cau_rt_data(p_dev);
987 /* Program GTT windows */
988 ecore_gtt_init(p_hwfn);
991 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
992 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
993 if (rc != ECORE_SUCCESS)
998 if (p_hwfn->mcp_info) {
999 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1000 qm_info->pf_rl_en = 1;
1001 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1002 qm_info->pf_wfq_en = 1;
1005 ecore_qm_common_rt_init(p_hwfn,
1006 p_hwfn->p_dev->num_ports_in_engines,
1007 qm_info->max_phys_tcs_per_port,
1008 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1009 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1010 qm_info->qm_port_params);
1012 ecore_cxt_hw_init_common(p_hwfn);
1014 /* Close gate from NIG to BRB/Storm; By default they are open, but
1015 * we close them to prevent NIG from passing data to reset blocks.
1016 * Should have been done in the ENGINE phase, but init-tool lacks
1017 * proper port-pretend capabilities.
1019 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1020 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1021 ecore_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
1022 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
1023 ecore_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
1024 ecore_port_unpretend(p_hwfn, p_ptt);
1026 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1027 if (rc != ECORE_SUCCESS)
1030 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1031 * need to decide with which value, maybe runtime
1033 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1034 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1036 if (ECORE_IS_BB(p_hwfn->p_dev)) {
1037 /* Workaround clears ROCE search for all functions to prevent
1038 * involving non initialized function in processing ROCE packet.
1040 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1041 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1042 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1043 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1044 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1046 /* pretend to original PF */
1047 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1050 /* Workaround for avoiding CCFC execution error when getting packets
1051 * with CRC errors, and allowing instead the invoking of the FW error
1053 * This is not done inside the init tool since it currently can't
1054 * perform a pretending to VFs.
1056 max_num_vfs = ECORE_IS_AH(p_hwfn->p_dev) ? MAX_NUM_VFS_K2
1058 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1059 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1060 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1061 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1062 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1063 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1064 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1066 /* pretend to original PF */
1067 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1073 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1074 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1076 #define PMEG_IF_BYTE_COUNT 8
1078 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1079 struct ecore_ptt *p_ptt,
1080 u32 addr, u64 data, u8 reg_type, u8 port)
1082 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1083 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1084 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) |
1085 (8 << PMEG_IF_BYTE_COUNT),
1086 (reg_type << 25) | (addr << 8) | port,
1087 (u32)((data >> 32) & 0xffffffff),
1088 (u32)(data & 0xffffffff));
1090 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0,
1091 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB_B0) &
1092 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1093 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB_B0,
1094 (reg_type << 25) | (addr << 8) | port);
1095 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1097 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB_B0,
1098 (data >> 32) & 0xffffffff);
1101 #define XLPORT_MODE_REG (0x20a)
1102 #define XLPORT_MAC_CONTROL (0x210)
1103 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1104 #define XLPORT_ENABLE_REG (0x20b)
1106 #define XLMAC_CTRL (0x600)
1107 #define XLMAC_MODE (0x601)
1108 #define XLMAC_RX_MAX_SIZE (0x608)
1109 #define XLMAC_TX_CTRL (0x604)
1110 #define XLMAC_PAUSE_CTRL (0x60d)
1111 #define XLMAC_PFC_CTRL (0x60e)
1113 static void ecore_emul_link_init_ah(struct ecore_hwfn *p_hwfn,
1114 struct ecore_ptt *p_ptt)
1116 u8 port = p_hwfn->port_id;
1117 u32 mac_base = NWM_REG_MAC0 + (port << 2) * NWM_REG_MAC0_SIZE;
1119 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2 + (port << 2),
1120 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT) |
1121 (port << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT)
1122 | (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT));
1124 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE,
1125 1 << ETH_MAC_REG_XIF_MODE_XGMII_SHIFT);
1127 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH,
1128 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT);
1130 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH,
1131 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT);
1133 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS,
1134 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT);
1136 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS,
1137 (0xA << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT) |
1138 (8 << ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT));
1140 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG, 0xa853);
1143 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1144 struct ecore_ptt *p_ptt)
1146 u8 loopback = 0, port = p_hwfn->port_id * 2;
1148 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1150 if (ECORE_IS_AH(p_hwfn->p_dev)) {
1151 ecore_emul_link_init_ah(p_hwfn, p_ptt);
1155 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1156 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1158 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1159 /* XLMAC: SOFT RESET */
1160 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1161 /* XLMAC: Port Speed >= 10Gbps */
1162 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1163 /* XLMAC: Max Size */
1164 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1165 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1166 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1168 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1169 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1170 0x30ffffc000ULL, 0, port);
1171 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1172 port); /* XLMAC: TX_EN, RX_EN */
1173 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1174 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1175 0x1003 | (loopback << 2), 0, port);
1176 /* Enabled Parallel PFC interface */
1177 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1179 /* XLPORT port enable */
1180 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1183 static void ecore_link_init(struct ecore_hwfn *p_hwfn,
1184 struct ecore_ptt *p_ptt, u8 port)
1186 int port_offset = port ? 0x800 : 0;
1187 u32 xmac_rxctrl = 0;
1190 /* FIXME: move to common start */
1191 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1192 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1194 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1195 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1197 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1199 /* Set the number of ports on the Warp Core to 10G */
1200 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1202 /* Soft reset of XMAC */
1203 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1204 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1206 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1207 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1209 /* FIXME: move to common end */
1210 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1211 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE + port_offset, 0x20);
1213 /* Set Max packet size: initialize XMAC block register for port 0 */
1214 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE + port_offset, 0x2710);
1216 /* CRC append for Tx packets: init XMAC block register for port 1 */
1217 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO + port_offset, 0xC800);
1219 /* Enable TX and RX: initialize XMAC block register for port 1 */
1220 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL + port_offset,
1221 XMAC_REG_CTRL_TX_EN | XMAC_REG_CTRL_RX_EN);
1222 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset);
1223 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE;
1224 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL + port_offset, xmac_rxctrl);
1228 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1229 struct ecore_ptt *p_ptt,
1232 enum _ecore_status_t rc = ECORE_SUCCESS;
1234 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1236 if (rc != ECORE_SUCCESS)
1239 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1240 return ECORE_SUCCESS;
1242 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1243 if (ECORE_IS_AH(p_hwfn->p_dev))
1244 return ECORE_SUCCESS;
1245 ecore_link_init(p_hwfn, p_ptt, p_hwfn->port_id);
1246 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1247 if (p_hwfn->p_dev->num_hwfns > 1) {
1248 /* Activate OPTE in CMT */
1251 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1253 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1254 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1255 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1256 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1257 ecore_wr(p_hwfn, p_ptt,
1258 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1259 ecore_wr(p_hwfn, p_ptt,
1260 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1261 ecore_wr(p_hwfn, p_ptt,
1262 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1266 ecore_emul_link_init(p_hwfn, p_ptt);
1268 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1275 static enum _ecore_status_t
1276 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1277 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1279 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1280 u32 dpi_bit_shift, dpi_count;
1283 /* Calculate DPI size
1284 * ------------------
1285 * The PWM region contains Doorbell Pages. The first is reserverd for
1286 * the kernel for, e.g, L2. The others are free to be used by non-
1287 * trusted applications, typically from user space. Each page, called a
1288 * doorbell page is sectioned into windows that allow doorbells to be
1289 * issued in parallel by the kernel/application. The size of such a
1290 * window (a.k.a. WID) is 1kB.
1292 * 1kB WID x N WIDS = DPI page size
1293 * DPI page size x N DPIs = PWM region size
1295 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1296 * in order to ensure that two applications won't share the same page.
1297 * It also must contain at least one WID per CPU to allow parallelism.
1298 * It also must be a power of 2, since it is stored as a bit shift.
1300 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1301 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1302 * containing 4 WIDs.
1304 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1305 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1306 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1307 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1308 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1310 dpi_count = pwm_region_size / dpi_page_size;
1312 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1313 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1316 p_hwfn->dpi_size = dpi_page_size;
1317 p_hwfn->dpi_count = dpi_count;
1319 /* Update registers */
1320 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1322 if (dpi_count < min_dpis)
1323 return ECORE_NORESOURCES;
1325 return ECORE_SUCCESS;
1328 enum ECORE_ROCE_EDPM_MODE {
1329 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1330 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1331 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1334 static enum _ecore_status_t
1335 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1336 struct ecore_ptt *p_ptt)
1338 u32 pwm_regsize, norm_regsize;
1339 u32 non_pwm_conn, min_addr_reg1;
1340 u32 db_bar_size, n_cpus;
1343 int rc = ECORE_SUCCESS;
1346 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1347 if (p_hwfn->p_dev->num_hwfns > 1)
1350 /* Calculate doorbell regions
1351 * -----------------------------------
1352 * The doorbell BAR is made of two regions. The first is called normal
1353 * region and the second is called PWM region. In the normal region
1354 * each ICID has its own set of addresses so that writing to that
1355 * specific address identifies the ICID. In the Process Window Mode
1356 * region the ICID is given in the data written to the doorbell. The
1357 * above per PF register denotes the offset in the doorbell BAR in which
1358 * the PWM region begins.
1359 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1360 * non-PWM connection. The calculation below computes the total non-PWM
1361 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1362 * in units of 4,096 bytes.
1364 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1365 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1367 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1368 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1369 min_addr_reg1 = norm_regsize / 4096;
1370 pwm_regsize = db_bar_size - norm_regsize;
1372 /* Check that the normal and PWM sizes are valid */
1373 if (db_bar_size < norm_regsize) {
1374 DP_ERR(p_hwfn->p_dev,
1375 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1376 db_bar_size, norm_regsize);
1377 return ECORE_NORESOURCES;
1379 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1380 DP_ERR(p_hwfn->p_dev,
1381 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1382 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1384 return ECORE_NORESOURCES;
1387 /* Calculate number of DPIs */
1388 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1389 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1390 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1391 /* Either EDPM is mandatory, or we are attempting to allocate a
1394 n_cpus = OSAL_NUM_ACTIVE_CPU();
1395 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1398 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1399 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1400 if (cond || p_hwfn->dcbx_no_edpm) {
1401 /* Either EDPM is disabled from user configuration, or it is
1402 * disabled via DCBx, or it is not mandatory and we failed to
1403 * allocated a WID per CPU.
1406 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1408 /* If we entered this flow due to DCBX then the DPM register is
1409 * already configured.
1414 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1415 norm_regsize, pwm_regsize);
1417 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1418 p_hwfn->dpi_size, p_hwfn->dpi_count,
1419 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1420 "disabled" : "enabled");
1422 /* Check return codes from above calls */
1425 "Failed to allocate enough DPIs\n");
1426 return ECORE_NORESOURCES;
1430 p_hwfn->dpi_start_offset = norm_regsize;
1432 /* Update registers */
1433 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1434 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1435 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1436 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1438 return ECORE_SUCCESS;
1441 static enum _ecore_status_t
1442 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1443 struct ecore_ptt *p_ptt,
1444 struct ecore_tunn_start_params *p_tunn,
1447 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1449 u8 rel_pf_id = p_hwfn->rel_pf_id;
1451 enum _ecore_status_t rc = ECORE_SUCCESS;
1455 if (p_hwfn->mcp_info) {
1456 struct ecore_mcp_function_info *p_info;
1458 p_info = &p_hwfn->mcp_info->func_info;
1459 if (p_info->bandwidth_min)
1460 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1462 /* Update rate limit once we'll actually have a link */
1463 p_hwfn->qm_info.pf_rl = 100000;
1465 ecore_cxt_hw_init_pf(p_hwfn);
1467 ecore_int_igu_init_rt(p_hwfn);
1469 /* Set VLAN in NIG if needed */
1470 if (hw_mode & (1 << MODE_MF_SD)) {
1471 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1472 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1473 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1474 p_hwfn->hw_info.ovlan);
1477 /* Enable classification by MAC if needed */
1478 if (hw_mode & (1 << MODE_MF_SI)) {
1479 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1480 "Configuring TAGMAC_CLS_TYPE\n");
1481 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1485 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1486 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1487 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1488 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1489 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1490 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1492 /* perform debug configuration when chip is out of reset */
1493 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1495 /* Cleanup chip from previous driver if such remains exist */
1496 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1497 if (rc != ECORE_SUCCESS) {
1498 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1502 /* PF Init sequence */
1503 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1507 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1508 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1512 /* Pure runtime initializations - directly to the HW */
1513 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1515 /* PCI relaxed ordering causes a decrease in the performance on some
1516 * systems. Till a root cause is found, disable this attribute in the
1520 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1522 * DP_NOTICE(p_hwfn, true,
1523 * "Failed to find the PCIe Cap\n");
1526 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1527 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1528 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1531 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1535 /* enable interrupts */
1536 ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1538 /* send function start command */
1539 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1540 allow_npar_tx_switch);
1542 DP_NOTICE(p_hwfn, true,
1543 "Function start ramrod failed\n");
1545 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1546 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1547 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1549 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1550 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1552 ecore_wr(p_hwfn, p_ptt,
1553 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1556 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1557 "PRS_REG_SEARCH registers after start PFn\n");
1558 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1559 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1560 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1561 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1562 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1563 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1564 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1565 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1566 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1567 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1568 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1569 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1570 prs_reg = ecore_rd(p_hwfn, p_ptt,
1571 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1572 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1573 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1575 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1576 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1577 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1583 static enum _ecore_status_t
1584 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1585 struct ecore_ptt *p_ptt, u8 enable)
1587 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1589 /* Change PF in PXP */
1590 ecore_wr(p_hwfn, p_ptt,
1591 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1593 /* wait until value is set - try for 1 second every 50us */
1594 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1595 val = ecore_rd(p_hwfn, p_ptt,
1596 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1603 if (val != set_val) {
1604 DP_NOTICE(p_hwfn, true,
1605 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1606 return ECORE_UNKNOWN_ERROR;
1609 return ECORE_SUCCESS;
1612 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1613 struct ecore_ptt *p_main_ptt)
1615 /* Read shadow of current MFW mailbox */
1616 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1617 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1618 p_hwfn->mcp_info->mfw_mb_cur,
1619 p_hwfn->mcp_info->mfw_mb_length);
1622 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1623 struct ecore_hw_init_params *p_params)
1625 enum _ecore_status_t rc, mfw_rc;
1626 u32 load_code, param;
1629 if (p_params->int_mode == ECORE_INT_MODE_MSI && p_dev->num_hwfns > 1) {
1630 DP_NOTICE(p_dev, false,
1631 "MSI mode is not supported for CMT devices\n");
1636 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1637 if (rc != ECORE_SUCCESS)
1641 for_each_hwfn(p_dev, i) {
1642 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1645 p_hwfn->b_int_enabled = 1;
1649 /* Enable DMAE in PXP */
1650 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1651 if (rc != ECORE_SUCCESS)
1654 rc = ecore_calc_hw_mode(p_hwfn);
1655 if (rc != ECORE_SUCCESS)
1658 /* @@@TBD need to add here:
1659 * Check for fan failure
1662 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1664 DP_NOTICE(p_hwfn, true,
1665 "Failed sending LOAD_REQ command\n");
1670 * When coming back from hiberbate state, the registers from
1671 * which shadow is read initially are not initialized. It turns
1672 * out that these registers get initialized during the call to
1673 * ecore_mcp_load_req request. So we need to reread them here
1674 * to get the proper shadow register value.
1675 * Note: This is a workaround for the missinginig MFW
1676 * initialization. It may be removed once the implementation
1679 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1681 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1682 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1685 /* Only relevant for recovery:
1686 * Clear the indication after the LOAD_REQ command is responded
1689 p_dev->recov_in_prog = false;
1691 p_hwfn->first_on_engine = (load_code ==
1692 FW_MSG_CODE_DRV_LOAD_ENGINE);
1694 if (!qm_lock_init) {
1695 OSAL_SPIN_LOCK_INIT(&qm_lock);
1696 qm_lock_init = true;
1699 switch (load_code) {
1700 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1701 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1702 p_hwfn->hw_info.hw_mode);
1706 case FW_MSG_CODE_DRV_LOAD_PORT:
1707 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1708 p_hwfn->hw_info.hw_mode);
1712 #ifndef REAL_ASIC_ONLY
1713 if (ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
1714 struct init_nig_pri_tc_map_req tc_map;
1716 OSAL_MEM_ZERO(&tc_map, sizeof(tc_map));
1718 /* remove this once flow control is
1721 for (j = 0; j < NUM_OF_VLAN_PRIORITIES; j++) {
1722 tc_map.pri[j].tc_id = 0;
1723 tc_map.pri[j].valid = 1;
1725 ecore_init_nig_pri_tc_map(p_hwfn,
1731 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1732 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1734 p_hwfn->hw_info.hw_mode,
1735 p_params->b_hw_start,
1737 p_params->allow_npar_tx_switch);
1744 if (rc != ECORE_SUCCESS)
1745 DP_NOTICE(p_hwfn, true,
1746 "init phase failed for loadcode 0x%x (rc %d)\n",
1749 /* ACK mfw regardless of success or failure of initialization */
1750 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1751 DRV_MSG_CODE_LOAD_DONE,
1752 0, &load_code, ¶m);
1753 if (rc != ECORE_SUCCESS)
1755 if (mfw_rc != ECORE_SUCCESS) {
1756 DP_NOTICE(p_hwfn, true,
1757 "Failed sending LOAD_DONE command\n");
1761 ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt);
1762 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
1765 /* send DCBX attention request command */
1766 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1767 "sending phony dcbx set command to trigger DCBx attention handling\n");
1768 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1769 DRV_MSG_CODE_SET_DCBX,
1770 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1771 &load_code, ¶m);
1772 if (mfw_rc != ECORE_SUCCESS) {
1773 DP_NOTICE(p_hwfn, true,
1774 "Failed to send DCBX attention request\n");
1778 p_hwfn->hw_init_done = true;
1781 return ECORE_SUCCESS;
1784 #define ECORE_HW_STOP_RETRY_LIMIT (10)
1785 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
1786 struct ecore_hwfn *p_hwfn,
1787 struct ecore_ptt *p_ptt)
1792 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1793 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1794 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
1796 if ((!ecore_rd(p_hwfn, p_ptt,
1797 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1798 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1801 /* Dependent on number of connection/tasks, possibly
1802 * 1ms sleep is required between polls
1806 if (i == ECORE_HW_STOP_RETRY_LIMIT)
1807 DP_NOTICE(p_hwfn, true,
1808 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1809 (u8)ecore_rd(p_hwfn, p_ptt,
1810 TM_REG_PF_SCAN_ACTIVE_CONN),
1811 (u8)ecore_rd(p_hwfn, p_ptt,
1812 TM_REG_PF_SCAN_ACTIVE_TASK));
1815 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
1819 for_each_hwfn(p_dev, j) {
1820 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1821 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1823 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1827 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
1829 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
1832 for_each_hwfn(p_dev, j) {
1833 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1834 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1836 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
1839 ecore_vf_pf_int_cleanup(p_hwfn);
1843 /* mark the hw as uninitialized... */
1844 p_hwfn->hw_init_done = false;
1846 rc = ecore_sp_pf_stop(p_hwfn);
1848 DP_NOTICE(p_hwfn, true,
1849 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1851 /* perform debug action after PF stop was sent */
1852 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
1854 /* close NIG to BRB gate */
1855 ecore_wr(p_hwfn, p_ptt,
1856 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1859 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1860 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1861 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1862 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1863 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1865 /* @@@TBD - clean transmission queues (5.b) */
1866 /* @@@TBD - clean BTB (5.c) */
1868 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
1870 /* @@@TBD - verify DMAE requests are done (8) */
1872 /* Disable Attention Generation */
1873 ecore_int_igu_disable_int(p_hwfn, p_ptt);
1874 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1875 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1876 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1877 /* Need to wait 1ms to guarantee SBs are cleared */
1882 /* Disable DMAE in PXP - in CMT, this should only be done for
1883 * first hw-function, and only after all transactions have
1884 * stopped for all active hw-functions.
1886 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
1887 p_dev->hwfns[0].p_main_ptt, false);
1888 if (t_rc != ECORE_SUCCESS)
1895 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
1899 for_each_hwfn(p_dev, j) {
1900 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
1901 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1904 ecore_vf_pf_int_cleanup(p_hwfn);
1908 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
1909 "Shutting down the fastpath\n");
1911 ecore_wr(p_hwfn, p_ptt,
1912 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1914 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1915 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1916 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1917 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1918 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1920 /* @@@TBD - clean transmission queues (5.b) */
1921 /* @@@TBD - clean BTB (5.c) */
1923 /* @@@TBD - verify DMAE requests are done (8) */
1925 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1926 /* Need to wait 1ms to guarantee SBs are cleared */
1931 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
1933 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
1935 if (IS_VF(p_hwfn->p_dev))
1938 /* If roce info is allocated it means roce is initialized and should
1939 * be enabled in searcher.
1941 if (p_hwfn->p_rdma_info) {
1942 if (p_hwfn->b_rdma_enabled_in_prs)
1943 ecore_wr(p_hwfn, p_ptt,
1944 p_hwfn->rdma_prs_search_reg, 0x1);
1945 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
1948 /* Re-open incoming traffic */
1949 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
1950 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1953 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
1954 struct ecore_ptt *p_ptt, u32 reg,
1957 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
1959 if (assert_val != expected) {
1960 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
1962 return ECORE_UNKNOWN_ERROR;
1968 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
1970 enum _ecore_status_t rc = ECORE_SUCCESS;
1971 u32 unload_resp, unload_param;
1974 for_each_hwfn(p_dev, i) {
1975 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1978 rc = ecore_vf_pf_reset(p_hwfn);
1984 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
1986 /* Check for incorrect states */
1987 if (!p_dev->recov_in_prog) {
1988 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1989 QM_REG_USG_CNT_PF_TX, 0);
1990 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1991 QM_REG_USG_CNT_PF_OTHER, 0);
1992 /* @@@TBD - assert on incorrect xCFC values (10.b) */
1995 /* Disable PF in HW blocks */
1996 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1997 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1999 if (p_dev->recov_in_prog) {
2000 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2001 "Recovery is in progress -> skip sending unload_req/done\n");
2005 /* Send unload command to MCP */
2006 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2007 DRV_MSG_CODE_UNLOAD_REQ,
2008 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2009 &unload_resp, &unload_param);
2010 if (rc != ECORE_SUCCESS) {
2011 DP_NOTICE(p_hwfn, true,
2012 "ecore_hw_reset: UNLOAD_REQ failed\n");
2013 /* @@TBD - what to do? for now, assume ENG. */
2014 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2017 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2018 DRV_MSG_CODE_UNLOAD_DONE,
2019 0, &unload_resp, &unload_param);
2020 if (rc != ECORE_SUCCESS) {
2022 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2023 /* @@@TBD - Should it really ASSERT here ? */
2031 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2032 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2034 ecore_ptt_pool_free(p_hwfn);
2035 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2038 /* Setup bar access */
2039 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2041 /* clear indirect access */
2042 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2043 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2044 PGLUE_B_REG_PGL_ADDR_E8_F0, 0);
2045 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2046 PGLUE_B_REG_PGL_ADDR_EC_F0, 0);
2047 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2048 PGLUE_B_REG_PGL_ADDR_F0_F0, 0);
2049 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2050 PGLUE_B_REG_PGL_ADDR_F4_F0, 0);
2052 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2053 PGLUE_B_REG_PGL_ADDR_88_F0, 0);
2054 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2055 PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
2056 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2057 PGLUE_B_REG_PGL_ADDR_90_F0, 0);
2058 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2059 PGLUE_B_REG_PGL_ADDR_94_F0, 0);
2062 /* Clean Previous errors if such exist */
2063 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2064 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2066 /* enable internal target-read */
2067 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2068 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2071 static void get_function_id(struct ecore_hwfn *p_hwfn)
2074 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2075 PXP_PF_ME_OPAQUE_ADDR);
2077 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2079 /* Bits 16-19 from the ME registers are the pf_num */
2080 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2081 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2082 PXP_CONCRETE_FID_PFID);
2083 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2084 PXP_CONCRETE_FID_PORT);
2086 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2087 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2088 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2091 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2093 u32 *feat_num = p_hwfn->hw_info.feat_num;
2094 int num_features = 1;
2096 /* L2 Queues require each: 1 status block. 1 L2 queue */
2097 feat_num[ECORE_PF_L2_QUE] =
2099 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2100 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2102 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2103 "#PF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2104 feat_num[ECORE_PF_L2_QUE],
2105 feat_num[ECORE_RDMA_CNQ],
2106 RESC_NUM(p_hwfn, ECORE_SB), num_features);
2109 static enum resource_id_enum
2110 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2112 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2116 mfw_res_id = RESOURCE_NUM_SB_E;
2118 case ECORE_L2_QUEUE:
2119 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2122 mfw_res_id = RESOURCE_NUM_VPORT_E;
2125 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2128 mfw_res_id = RESOURCE_NUM_PQ_E;
2131 mfw_res_id = RESOURCE_NUM_RL_E;
2135 /* Each VFC resource can accommodate both a MAC and a VLAN */
2136 mfw_res_id = RESOURCE_VFC_FILTER_E;
2139 mfw_res_id = RESOURCE_ILT_E;
2141 case ECORE_LL2_QUEUE:
2142 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2144 case ECORE_RDMA_CNQ_RAM:
2145 case ECORE_CMDQS_CQS:
2146 /* CNQ/CMDQS are the same resource */
2147 mfw_res_id = RESOURCE_CQS_E;
2149 case ECORE_RDMA_STATS_QUEUE:
2150 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2159 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2160 enum ecore_resources res_id)
2162 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2163 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2164 struct ecore_sb_cnt_info sb_cnt_info;
2165 u32 dflt_resc_num = 0;
2169 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2170 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2171 dflt_resc_num = sb_cnt_info.sb_cnt;
2173 case ECORE_L2_QUEUE:
2174 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2175 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2178 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2179 MAX_NUM_VPORTS_BB) / num_funcs;
2182 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2183 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2186 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2187 MAX_QM_TX_QUEUES_BB) / num_funcs;
2190 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2194 /* Each VFC resource can accommodate both a MAC and a VLAN */
2195 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2198 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2199 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2201 case ECORE_LL2_QUEUE:
2202 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2204 case ECORE_RDMA_CNQ_RAM:
2205 case ECORE_CMDQS_CQS:
2206 /* CNQ/CMDQS are the same resource */
2208 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2210 case ECORE_RDMA_STATS_QUEUE:
2212 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2213 MAX_NUM_VPORTS_BB) / num_funcs;
2219 return dflt_resc_num;
2222 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2223 enum ecore_resources res_id,
2224 bool drv_resc_alloc)
2226 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2227 u32 *p_resc_num, *p_resc_start;
2228 struct resource_info resc_info;
2229 enum _ecore_status_t rc;
2231 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2232 p_resc_start = &RESC_START(p_hwfn, res_id);
2234 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2235 if (!dflt_resc_num) {
2236 DP_ERR(p_hwfn, "Failed to get default amount for resource %d\n",
2240 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2243 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2244 *p_resc_num = dflt_resc_num;
2245 *p_resc_start = dflt_resc_start;
2250 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2251 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2252 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2254 "Failed to match resource %d with MFW resources\n",
2259 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2260 &mcp_resp, &mcp_param);
2261 if (rc != ECORE_SUCCESS) {
2262 DP_NOTICE(p_hwfn, true,
2263 "MFW resp failure for a resc alloc req [res_id %d]\n",
2268 /* Default driver values are applied in the following cases:
2269 * - The resource allocation MB command is not supported by the MFW
2270 * - There is an internal error in the MFW while processing the request
2271 * - The resource ID is unknown to the MFW
2273 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2274 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2277 "No allocation info for resc %d [mcp_resp 0x%x].",
2280 "Applying default values [num %d, start %d].\n",
2281 dflt_resc_num, dflt_resc_start);
2283 *p_resc_num = dflt_resc_num;
2284 *p_resc_start = dflt_resc_start;
2288 /* TBD - remove this when revising the handling of the SB resource */
2289 if (res_id == ECORE_SB) {
2290 /* Excluding the slowpath SB */
2291 resc_info.size -= 1;
2292 resc_info.offset -= p_hwfn->enabled_func_idx;
2295 *p_resc_num = resc_info.size;
2296 *p_resc_start = resc_info.offset;
2298 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2299 DP_NOTICE(p_hwfn, false,
2300 "Resource %d: MFW allocation [num %d, start %d]",
2301 res_id, *p_resc_num, *p_resc_start);
2302 DP_NOTICE(p_hwfn, false,
2303 "differs from default values [num %d, start %d]%s\n",
2306 drv_resc_alloc ? " - applying default values" : "");
2307 if (drv_resc_alloc) {
2308 *p_resc_num = dflt_resc_num;
2309 *p_resc_start = dflt_resc_start;
2313 return ECORE_SUCCESS;
2316 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2321 case ECORE_L2_QUEUE:
2335 case ECORE_RDMA_CNQ_RAM:
2336 return "RDMA_CNQ_RAM";
2339 case ECORE_LL2_QUEUE:
2341 case ECORE_CMDQS_CQS:
2343 case ECORE_RDMA_STATS_QUEUE:
2344 return "RDMA_STATS_QUEUE";
2346 return "UNKNOWN_RESOURCE";
2350 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2351 bool drv_resc_alloc)
2353 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2354 enum _ecore_status_t rc;
2357 u32 *resc_start = p_hwfn->hw_info.resc_start;
2358 u32 *resc_num = p_hwfn->hw_info.resc_num;
2359 /* For AH, an equal share of the ILT lines between the maximal number of
2360 * PFs is not enough for RoCE. This would be solved by the future
2361 * resource allocation scheme, but isn't currently present for
2362 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2363 * to work - the BB number of ILT lines divided by its max PFs number.
2365 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2368 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2369 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2370 if (rc != ECORE_SUCCESS)
2375 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2376 /* Reduced build contains less PQs */
2377 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2378 resc_num[ECORE_PQ] = 32;
2379 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2380 p_hwfn->enabled_func_idx;
2383 /* For AH emulation, since we have a possible maximal number of
2384 * 16 enabled PFs, in case there are not enough ILT lines -
2385 * allocate only first PF as RoCE and have all the other ETH
2386 * only with less ILT lines.
2388 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2389 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2390 resc_num[ECORE_ILT],
2391 roce_min_ilt_lines);
2394 /* Correct the common ILT calculation if PF0 has more */
2395 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2396 p_hwfn->p_dev->b_is_emul_full &&
2397 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2398 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2399 resc_num[ECORE_ILT];
2402 /* Sanity for ILT */
2403 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2404 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2405 DP_NOTICE(p_hwfn, true,
2406 "Can't assign ILT pages [%08x,...,%08x]\n",
2407 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2413 ecore_hw_set_feat(p_hwfn);
2415 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2416 "The numbers for each resource are:\n");
2417 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2418 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2419 ecore_hw_get_resc_name(res_id),
2420 RESC_NUM(p_hwfn, res_id),
2421 RESC_START(p_hwfn, res_id));
2423 return ECORE_SUCCESS;
2426 static enum _ecore_status_t ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2427 struct ecore_ptt *p_ptt)
2429 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2430 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2431 struct ecore_mcp_link_params *link;
2433 /* Read global nvm_cfg address */
2434 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2436 /* Verify MCP has initialized it */
2437 if (!nvm_cfg_addr) {
2438 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2442 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2444 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2446 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2447 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2450 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2452 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2453 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2454 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2455 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2457 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2458 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2460 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2461 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2463 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2464 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2466 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2467 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2469 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2470 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2472 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2473 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2475 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2476 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2478 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2479 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2481 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2482 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2485 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2490 /* Read default link configuration */
2491 link = &p_hwfn->mcp_info->link_input;
2492 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2493 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2494 link_temp = ecore_rd(p_hwfn, p_ptt,
2496 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2497 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2498 link->speed.advertised_speeds = link_temp;
2500 link_temp = link->speed.advertised_speeds;
2501 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2503 link_temp = ecore_rd(p_hwfn, p_ptt,
2505 OFFSETOF(struct nvm_cfg1_port, link_settings));
2506 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2507 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2508 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2509 link->speed.autoneg = true;
2511 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2512 link->speed.forced_speed = 1000;
2514 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2515 link->speed.forced_speed = 10000;
2517 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2518 link->speed.forced_speed = 25000;
2520 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2521 link->speed.forced_speed = 40000;
2523 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2524 link->speed.forced_speed = 50000;
2526 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2527 link->speed.forced_speed = 100000;
2530 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2533 p_hwfn->mcp_info->link_capabilities.default_speed =
2534 link->speed.forced_speed;
2535 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2536 link->speed.autoneg;
2538 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2539 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2540 link->pause.autoneg = !!(link_temp &
2541 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2542 link->pause.forced_rx = !!(link_temp &
2543 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2544 link->pause.forced_tx = !!(link_temp &
2545 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2546 link->loopback_mode = 0;
2548 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2549 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2550 link->speed.forced_speed, link->speed.advertised_speeds,
2551 link->speed.autoneg, link->pause.autoneg);
2553 /* Read Multi-function information from shmem */
2554 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2555 OFFSETOF(struct nvm_cfg1, glob) +
2556 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2558 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2560 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2561 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2564 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2565 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2567 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2568 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2570 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2571 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2574 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2575 p_hwfn->p_dev->mf_mode);
2577 /* Read Multi-function information from shmem */
2578 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2579 OFFSETOF(struct nvm_cfg1, glob) +
2580 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2582 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2583 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2584 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2585 &p_hwfn->hw_info.device_capabilities);
2586 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2587 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2588 &p_hwfn->hw_info.device_capabilities);
2589 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2590 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2591 &p_hwfn->hw_info.device_capabilities);
2592 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2593 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2594 &p_hwfn->hw_info.device_capabilities);
2595 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2596 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2597 &p_hwfn->hw_info.device_capabilities);
2599 return ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2602 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2603 struct ecore_ptt *p_ptt)
2605 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2606 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2607 struct ecore_dev *p_dev = p_hwfn->p_dev;
2609 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2611 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2612 * in the other bits are selected.
2613 * Bits 1-15 are for functions 1-15, respectively, and their value is
2614 * '0' only for enabled functions (function 0 always exists and
2616 * In case of CMT in BB, only the "even" functions are enabled, and thus
2617 * the number of functions for both hwfns is learnt from the same bits.
2619 reg_function_hide = ecore_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2621 if (reg_function_hide & 0x1) {
2622 if (ECORE_IS_BB(p_dev)) {
2623 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
2635 /* Get the number of the enabled functions on the engine */
2636 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2643 /* Get the PF index within the enabled functions */
2644 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2645 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2653 p_hwfn->num_funcs_on_engine = num_funcs;
2654 p_hwfn->enabled_func_idx = enabled_func_idx;
2657 if (CHIP_REV_IS_FPGA(p_dev)) {
2658 DP_NOTICE(p_hwfn, false,
2659 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
2660 p_hwfn->num_funcs_on_engine = 4;
2664 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2665 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2666 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
2667 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2670 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
2671 struct ecore_ptt *p_ptt)
2676 /* Read the port mode */
2677 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
2679 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
2680 (p_hwfn->p_dev->num_hwfns > 1))
2681 /* In CMT on emulation, assume 1 port */
2685 port_mode = ecore_rd(p_hwfn, p_ptt,
2686 CNIG_REG_NW_PORT_MODE_BB_B0);
2688 if (port_mode < 3) {
2689 p_hwfn->p_dev->num_ports_in_engines = 1;
2690 } else if (port_mode <= 5) {
2691 p_hwfn->p_dev->num_ports_in_engines = 2;
2693 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
2694 p_hwfn->p_dev->num_ports_in_engines);
2696 /* Default num_ports_in_engines to something */
2697 p_hwfn->p_dev->num_ports_in_engines = 1;
2701 static void ecore_hw_info_port_num_ah(struct ecore_hwfn *p_hwfn,
2702 struct ecore_ptt *p_ptt)
2707 p_hwfn->p_dev->num_ports_in_engines = 0;
2710 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2711 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
2712 switch ((port & 0xf000) >> 12) {
2714 p_hwfn->p_dev->num_ports_in_engines = 1;
2717 p_hwfn->p_dev->num_ports_in_engines = 2;
2720 p_hwfn->p_dev->num_ports_in_engines = 4;
2723 DP_NOTICE(p_hwfn, false,
2724 "Unknown port mode in ECO_RESERVED %08x\n",
2729 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2730 port = ecore_rd(p_hwfn, p_ptt,
2731 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2733 p_hwfn->p_dev->num_ports_in_engines++;
2737 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
2738 struct ecore_ptt *p_ptt)
2740 if (ECORE_IS_BB(p_hwfn->p_dev))
2741 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
2743 ecore_hw_info_port_num_ah(p_hwfn, p_ptt);
2746 static enum _ecore_status_t
2747 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2748 enum ecore_pci_personality personality, bool drv_resc_alloc)
2750 enum _ecore_status_t rc;
2752 /* Since all information is common, only first hwfns should do this */
2753 if (IS_LEAD_HWFN(p_hwfn)) {
2754 rc = ecore_iov_hw_info(p_hwfn);
2759 /* TODO In get_hw_info, amoungst others:
2760 * Get MCP FW revision and determine according to it the supported
2761 * featrues (e.g. DCB)
2763 * ecore_get_pcie_width_speed, WOL capability.
2764 * Number of global CQ-s (for storage
2766 ecore_hw_info_port_num(p_hwfn, p_ptt);
2769 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2771 ecore_hw_get_nvm_info(p_hwfn, p_ptt);
2773 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
2778 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
2780 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
2781 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
2784 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
2786 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
2787 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
2791 if (ecore_mcp_is_init(p_hwfn)) {
2792 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
2793 p_hwfn->hw_info.ovlan =
2794 p_hwfn->mcp_info->func_info.ovlan;
2796 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
2799 if (personality != ECORE_PCI_DEFAULT)
2800 p_hwfn->hw_info.personality = personality;
2801 else if (ecore_mcp_is_init(p_hwfn))
2802 p_hwfn->hw_info.personality =
2803 p_hwfn->mcp_info->func_info.protocol;
2806 /* To overcome ILT lack for emulation, until at least until we'll have
2807 * a definite answer from system about it, allow only PF0 to be RoCE.
2809 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
2810 if (!p_hwfn->rel_pf_id)
2811 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2813 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2817 /* although in BB some constellations may support more than 4 tcs,
2818 * that can result in performance penalty in some cases. 4
2819 * represents a good tradeoff between performance and flexibility.
2821 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2823 /* start out with a single active tc. This can be increased either
2824 * by dcbx negotiation or by upper layer driver
2826 p_hwfn->hw_info.num_active_tc = 1;
2828 ecore_get_num_funcs(p_hwfn, p_ptt);
2830 /* In case of forcing the driver's default resource allocation, calling
2831 * ecore_hw_get_resc() should come after initializing the personality
2832 * and after getting the number of functions, since the calculation of
2833 * the resources/features depends on them.
2834 * This order is not harmful if not forcing.
2836 return ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
2839 #define ECORE_DEV_ID_MASK 0xff00
2840 #define ECORE_DEV_ID_MASK_BB 0x1600
2841 #define ECORE_DEV_ID_MASK_AH 0x8000
2843 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
2845 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2848 /* Read Vendor Id / Device Id */
2849 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
2851 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
2854 /* Determine type */
2855 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
2856 p_dev->type = ECORE_DEV_TYPE_AH;
2858 p_dev->type = ECORE_DEV_TYPE_BB;
2860 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2861 MISCS_REG_CHIP_NUM);
2862 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2863 MISCS_REG_CHIP_REV);
2865 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
2867 /* Learn number of HW-functions */
2868 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2869 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2871 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2872 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
2873 p_dev->num_hwfns = 2;
2875 p_dev->num_hwfns = 1;
2879 if (CHIP_REV_IS_EMUL(p_dev)) {
2880 /* For some reason we have problems with this register
2881 * in B0 emulation; Simply assume no CMT
2883 DP_NOTICE(p_dev->hwfns, false,
2884 "device on emul - assume no CMT\n");
2885 p_dev->num_hwfns = 1;
2889 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2890 MISCS_REG_CHIP_TEST_REG) >> 4;
2891 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
2892 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2893 MISCS_REG_CHIP_METAL);
2894 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
2895 DP_INFO(p_dev->hwfns,
2896 "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2897 ECORE_IS_BB(p_dev) ? "BB" : "AH",
2898 CHIP_REV_IS_A0(p_dev) ? 0 : 1,
2899 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
2902 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
2903 DP_NOTICE(p_dev->hwfns, false,
2904 "The chip type/rev (BB A0) is not supported!\n");
2905 return ECORE_ABORTED;
2908 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
2909 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2910 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
2912 if (CHIP_REV_IS_EMUL(p_dev)) {
2913 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
2914 MISCS_REG_ECO_RESERVED);
2915 if (tmp & (1 << 29)) {
2916 DP_NOTICE(p_hwfn, false,
2917 "Emulation: Running on a FULL build\n");
2918 p_dev->b_is_emul_full = true;
2920 DP_NOTICE(p_hwfn, false,
2921 "Emulation: Running on a REDUCED build\n");
2926 return ECORE_SUCCESS;
2929 #ifndef LINUX_REMOVE
2930 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
2937 for_each_hwfn(p_dev, j) {
2938 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2940 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2941 "Mark hw/fw uninitialized\n");
2943 p_hwfn->hw_init_done = false;
2944 p_hwfn->first_on_engine = false;
2946 ecore_ptt_invalidate(p_hwfn);
2951 static enum _ecore_status_t
2952 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
2953 void OSAL_IOMEM *p_doorbells,
2954 struct ecore_hw_prepare_params *p_params)
2956 struct ecore_dev *p_dev = p_hwfn->p_dev;
2957 enum _ecore_status_t rc = ECORE_SUCCESS;
2959 /* Split PCI bars evenly between hwfns */
2960 p_hwfn->regview = p_regview;
2961 p_hwfn->doorbells = p_doorbells;
2964 return ecore_vf_hw_prepare(p_hwfn);
2966 /* Validate that chip access is feasible */
2967 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2969 "Reading the ME register returns all Fs; Preventing further chip access\n");
2973 get_function_id(p_hwfn);
2975 /* Allocate PTT pool */
2976 rc = ecore_ptt_pool_alloc(p_hwfn);
2978 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
2982 /* Allocate the main PTT */
2983 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2985 /* First hwfn learns basic information, e.g., number of hwfns */
2986 if (!p_hwfn->my_id) {
2987 rc = ecore_get_dev_info(p_dev);
2988 if (rc != ECORE_SUCCESS)
2992 ecore_hw_hwfn_prepare(p_hwfn);
2994 /* Initialize MCP structure */
2995 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2997 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3001 /* Read the device configuration information from the HW and SHMEM */
3002 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3003 p_params->personality, p_params->drv_resc_alloc);
3005 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3009 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3010 * called, since among others it sets the ports number in an engine.
3012 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3013 !p_dev->recov_in_prog) {
3014 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3015 if (rc != ECORE_SUCCESS)
3016 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3019 /* Allocate the init RT array and initialize the init-ops engine */
3020 rc = ecore_init_alloc(p_hwfn);
3022 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3026 if (CHIP_REV_IS_FPGA(p_dev)) {
3027 DP_NOTICE(p_hwfn, false,
3028 "FPGA: workaround; Prevent DMAE parities\n");
3029 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
3031 DP_NOTICE(p_hwfn, false,
3032 "FPGA: workaround: Set VF bar0 size\n");
3033 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3034 PGLUE_B_REG_VF_BAR0_SIZE, 4);
3040 if (IS_LEAD_HWFN(p_hwfn))
3041 ecore_iov_free_hw_info(p_dev);
3042 ecore_mcp_free(p_hwfn);
3044 ecore_hw_hwfn_free(p_hwfn);
3049 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3050 struct ecore_hw_prepare_params *p_params)
3052 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3053 enum _ecore_status_t rc;
3055 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3057 /* Store the precompiled init data ptrs */
3059 ecore_init_iro_array(p_dev);
3061 /* Initialize the first hwfn - will learn number of hwfns */
3062 rc = ecore_hw_prepare_single(p_hwfn,
3064 p_dev->doorbells, p_params);
3065 if (rc != ECORE_SUCCESS)
3068 p_params->personality = p_hwfn->hw_info.personality;
3070 /* initilalize 2nd hwfn if necessary */
3071 if (p_dev->num_hwfns > 1) {
3072 void OSAL_IOMEM *p_regview, *p_doorbell;
3073 u8 OSAL_IOMEM *addr;
3075 /* adjust bar offset for second engine */
3076 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3077 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3078 p_regview = (void OSAL_IOMEM *)addr;
3080 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3081 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3082 p_doorbell = (void OSAL_IOMEM *)addr;
3084 /* prepare second hw function */
3085 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3086 p_doorbell, p_params);
3088 /* in case of error, need to free the previously
3089 * initiliazed hwfn 0.
3091 if (rc != ECORE_SUCCESS) {
3093 ecore_init_free(p_hwfn);
3094 ecore_mcp_free(p_hwfn);
3095 ecore_hw_hwfn_free(p_hwfn);
3097 DP_NOTICE(p_dev, true,
3098 "What do we need to free when VF hwfn1 init fails\n");
3104 return ECORE_SUCCESS;
3107 void ecore_hw_remove(struct ecore_dev *p_dev)
3111 for_each_hwfn(p_dev, i) {
3112 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3115 ecore_vf_pf_release(p_hwfn);
3119 ecore_init_free(p_hwfn);
3120 ecore_hw_hwfn_free(p_hwfn);
3121 ecore_mcp_free(p_hwfn);
3123 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3126 ecore_iov_free_hw_info(p_dev);
3129 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3130 struct ecore_chain *p_chain)
3132 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3133 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3134 struct ecore_chain_next *p_next;
3140 size = p_chain->elem_size * p_chain->usable_per_page;
3142 for (i = 0; i < p_chain->page_cnt; i++) {
3146 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3147 p_virt_next = p_next->next_virt;
3148 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3150 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3151 ECORE_CHAIN_PAGE_SIZE);
3153 p_virt = p_virt_next;
3154 p_phys = p_phys_next;
3158 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3159 struct ecore_chain *p_chain)
3161 if (!p_chain->p_virt_addr)
3164 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3165 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3168 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3169 struct ecore_chain *p_chain)
3171 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3172 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3173 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3175 if (!pp_virt_addr_tbl)
3178 if (!p_chain->pbl.p_virt_table)
3181 for (i = 0; i < page_cnt; i++) {
3182 if (!pp_virt_addr_tbl[i])
3185 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3186 *(dma_addr_t *)p_pbl_virt,
3187 ECORE_CHAIN_PAGE_SIZE);
3189 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3192 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3193 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3194 p_chain->pbl.p_phys_table, pbl_size);
3196 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3199 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3201 switch (p_chain->mode) {
3202 case ECORE_CHAIN_MODE_NEXT_PTR:
3203 ecore_chain_free_next_ptr(p_dev, p_chain);
3205 case ECORE_CHAIN_MODE_SINGLE:
3206 ecore_chain_free_single(p_dev, p_chain);
3208 case ECORE_CHAIN_MODE_PBL:
3209 ecore_chain_free_pbl(p_dev, p_chain);
3214 static enum _ecore_status_t
3215 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3216 enum ecore_chain_cnt_type cnt_type,
3217 osal_size_t elem_size, u32 page_cnt)
3219 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3221 /* The actual chain size can be larger than the maximal possible value
3222 * after rounding up the requested elements number to pages, and after
3223 * taking into acount the unusuable elements (next-ptr elements).
3224 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3225 * size/capacity fields are of a u32 type.
3227 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3228 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3229 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3230 chain_size > ECORE_U32_MAX)) {
3231 DP_NOTICE(p_dev, true,
3232 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3233 (unsigned long)chain_size);
3237 return ECORE_SUCCESS;
3240 static enum _ecore_status_t
3241 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3243 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3244 dma_addr_t p_phys = 0;
3247 for (i = 0; i < p_chain->page_cnt; i++) {
3248 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3249 ECORE_CHAIN_PAGE_SIZE);
3251 DP_NOTICE(p_dev, true,
3252 "Failed to allocate chain memory\n");
3257 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3258 ecore_chain_reset(p_chain);
3260 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3264 p_virt_prev = p_virt;
3266 /* Last page's next element should point to the beginning of the
3269 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3270 p_chain->p_virt_addr,
3271 p_chain->p_phys_addr);
3273 return ECORE_SUCCESS;
3276 static enum _ecore_status_t
3277 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3279 void *p_virt = OSAL_NULL;
3280 dma_addr_t p_phys = 0;
3282 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3284 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3288 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3289 ecore_chain_reset(p_chain);
3291 return ECORE_SUCCESS;
3294 static enum _ecore_status_t ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3295 struct ecore_chain *p_chain)
3297 void *p_virt = OSAL_NULL;
3298 u8 *p_pbl_virt = OSAL_NULL;
3299 void **pp_virt_addr_tbl = OSAL_NULL;
3300 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3301 u32 page_cnt = p_chain->page_cnt, size, i;
3303 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3304 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3305 if (!pp_virt_addr_tbl) {
3306 DP_NOTICE(p_dev, true,
3307 "Failed to allocate memory for the chain virtual addresses table\n");
3310 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3312 /* The allocation of the PBL table is done with its full size, since it
3313 * is expected to be successive.
3314 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3315 * failure, since pp_virt_addr_tbl was previously allocated, and it
3316 * should be saved to allow its freeing during the error flow.
3318 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3319 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3320 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3323 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3327 for (i = 0; i < page_cnt; i++) {
3328 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3329 ECORE_CHAIN_PAGE_SIZE);
3331 DP_NOTICE(p_dev, true,
3332 "Failed to allocate chain memory\n");
3337 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3338 ecore_chain_reset(p_chain);
3341 /* Fill the PBL table with the physical address of the page */
3342 *(dma_addr_t *)p_pbl_virt = p_phys;
3343 /* Keep the virtual address of the page */
3344 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3346 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3349 return ECORE_SUCCESS;
3352 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3353 enum ecore_chain_use_mode intended_use,
3354 enum ecore_chain_mode mode,
3355 enum ecore_chain_cnt_type cnt_type,
3356 u32 num_elems, osal_size_t elem_size,
3357 struct ecore_chain *p_chain)
3360 enum _ecore_status_t rc = ECORE_SUCCESS;
3362 if (mode == ECORE_CHAIN_MODE_SINGLE)
3365 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3367 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3370 DP_NOTICE(p_dev, true,
3371 "Cannot allocate a chain with the given arguments:\n"
3372 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3373 intended_use, mode, cnt_type, num_elems, elem_size);
3377 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3378 mode, cnt_type, p_dev->dp_ctx);
3381 case ECORE_CHAIN_MODE_NEXT_PTR:
3382 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3384 case ECORE_CHAIN_MODE_SINGLE:
3385 rc = ecore_chain_alloc_single(p_dev, p_chain);
3387 case ECORE_CHAIN_MODE_PBL:
3388 rc = ecore_chain_alloc_pbl(p_dev, p_chain);
3394 return ECORE_SUCCESS;
3397 ecore_chain_free(p_dev, p_chain);
3401 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3402 u16 src_id, u16 *dst_id)
3404 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3407 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3408 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3409 DP_NOTICE(p_hwfn, true,
3410 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3416 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3418 return ECORE_SUCCESS;
3421 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3422 u8 src_id, u8 *dst_id)
3424 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3427 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3428 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3429 DP_NOTICE(p_hwfn, true,
3430 "vport id [%d] is not valid, available indices [%d - %d]\n",
3436 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3438 return ECORE_SUCCESS;
3441 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3442 u8 src_id, u8 *dst_id)
3444 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3447 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3448 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3449 DP_NOTICE(p_hwfn, true,
3450 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3456 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3458 return ECORE_SUCCESS;
3461 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3462 struct ecore_ptt *p_ptt,
3468 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3469 return ECORE_SUCCESS;
3471 high = p_filter[1] | (p_filter[0] << 8);
3472 low = p_filter[5] | (p_filter[4] << 8) |
3473 (p_filter[3] << 16) | (p_filter[2] << 24);
3475 /* Find a free entry and utilize it */
3476 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3477 en = ecore_rd(p_hwfn, p_ptt,
3478 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3481 ecore_wr(p_hwfn, p_ptt,
3482 NIG_REG_LLH_FUNC_FILTER_VALUE +
3483 2 * i * sizeof(u32), low);
3484 ecore_wr(p_hwfn, p_ptt,
3485 NIG_REG_LLH_FUNC_FILTER_VALUE +
3486 (2 * i + 1) * sizeof(u32), high);
3487 ecore_wr(p_hwfn, p_ptt,
3488 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3489 ecore_wr(p_hwfn, p_ptt,
3490 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3491 i * sizeof(u32), 0);
3492 ecore_wr(p_hwfn, p_ptt,
3493 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3496 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3497 DP_NOTICE(p_hwfn, false,
3498 "Failed to find an empty LLH filter to utilize\n");
3502 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3503 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3504 p_filter[0], p_filter[1], p_filter[2],
3505 p_filter[3], p_filter[4], p_filter[5], i);
3507 return ECORE_SUCCESS;
3510 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3511 struct ecore_ptt *p_ptt, u8 *p_filter)
3516 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3519 high = p_filter[1] | (p_filter[0] << 8);
3520 low = p_filter[5] | (p_filter[4] << 8) |
3521 (p_filter[3] << 16) | (p_filter[2] << 24);
3523 /* Find the entry and clean it */
3524 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3525 if (ecore_rd(p_hwfn, p_ptt,
3526 NIG_REG_LLH_FUNC_FILTER_VALUE +
3527 2 * i * sizeof(u32)) != low)
3529 if (ecore_rd(p_hwfn, p_ptt,
3530 NIG_REG_LLH_FUNC_FILTER_VALUE +
3531 (2 * i + 1) * sizeof(u32)) != high)
3534 ecore_wr(p_hwfn, p_ptt,
3535 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3536 ecore_wr(p_hwfn, p_ptt,
3537 NIG_REG_LLH_FUNC_FILTER_VALUE +
3538 2 * i * sizeof(u32), 0);
3539 ecore_wr(p_hwfn, p_ptt,
3540 NIG_REG_LLH_FUNC_FILTER_VALUE +
3541 (2 * i + 1) * sizeof(u32), 0);
3544 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3545 DP_NOTICE(p_hwfn, false,
3546 "Tried to remove a non-configured filter\n");
3549 enum _ecore_status_t
3550 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
3551 struct ecore_ptt *p_ptt,
3552 u16 source_port_or_eth_type,
3554 enum ecore_llh_port_filter_type_t type)
3559 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3560 return ECORE_SUCCESS;
3565 case ECORE_LLH_FILTER_ETHERTYPE:
3566 high = source_port_or_eth_type;
3568 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3569 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3570 low = source_port_or_eth_type << 16;
3572 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3573 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3576 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3577 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3578 low = (source_port_or_eth_type << 16) | dest_port;
3581 DP_NOTICE(p_hwfn, true,
3582 "Non valid LLH protocol filter type %d\n", type);
3585 /* Find a free entry and utilize it */
3586 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3587 en = ecore_rd(p_hwfn, p_ptt,
3588 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3591 ecore_wr(p_hwfn, p_ptt,
3592 NIG_REG_LLH_FUNC_FILTER_VALUE +
3593 2 * i * sizeof(u32), low);
3594 ecore_wr(p_hwfn, p_ptt,
3595 NIG_REG_LLH_FUNC_FILTER_VALUE +
3596 (2 * i + 1) * sizeof(u32), high);
3597 ecore_wr(p_hwfn, p_ptt,
3598 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3599 ecore_wr(p_hwfn, p_ptt,
3600 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3601 i * sizeof(u32), 1 << type);
3602 ecore_wr(p_hwfn, p_ptt,
3603 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3606 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3607 DP_NOTICE(p_hwfn, false,
3608 "Failed to find an empty LLH filter to utilize\n");
3609 return ECORE_NORESOURCES;
3612 case ECORE_LLH_FILTER_ETHERTYPE:
3613 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3614 "ETH type %x is added at %d\n",
3615 source_port_or_eth_type, i);
3617 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3618 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3619 "TCP src port %x is added at %d\n",
3620 source_port_or_eth_type, i);
3622 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3623 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3624 "UDP src port %x is added at %d\n",
3625 source_port_or_eth_type, i);
3627 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3628 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3629 "TCP dst port %x is added at %d\n", dest_port, i);
3631 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3632 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3633 "UDP dst port %x is added at %d\n", dest_port, i);
3635 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3636 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3637 "TCP src/dst ports %x/%x are added at %d\n",
3638 source_port_or_eth_type, dest_port, i);
3640 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3641 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3642 "UDP src/dst ports %x/%x are added at %d\n",
3643 source_port_or_eth_type, dest_port, i);
3646 return ECORE_SUCCESS;
3650 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
3651 struct ecore_ptt *p_ptt,
3652 u16 source_port_or_eth_type,
3654 enum ecore_llh_port_filter_type_t type)
3659 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3665 case ECORE_LLH_FILTER_ETHERTYPE:
3666 high = source_port_or_eth_type;
3668 case ECORE_LLH_FILTER_TCP_SRC_PORT:
3669 case ECORE_LLH_FILTER_UDP_SRC_PORT:
3670 low = source_port_or_eth_type << 16;
3672 case ECORE_LLH_FILTER_TCP_DEST_PORT:
3673 case ECORE_LLH_FILTER_UDP_DEST_PORT:
3676 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3677 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3678 low = (source_port_or_eth_type << 16) | dest_port;
3681 DP_NOTICE(p_hwfn, true,
3682 "Non valid LLH protocol filter type %d\n", type);
3686 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3687 if (!ecore_rd(p_hwfn, p_ptt,
3688 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3690 if (!ecore_rd(p_hwfn, p_ptt,
3691 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3693 if (!(ecore_rd(p_hwfn, p_ptt,
3694 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3695 i * sizeof(u32)) & (1 << type)))
3697 if (ecore_rd(p_hwfn, p_ptt,
3698 NIG_REG_LLH_FUNC_FILTER_VALUE +
3699 2 * i * sizeof(u32)) != low)
3701 if (ecore_rd(p_hwfn, p_ptt,
3702 NIG_REG_LLH_FUNC_FILTER_VALUE +
3703 (2 * i + 1) * sizeof(u32)) != high)
3706 ecore_wr(p_hwfn, p_ptt,
3707 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3708 ecore_wr(p_hwfn, p_ptt,
3709 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3710 ecore_wr(p_hwfn, p_ptt,
3711 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3712 i * sizeof(u32), 0);
3713 ecore_wr(p_hwfn, p_ptt,
3714 NIG_REG_LLH_FUNC_FILTER_VALUE +
3715 2 * i * sizeof(u32), 0);
3716 ecore_wr(p_hwfn, p_ptt,
3717 NIG_REG_LLH_FUNC_FILTER_VALUE +
3718 (2 * i + 1) * sizeof(u32), 0);
3722 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3723 DP_NOTICE(p_hwfn, false,
3724 "Tried to remove a non-configured filter\n");
3727 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
3728 struct ecore_ptt *p_ptt)
3732 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3735 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3736 ecore_wr(p_hwfn, p_ptt,
3737 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3738 ecore_wr(p_hwfn, p_ptt,
3739 NIG_REG_LLH_FUNC_FILTER_VALUE +
3740 2 * i * sizeof(u32), 0);
3741 ecore_wr(p_hwfn, p_ptt,
3742 NIG_REG_LLH_FUNC_FILTER_VALUE +
3743 (2 * i + 1) * sizeof(u32), 0);
3747 enum _ecore_status_t
3748 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
3749 struct ecore_ptt *p_ptt)
3751 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
3752 ecore_wr(p_hwfn, p_ptt,
3753 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
3754 1 << p_hwfn->abs_pf_id / 2);
3755 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
3756 return ECORE_SUCCESS;
3759 DP_NOTICE(p_hwfn, false,
3760 "This function can't be set as default\n");
3764 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
3765 struct ecore_ptt *p_ptt,
3766 u32 hw_addr, void *p_eth_qzone,
3767 osal_size_t eth_qzone_size,
3770 struct coalescing_timeset *p_coal_timeset;
3772 if (IS_VF(p_hwfn->p_dev)) {
3773 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
3777 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
3778 DP_NOTICE(p_hwfn, true,
3779 "Coalescing configuration not enabled\n");
3783 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
3784 p_coal_timeset = p_eth_qzone;
3785 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3786 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3787 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3789 return ECORE_SUCCESS;
3792 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
3793 struct ecore_ptt *p_ptt,
3794 u16 coalesce, u8 qid, u16 sb_id)
3796 struct ustorm_eth_queue_zone eth_qzone;
3799 enum _ecore_status_t rc;
3800 u8 timeset, timer_res;
3802 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3803 if (coalesce <= 0x7F) {
3805 } else if (coalesce <= 0xFF) {
3807 } else if (coalesce <= 0x1FF) {
3810 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3813 timeset = (u8)(coalesce >> timer_res);
3815 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3816 if (rc != ECORE_SUCCESS)
3819 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3820 if (rc != ECORE_SUCCESS)
3823 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3825 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3826 sizeof(struct ustorm_eth_queue_zone), timeset);
3827 if (rc != ECORE_SUCCESS)
3830 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
3835 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
3836 struct ecore_ptt *p_ptt,
3837 u16 coalesce, u8 qid, u16 sb_id)
3839 struct xstorm_eth_queue_zone eth_qzone;
3842 enum _ecore_status_t rc;
3843 u8 timeset, timer_res;
3845 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3846 if (coalesce <= 0x7F) {
3848 } else if (coalesce <= 0xFF) {
3850 } else if (coalesce <= 0x1FF) {
3853 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3857 timeset = (u8)(coalesce >> timer_res);
3859 rc = ecore_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3860 if (rc != ECORE_SUCCESS)
3863 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3864 if (rc != ECORE_SUCCESS)
3867 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3869 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3870 sizeof(struct xstorm_eth_queue_zone), timeset);
3871 if (rc != ECORE_SUCCESS)
3874 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
3879 /* Calculate final WFQ values for all vports and configure it.
3880 * After this configuration each vport must have
3881 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
3883 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3884 struct ecore_ptt *p_ptt,
3887 struct init_qm_vport_params *vport_params;
3890 vport_params = p_hwfn->qm_info.qm_vport_params;
3892 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3893 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3895 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
3897 ecore_init_vport_wfq(p_hwfn, p_ptt,
3898 vport_params[i].first_tx_pq_id,
3899 vport_params[i].vport_wfq);
3904 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
3908 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3909 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3912 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
3913 struct ecore_ptt *p_ptt,
3916 struct init_qm_vport_params *vport_params;
3919 vport_params = p_hwfn->qm_info.qm_vport_params;
3921 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3922 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
3923 ecore_init_vport_wfq(p_hwfn, p_ptt,
3924 vport_params[i].first_tx_pq_id,
3925 vport_params[i].vport_wfq);
3929 /* This function performs several validations for WFQ
3930 * configuration and required min rate for a given vport
3931 * 1. req_rate must be greater than one percent of min_pf_rate.
3932 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3933 * rates to get less than one percent of min_pf_rate.
3934 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3936 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
3937 u16 vport_id, u32 req_rate,
3940 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3941 int non_requested_count = 0, req_count = 0, i, num_vports;
3943 num_vports = p_hwfn->qm_info.num_vports;
3945 /* Accounting for the vports which are configured for WFQ explicitly */
3947 for (i = 0; i < num_vports; i++) {
3950 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
3952 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3953 total_req_min_rate += tmp_speed;
3957 /* Include current vport data as well */
3959 total_req_min_rate += req_rate;
3960 non_requested_count = num_vports - req_count;
3962 /* validate possible error cases */
3963 if (req_rate > min_pf_rate) {
3964 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3965 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3966 vport_id, req_rate, min_pf_rate);
3970 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
3971 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3972 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3973 vport_id, req_rate, min_pf_rate);
3977 /* TBD - for number of vports greater than 100 */
3978 if (num_vports > ECORE_WFQ_UNIT) {
3979 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3980 "Number of vports is greater than %d\n",
3985 if (total_req_min_rate > min_pf_rate) {
3986 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3987 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3988 total_req_min_rate, min_pf_rate);
3992 /* Data left for non requested vports */
3993 total_left_rate = min_pf_rate - total_req_min_rate;
3994 left_rate_per_vp = total_left_rate / non_requested_count;
3996 /* validate if non requested get < 1% of min bw */
3997 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
3998 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3999 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4000 left_rate_per_vp, min_pf_rate);
4004 /* now req_rate for given vport passes all scenarios.
4005 * assign final wfq rates to all vports.
4007 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4008 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4010 for (i = 0; i < num_vports; i++) {
4011 if (p_hwfn->qm_info.wfq_data[i].configured)
4014 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4017 return ECORE_SUCCESS;
4020 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4021 struct ecore_ptt *p_ptt,
4022 u16 vp_id, u32 rate)
4024 struct ecore_mcp_link_state *p_link;
4025 int rc = ECORE_SUCCESS;
4027 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4029 if (!p_link->min_pf_rate) {
4030 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4031 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4035 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4037 if (rc == ECORE_SUCCESS)
4038 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4039 p_link->min_pf_rate);
4041 DP_NOTICE(p_hwfn, false,
4042 "Validation failed while configuring min rate\n");
4047 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4048 struct ecore_ptt *p_ptt,
4051 bool use_wfq = false;
4052 int rc = ECORE_SUCCESS;
4055 /* Validate all pre configured vports for wfq */
4056 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4059 if (!p_hwfn->qm_info.wfq_data[i].configured)
4062 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4065 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4066 if (rc != ECORE_SUCCESS) {
4067 DP_NOTICE(p_hwfn, false,
4068 "WFQ validation failed while configuring min rate\n");
4073 if (rc == ECORE_SUCCESS && use_wfq)
4074 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4076 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4081 /* Main API for ecore clients to configure vport min rate.
4082 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4083 * rate - Speed in Mbps needs to be assigned to a given vport.
4085 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4087 int i, rc = ECORE_INVAL;
4089 /* TBD - for multiple hardware functions - that is 100 gig */
4090 if (p_dev->num_hwfns > 1) {
4091 DP_NOTICE(p_dev, false,
4092 "WFQ configuration is not supported for this device\n");
4096 for_each_hwfn(p_dev, i) {
4097 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4098 struct ecore_ptt *p_ptt;
4100 p_ptt = ecore_ptt_acquire(p_hwfn);
4102 return ECORE_TIMEOUT;
4104 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4106 if (rc != ECORE_SUCCESS) {
4107 ecore_ptt_release(p_hwfn, p_ptt);
4111 ecore_ptt_release(p_hwfn, p_ptt);
4117 /* API to configure WFQ from mcp link change */
4118 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4123 /* TBD - for multiple hardware functions - that is 100 gig */
4124 if (p_dev->num_hwfns > 1) {
4125 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4126 "WFQ configuration is not supported for this device\n");
4130 for_each_hwfn(p_dev, i) {
4131 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4133 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4139 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4140 struct ecore_ptt *p_ptt,
4141 struct ecore_mcp_link_state *p_link,
4144 int rc = ECORE_SUCCESS;
4146 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4148 if (!p_link->line_speed && (max_bw != 100))
4151 p_link->speed = (p_link->line_speed * max_bw) / 100;
4152 p_hwfn->qm_info.pf_rl = p_link->speed;
4154 /* Since the limiter also affects Tx-switched traffic, we don't want it
4155 * to limit such traffic in case there's no actual limit.
4156 * In that case, set limit to imaginary high boundary.
4159 p_hwfn->qm_info.pf_rl = 100000;
4161 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4162 p_hwfn->qm_info.pf_rl);
4164 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4165 "Configured MAX bandwidth to be %08x Mb/sec\n",
4171 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4172 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4174 int i, rc = ECORE_INVAL;
4176 if (max_bw < 1 || max_bw > 100) {
4177 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4181 for_each_hwfn(p_dev, i) {
4182 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4183 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4184 struct ecore_mcp_link_state *p_link;
4185 struct ecore_ptt *p_ptt;
4187 p_link = &p_lead->mcp_info->link_output;
4189 p_ptt = ecore_ptt_acquire(p_hwfn);
4191 return ECORE_TIMEOUT;
4193 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4196 ecore_ptt_release(p_hwfn, p_ptt);
4198 if (rc != ECORE_SUCCESS)
4205 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4206 struct ecore_ptt *p_ptt,
4207 struct ecore_mcp_link_state *p_link,
4210 int rc = ECORE_SUCCESS;
4212 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4213 p_hwfn->qm_info.pf_wfq = min_bw;
4215 if (!p_link->line_speed)
4218 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4220 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4222 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4223 "Configured MIN bandwidth to be %d Mb/sec\n",
4224 p_link->min_pf_rate);
4229 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4230 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4232 int i, rc = ECORE_INVAL;
4234 if (min_bw < 1 || min_bw > 100) {
4235 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4239 for_each_hwfn(p_dev, i) {
4240 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4241 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4242 struct ecore_mcp_link_state *p_link;
4243 struct ecore_ptt *p_ptt;
4245 p_link = &p_lead->mcp_info->link_output;
4247 p_ptt = ecore_ptt_acquire(p_hwfn);
4249 return ECORE_TIMEOUT;
4251 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4253 if (rc != ECORE_SUCCESS) {
4254 ecore_ptt_release(p_hwfn, p_ptt);
4258 if (p_link->min_pf_rate) {
4259 u32 min_rate = p_link->min_pf_rate;
4261 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4266 ecore_ptt_release(p_hwfn, p_ptt);
4272 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4274 struct ecore_mcp_link_state *p_link;
4276 p_link = &p_hwfn->mcp_info->link_output;
4278 if (p_link->min_pf_rate)
4279 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4280 p_link->min_pf_rate);
4282 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4283 sizeof(*p_hwfn->qm_info.wfq_data) *
4284 p_hwfn->qm_info.num_vports);
4287 int ecore_device_num_engines(struct ecore_dev *p_dev)
4289 return ECORE_IS_BB(p_dev) ? 2 : 1;
4292 int ecore_device_num_ports(struct ecore_dev *p_dev)
4294 /* in CMT always only one port */
4295 if (p_dev->num_hwfns > 1)
4298 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4301 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4306 ((u8 *)fw_msb)[0] = mac[1];
4307 ((u8 *)fw_msb)[1] = mac[0];
4308 ((u8 *)fw_mid)[0] = mac[3];
4309 ((u8 *)fw_mid)[1] = mac[2];
4310 ((u8 *)fw_lsb)[0] = mac[5];
4311 ((u8 *)fw_lsb)[1] = mac[4];