2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_gtt_reg_addr.h"
13 #include "ecore_chain.h"
14 #include "ecore_status.h"
16 #include "ecore_rt_defs.h"
17 #include "ecore_init_ops.h"
18 #include "ecore_int.h"
19 #include "ecore_cxt.h"
20 #include "ecore_spq.h"
21 #include "ecore_init_fw_funcs.h"
22 #include "ecore_sp_commands.h"
23 #include "ecore_dev_api.h"
24 #include "ecore_sriov.h"
26 #include "ecore_mcp.h"
27 #include "ecore_hw_defs.h"
28 #include "mcp_public.h"
29 #include "ecore_iro.h"
31 #include "ecore_dev_api.h"
32 #include "ecore_dcbx.h"
34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
35 * registers involved are not split and thus configuration is a race where
36 * some of the PFs configuration might be lost.
37 * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
38 * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
39 * there's more than a single compiled ecore component in system].
41 static osal_spinlock_t qm_lock;
42 static bool qm_lock_init;
45 #define ECORE_MIN_DPIS (4) /* The minimal num of DPIs required to
46 * load the driver. The number was
51 #define ECORE_MIN_PWM_REGION ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
54 BAR_ID_0, /* used for GRC */
55 BAR_ID_1 /* Used for doorbells */
58 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
60 u32 bar_reg = (bar_id == BAR_ID_0 ?
61 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
64 if (IS_VF(p_hwfn->p_dev)) {
65 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
66 * read from actual register, but we're currently not using
67 * it for actual doorbelling.
72 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
74 return 1 << (val + 15);
76 /* The above registers were updated in the past only in CMT mode. Since
77 * they were found to be useful MFW started updating them from 8.7.7.0.
78 * In older MFW versions they are set to 0 which means disabled.
80 if (p_hwfn->p_dev->num_hwfns > 1) {
81 DP_NOTICE(p_hwfn, false,
82 "BAR size not configured. Assuming BAR size of 256kB"
83 " for GRC and 512kB for DB\n");
84 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
86 DP_NOTICE(p_hwfn, false,
87 "BAR size not configured. Assuming BAR size of 512kB"
88 " for GRC and 512kB for DB\n");
95 void ecore_init_dp(struct ecore_dev *p_dev,
96 u32 dp_module, u8 dp_level, void *dp_ctx)
100 p_dev->dp_level = dp_level;
101 p_dev->dp_module = dp_module;
102 p_dev->dp_ctx = dp_ctx;
103 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
104 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
106 p_hwfn->dp_level = dp_level;
107 p_hwfn->dp_module = dp_module;
108 p_hwfn->dp_ctx = dp_ctx;
112 void ecore_init_struct(struct ecore_dev *p_dev)
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
119 p_hwfn->p_dev = p_dev;
121 p_hwfn->b_active = false;
123 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
124 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
127 /* hwfn 0 is always active */
128 p_dev->hwfns[0].b_active = true;
130 /* set the default cache alignment to 128 (may be overridden later) */
131 p_dev->cache_shift = 7;
134 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
136 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
138 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
139 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
140 OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
141 OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
144 void ecore_resc_free(struct ecore_dev *p_dev)
151 OSAL_FREE(p_dev, p_dev->fw_data);
153 OSAL_FREE(p_dev, p_dev->reset_stats);
155 for_each_hwfn(p_dev, i) {
156 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
158 OSAL_FREE(p_dev, p_hwfn->p_tx_cids);
159 OSAL_FREE(p_dev, p_hwfn->p_rx_cids);
162 for_each_hwfn(p_dev, i) {
163 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
165 ecore_cxt_mngr_free(p_hwfn);
166 ecore_qm_info_free(p_hwfn);
167 ecore_spq_free(p_hwfn);
168 ecore_eq_free(p_hwfn, p_hwfn->p_eq);
169 ecore_consq_free(p_hwfn, p_hwfn->p_consq);
170 ecore_int_free(p_hwfn);
171 #ifdef CONFIG_ECORE_LL2
172 ecore_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
174 ecore_iov_free(p_hwfn);
175 ecore_dmae_info_free(p_hwfn);
176 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
177 /* @@@TBD Flush work-queue ? */
181 /******************** QM initialization *******************/
183 /* bitmaps for indicating active traffic classes.
184 * Special case for Arrowhead 4 port
186 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
187 #define ACTIVE_TCS_BMAP 0x9f
188 /* 0..3 actually used, OOO and high priority stuff all use 3 */
189 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
191 /* determines the physical queue flags for a given PF. */
192 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
200 if (IS_ECORE_SRIOV(p_hwfn->p_dev))
201 flags |= PQ_FLAGS_VFS;
204 switch (p_hwfn->hw_info.personality) {
206 flags |= PQ_FLAGS_MCOS;
209 flags |= PQ_FLAGS_OFLD;
211 case ECORE_PCI_ISCSI:
212 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
214 case ECORE_PCI_ETH_ROCE:
215 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
217 case ECORE_PCI_ETH_IWARP:
218 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
222 DP_ERR(p_hwfn, "unknown personality %d\n",
223 p_hwfn->hw_info.personality);
229 /* Getters for resource amounts necessary for qm initialization */
230 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
232 return p_hwfn->hw_info.num_hw_tc;
235 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
237 return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
238 p_hwfn->p_dev->p_iov_info->total_vfs : 0;
241 #define NUM_DEFAULT_RLS 1
243 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
245 u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
248 /* num RLs can't exceed resource amount of rls or vports or the
251 num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
252 (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
254 /* make sure after we reserve the default and VF rls we'll have
257 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
258 DP_NOTICE(p_hwfn, false,
259 "no rate limiters left for PF rate limiting"
260 " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
264 /* subtract rls necessary for VFs and one default one for the PF */
265 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
270 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
272 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
274 /* all pqs share the same vport (hence the 1 below), except for vfs
277 return (!!(PQ_FLAGS_RLS & pq_flags)) *
278 ecore_init_qm_get_num_pf_rls(p_hwfn) +
279 (!!(PQ_FLAGS_VFS & pq_flags)) *
280 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
283 /* calc amount of PQs according to the requested flags */
284 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
286 u32 pq_flags = ecore_get_pq_flags(p_hwfn);
288 return (!!(PQ_FLAGS_RLS & pq_flags)) *
289 ecore_init_qm_get_num_pf_rls(p_hwfn) +
290 (!!(PQ_FLAGS_MCOS & pq_flags)) *
291 ecore_init_qm_get_num_tcs(p_hwfn) +
292 (!!(PQ_FLAGS_LB & pq_flags)) +
293 (!!(PQ_FLAGS_OOO & pq_flags)) +
294 (!!(PQ_FLAGS_ACK & pq_flags)) +
295 (!!(PQ_FLAGS_OFLD & pq_flags)) +
296 (!!(PQ_FLAGS_VFS & pq_flags)) *
297 ecore_init_qm_get_num_vfs(p_hwfn);
300 /* initialize the top level QM params */
301 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
303 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
305 /* pq and vport bases for this PF */
306 qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
307 qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
309 /* rate limiting and weighted fair queueing are always enabled */
310 qm_info->vport_rl_en = 1;
311 qm_info->vport_wfq_en = 1;
313 /* in AH 4 port we have fewer TCs per port */
314 qm_info->max_phys_tcs_per_port =
315 p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2 ?
316 NUM_PHYS_TCS_4PORT_K2 : NUM_OF_PHYS_TCS;
319 /* initialize qm vport params */
320 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
322 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
325 /* all vports participate in weighted fair queueing */
326 for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
327 qm_info->qm_vport_params[i].vport_wfq = 1;
330 /* initialize qm port params */
331 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
333 /* Initialize qm port parameters */
334 u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
336 /* indicate how ooo and high pri traffic is dealt with */
337 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
338 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
340 for (i = 0; i < num_ports; i++) {
341 struct init_qm_port_params *p_qm_port =
342 &p_hwfn->qm_info.qm_port_params[i];
344 p_qm_port->active = 1;
345 p_qm_port->active_phys_tcs = active_phys_tcs;
346 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
347 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
351 /* Reset the params which must be reset for qm init. QM init may be called as
352 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
353 * params may be affected by the init but would simply recalculate to the same
354 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
355 * affected as these amounts stay the same.
357 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
359 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
361 qm_info->num_pqs = 0;
362 qm_info->num_vports = 0;
363 qm_info->num_pf_rls = 0;
364 qm_info->num_vf_pqs = 0;
365 qm_info->first_vf_pq = 0;
366 qm_info->first_mcos_pq = 0;
367 qm_info->first_rl_pq = 0;
370 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
372 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
374 qm_info->num_vports++;
376 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
378 "vport overflow! qm_info->num_vports %d,"
379 " qm_init_get_num_vports() %d\n",
381 ecore_init_qm_get_num_vports(p_hwfn));
384 /* initialize a single pq and manage qm_info resources accounting.
385 * The pq_init_flags param determines whether the PQ is rate limited
387 * and whether a new vport is allocated to the pq or not (i.e. vport will be
391 /* flags for pq init */
392 #define PQ_INIT_SHARE_VPORT (1 << 0)
393 #define PQ_INIT_PF_RL (1 << 1)
394 #define PQ_INIT_VF_RL (1 << 2)
396 /* defines for pq init */
397 #define PQ_INIT_DEFAULT_WRR_GROUP 1
398 #define PQ_INIT_DEFAULT_TC 0
399 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
401 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
402 struct ecore_qm_info *qm_info,
403 u8 tc, u32 pq_init_flags)
405 u16 pq_idx = qm_info->num_pqs, max_pq =
406 ecore_init_qm_get_num_pqs(p_hwfn);
410 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
413 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
415 qm_info->qm_pq_params[pq_idx].tc_id = tc;
416 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
417 qm_info->qm_pq_params[pq_idx].rl_valid =
418 (pq_init_flags & PQ_INIT_PF_RL ||
419 pq_init_flags & PQ_INIT_VF_RL);
421 /* qm params accounting */
423 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
424 qm_info->num_vports++;
426 if (pq_init_flags & PQ_INIT_PF_RL)
427 qm_info->num_pf_rls++;
429 if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
431 "vport overflow! qm_info->num_vports %d,"
432 " qm_init_get_num_vports() %d\n",
434 ecore_init_qm_get_num_vports(p_hwfn));
436 if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
437 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
438 " qm_init_get_num_pf_rls() %d\n",
440 ecore_init_qm_get_num_pf_rls(p_hwfn));
443 /* get pq index according to PQ_FLAGS */
444 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
447 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
449 /* Can't have multiple flags set here */
450 if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
451 sizeof(pq_flags)) > 1)
456 return &qm_info->first_rl_pq;
458 return &qm_info->first_mcos_pq;
460 return &qm_info->pure_lb_pq;
462 return &qm_info->ooo_pq;
464 return &qm_info->pure_ack_pq;
466 return &qm_info->offload_pq;
468 return &qm_info->first_vf_pq;
474 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
478 /* save pq index in qm info */
479 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
480 u32 pq_flags, u16 pq_val)
482 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
484 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
487 /* get tx pq index, with the PQ TX base already set (ready for context init) */
488 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
490 u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
492 return *base_pq_idx + CM_TX_PQ_BASE;
495 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
497 u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
500 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
502 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
505 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
507 u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
510 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
512 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
515 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
517 u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
520 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
522 return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
525 /* Functions for creating specific types of pqs */
526 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
528 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
530 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
533 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
534 ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
537 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
539 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
541 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
544 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
545 ecore_init_qm_pq(p_hwfn, qm_info, DCBX_ISCSI_OOO_TC,
546 PQ_INIT_SHARE_VPORT);
549 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
551 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
553 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
556 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
557 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
560 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
562 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
564 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
567 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
568 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
571 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
573 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
576 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
579 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
580 for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
581 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
584 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
586 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
587 u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
589 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
592 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
594 qm_info->num_vf_pqs = num_vfs;
595 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
596 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
600 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
602 u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
603 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
605 if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
608 ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
609 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
610 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
614 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
616 /* rate limited pqs, must come first (FW assumption) */
617 ecore_init_qm_rl_pqs(p_hwfn);
619 /* pqs for multi cos */
620 ecore_init_qm_mcos_pqs(p_hwfn);
622 /* pure loopback pq */
623 ecore_init_qm_lb_pq(p_hwfn);
625 /* out of order pq */
626 ecore_init_qm_ooo_pq(p_hwfn);
629 ecore_init_qm_pure_ack_pq(p_hwfn);
631 /* pq for offloaded protocol */
632 ecore_init_qm_offload_pq(p_hwfn);
634 /* done sharing vports */
635 ecore_init_qm_advance_vport(p_hwfn);
638 ecore_init_qm_vf_pqs(p_hwfn);
641 /* compare values of getters against resources amounts */
642 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
644 if (ecore_init_qm_get_num_vports(p_hwfn) >
645 RESC_NUM(p_hwfn, ECORE_VPORT)) {
646 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
650 if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
651 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
655 return ECORE_SUCCESS;
659 * Function for verbose printing of the qm initialization results
661 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
663 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
664 struct init_qm_vport_params *vport;
665 struct init_qm_port_params *port;
666 struct init_qm_pq_params *pq;
669 /* top level params */
670 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
671 "qm init top level params: start_pq %d, start_vport %d,"
672 " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
673 qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
674 qm_info->offload_pq, qm_info->pure_ack_pq);
675 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
676 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
677 " num_vports %d, max_phys_tcs_per_port %d\n",
678 qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
679 qm_info->num_vf_pqs, qm_info->num_vports,
680 qm_info->max_phys_tcs_per_port);
681 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
682 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
683 " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
684 qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
685 qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
686 qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
689 for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
690 port = &qm_info->qm_port_params[i];
691 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
692 "port idx %d, active %d, active_phys_tcs %d,"
693 " num_pbf_cmd_lines %d, num_btb_blocks %d,"
695 i, port->active, port->active_phys_tcs,
696 port->num_pbf_cmd_lines, port->num_btb_blocks,
701 for (i = 0; i < qm_info->num_vports; i++) {
702 vport = &qm_info->qm_vport_params[i];
703 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
704 "vport idx %d, vport_rl %d, wfq %d,"
705 " first_tx_pq_id [ ",
706 qm_info->start_vport + i, vport->vport_rl,
708 for (tc = 0; tc < NUM_OF_TCS; tc++)
709 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
710 vport->first_tx_pq_id[tc]);
711 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
715 for (i = 0; i < qm_info->num_pqs; i++) {
716 pq = &qm_info->qm_pq_params[i];
717 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
718 "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
720 qm_info->start_pq + i, pq->vport_id, pq->tc_id,
721 pq->wrr_group, pq->rl_valid);
725 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
727 /* reset params required for init run */
728 ecore_init_qm_reset_params(p_hwfn);
730 /* init QM top level params */
731 ecore_init_qm_params(p_hwfn);
733 /* init QM port params */
734 ecore_init_qm_port_params(p_hwfn);
736 /* init QM vport params */
737 ecore_init_qm_vport_params(p_hwfn);
739 /* init QM physical queue params */
740 ecore_init_qm_pq_params(p_hwfn);
742 /* display all that init */
743 ecore_dp_init_qm_params(p_hwfn);
746 /* This function reconfigures the QM pf on the fly.
747 * For this purpose we:
748 * 1. reconfigure the QM database
749 * 2. set new values to runtime array
750 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
751 * 4. activate init tool in QM_PF stage
752 * 5. send an sdm_qm_cmd through rbc interface to release the QM
754 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
755 struct ecore_ptt *p_ptt)
757 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
758 enum _ecore_status_t rc;
761 /* initialize ecore's qm data structure */
762 ecore_init_qm_info(p_hwfn);
764 /* stop PF's qm queues */
765 OSAL_SPIN_LOCK(&qm_lock);
766 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
767 qm_info->start_pq, qm_info->num_pqs);
768 OSAL_SPIN_UNLOCK(&qm_lock);
772 /* clear the QM_PF runtime phase leftovers from previous init */
773 ecore_init_clear_rt_data(p_hwfn);
775 /* prepare QM portion of runtime array */
776 ecore_qm_init_pf(p_hwfn);
778 /* activate init tool on runtime array */
779 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
780 p_hwfn->hw_info.hw_mode);
781 if (rc != ECORE_SUCCESS)
784 /* start PF's qm queues */
785 OSAL_SPIN_LOCK(&qm_lock);
786 b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
787 qm_info->start_pq, qm_info->num_pqs);
788 OSAL_SPIN_UNLOCK(&qm_lock);
792 return ECORE_SUCCESS;
795 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
797 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
798 enum _ecore_status_t rc;
800 rc = ecore_init_qm_sanity(p_hwfn);
801 if (rc != ECORE_SUCCESS)
804 qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
805 sizeof(struct init_qm_pq_params) *
806 ecore_init_qm_get_num_pqs(p_hwfn));
807 if (!qm_info->qm_pq_params)
810 qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
811 sizeof(struct init_qm_vport_params) *
812 ecore_init_qm_get_num_vports(p_hwfn));
813 if (!qm_info->qm_vport_params)
816 qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
817 sizeof(struct init_qm_port_params) *
818 p_hwfn->p_dev->num_ports_in_engines);
819 if (!qm_info->qm_port_params)
822 qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
823 sizeof(struct ecore_wfq_data) *
824 ecore_init_qm_get_num_vports(p_hwfn));
825 if (!qm_info->wfq_data)
828 return ECORE_SUCCESS;
831 DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
832 ecore_qm_info_free(p_hwfn);
835 /******************** End QM initialization ***************/
837 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
839 struct ecore_consq *p_consq;
840 struct ecore_eq *p_eq;
841 #ifdef CONFIG_ECORE_LL2
842 struct ecore_ll2_info *p_ll2_info;
844 enum _ecore_status_t rc = ECORE_SUCCESS;
850 p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
851 sizeof(*p_dev->fw_data));
855 /* Allocate Memory for the Queue->CID mapping */
856 for_each_hwfn(p_dev, i) {
857 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
858 u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
859 int tx_size, rx_size;
861 /* @@@TMP - resc management, change to actual required size */
862 if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
863 num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
864 tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
865 rx_size = sizeof(struct ecore_hw_cid_data) *
866 RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
868 p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
870 if (!p_hwfn->p_tx_cids) {
871 DP_NOTICE(p_hwfn, true,
872 "Failed to allocate memory for Tx Cids\n");
876 p_hwfn->p_rx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
878 if (!p_hwfn->p_rx_cids) {
879 DP_NOTICE(p_hwfn, true,
880 "Failed to allocate memory for Rx Cids\n");
885 for_each_hwfn(p_dev, i) {
886 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
887 u32 n_eqes, num_cons;
889 /* First allocate the context manager structure */
890 rc = ecore_cxt_mngr_alloc(p_hwfn);
894 /* Set the HW cid/tid numbers (in the contest manager)
895 * Must be done prior to any further computations.
897 rc = ecore_cxt_set_pf_params(p_hwfn);
901 rc = ecore_alloc_qm_data(p_hwfn);
906 ecore_init_qm_info(p_hwfn);
908 /* Compute the ILT client partition */
909 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
913 /* CID map / ILT shadow table / T2
914 * The talbes sizes are determined by the computations above
916 rc = ecore_cxt_tables_alloc(p_hwfn);
920 /* SPQ, must follow ILT because initializes SPQ context */
921 rc = ecore_spq_alloc(p_hwfn);
925 /* SP status block allocation */
926 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
929 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
933 rc = ecore_iov_alloc(p_hwfn);
938 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
939 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
940 /* Calculate the EQ size
941 * ---------------------
942 * Each ICID may generate up to one event at a time i.e.
943 * the event must be handled/cleared before a new one
944 * can be generated. We calculate the sum of events per
945 * protocol and create an EQ deep enough to handle the
947 * - Core - according to SPQ.
948 * - RoCE - per QP there are a couple of ICIDs, one
949 * responder and one requester, each can
950 * generate an EQE => n_eqes_qp = 2 * n_qp.
951 * Each CQ can generate an EQE. There are 2 CQs
952 * per QP => n_eqes_cq = 2 * n_qp.
953 * Hence the RoCE total is 4 * n_qp or
955 * - ENet - There can be up to two events per VF. One
956 * for VF-PF channel and another for VF FLR
957 * initial cleanup. The number of VFs is
958 * bounded by MAX_NUM_VFS_BB, and is much
959 * smaller than RoCE's so we avoid exact
962 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
964 ecore_cxt_get_proto_cid_count(
970 num_cons = ecore_cxt_get_proto_cid_count(
975 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
976 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
978 ecore_cxt_get_proto_cid_count(p_hwfn,
981 n_eqes += 2 * num_cons;
984 if (n_eqes > 0xFFFF) {
985 DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
986 "The maximum of a u16 chain is 0x%x\n",
991 p_eq = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
996 p_consq = ecore_consq_alloc(p_hwfn);
999 p_hwfn->p_consq = p_consq;
1001 #ifdef CONFIG_ECORE_LL2
1002 if (p_hwfn->using_ll2) {
1003 p_ll2_info = ecore_ll2_alloc(p_hwfn);
1006 p_hwfn->p_ll2_info = p_ll2_info;
1010 /* DMA info initialization */
1011 rc = ecore_dmae_info_alloc(p_hwfn);
1013 DP_NOTICE(p_hwfn, true,
1014 "Failed to allocate memory for dmae_info"
1019 /* DCBX initialization */
1020 rc = ecore_dcbx_info_alloc(p_hwfn);
1022 DP_NOTICE(p_hwfn, true,
1023 "Failed to allocate memory for dcbx structure\n");
1028 p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1029 sizeof(*p_dev->reset_stats));
1030 if (!p_dev->reset_stats) {
1031 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1035 return ECORE_SUCCESS;
1040 ecore_resc_free(p_dev);
1044 void ecore_resc_setup(struct ecore_dev *p_dev)
1051 for_each_hwfn(p_dev, i) {
1052 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1054 ecore_cxt_mngr_setup(p_hwfn);
1055 ecore_spq_setup(p_hwfn);
1056 ecore_eq_setup(p_hwfn, p_hwfn->p_eq);
1057 ecore_consq_setup(p_hwfn, p_hwfn->p_consq);
1059 /* Read shadow of current MFW mailbox */
1060 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1061 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1062 p_hwfn->mcp_info->mfw_mb_cur,
1063 p_hwfn->mcp_info->mfw_mb_length);
1065 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1067 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1068 #ifdef CONFIG_ECORE_LL2
1069 if (p_hwfn->using_ll2)
1070 ecore_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
1075 #define FINAL_CLEANUP_POLL_CNT (100)
1076 #define FINAL_CLEANUP_POLL_TIME (10)
1077 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1078 struct ecore_ptt *p_ptt,
1081 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1082 enum _ecore_status_t rc = ECORE_TIMEOUT;
1085 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1086 CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1087 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1088 return ECORE_SUCCESS;
1092 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1093 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1098 command |= X_FINAL_CLEANUP_AGG_INT <<
1099 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1100 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1101 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1102 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1104 /* Make sure notification is not set before initiating final cleanup */
1106 if (REG_RD(p_hwfn, addr)) {
1107 DP_NOTICE(p_hwfn, false,
1108 "Unexpected; Found final cleanup notification");
1109 DP_NOTICE(p_hwfn, false,
1110 " before initiating final cleanup\n");
1111 REG_WR(p_hwfn, addr, 0);
1114 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1115 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1118 ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1120 /* Poll until completion */
1121 while (!REG_RD(p_hwfn, addr) && count--)
1122 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1124 if (REG_RD(p_hwfn, addr))
1127 DP_NOTICE(p_hwfn, true,
1128 "Failed to receive FW final cleanup notification\n");
1130 /* Cleanup afterwards */
1131 REG_WR(p_hwfn, addr, 0);
1136 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1140 if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1141 hw_mode |= 1 << MODE_BB;
1142 } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1143 hw_mode |= 1 << MODE_K2;
1145 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1146 p_hwfn->p_dev->type);
1150 /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1151 switch (p_hwfn->p_dev->num_ports_in_engines) {
1153 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1156 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1159 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1162 DP_NOTICE(p_hwfn, true,
1163 "num_ports_in_engine = %d not supported\n",
1164 p_hwfn->p_dev->num_ports_in_engines);
1168 switch (p_hwfn->p_dev->mf_mode) {
1169 case ECORE_MF_DEFAULT:
1171 hw_mode |= 1 << MODE_MF_SI;
1173 case ECORE_MF_OVLAN:
1174 hw_mode |= 1 << MODE_MF_SD;
1177 DP_NOTICE(p_hwfn, true,
1178 "Unsupported MF mode, init as DEFAULT\n");
1179 hw_mode |= 1 << MODE_MF_SI;
1183 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1184 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1185 hw_mode |= 1 << MODE_FPGA;
1187 if (p_hwfn->p_dev->b_is_emul_full)
1188 hw_mode |= 1 << MODE_EMUL_FULL;
1190 hw_mode |= 1 << MODE_EMUL_REDUCED;
1194 hw_mode |= 1 << MODE_ASIC;
1196 if (p_hwfn->p_dev->num_hwfns > 1)
1197 hw_mode |= 1 << MODE_100G;
1199 p_hwfn->hw_info.hw_mode = hw_mode;
1201 DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1202 "Configuring function for hw_mode: 0x%08x\n",
1203 p_hwfn->hw_info.hw_mode);
1205 return ECORE_SUCCESS;
1209 /* MFW-replacement initializations for non-ASIC */
1210 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1211 struct ecore_ptt *p_ptt)
1213 struct ecore_dev *p_dev = p_hwfn->p_dev;
1217 if (CHIP_REV_IS_EMUL(p_dev)) {
1218 if (ECORE_IS_AH(p_dev))
1222 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1224 if (CHIP_REV_IS_EMUL(p_dev) &&
1225 (ECORE_IS_AH(p_dev)))
1226 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1229 /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1230 /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1231 if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1232 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1234 if (CHIP_REV_IS_EMUL(p_dev)) {
1235 if (ECORE_IS_AH(p_dev)) {
1236 /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1237 ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1238 (p_dev->num_ports_in_engines >> 1));
1240 ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1241 p_dev->num_ports_in_engines == 4 ? 0 : 3);
1246 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1247 for (i = 0; i < 100; i++) {
1249 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1253 DP_NOTICE(p_hwfn, true,
1254 "RBC done failed to complete in PSWRQ2\n");
1256 return ECORE_SUCCESS;
1260 /* Init run time data for all PFs and their VFs on an engine.
1261 * TBD - for VFs - Once we have parent PF info for each VF in
1262 * shmem available as CAU requires knowledge of parent PF for each VF.
1264 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1266 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1269 for_each_hwfn(p_dev, i) {
1270 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1271 struct ecore_igu_info *p_igu_info;
1272 struct ecore_igu_block *p_block;
1273 struct cau_sb_entry sb_entry;
1275 p_igu_info = p_hwfn->hw_info.p_igu_info;
1277 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1279 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1281 if (!p_block->is_pf)
1284 ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1285 p_block->function_id, 0, 0);
1286 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1291 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1292 struct ecore_ptt *p_ptt,
1295 struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1296 struct ecore_dev *p_dev = p_hwfn->p_dev;
1297 u8 vf_id, max_num_vfs;
1300 enum _ecore_status_t rc = ECORE_SUCCESS;
1302 ecore_init_cau_rt_data(p_dev);
1304 /* Program GTT windows */
1305 ecore_gtt_init(p_hwfn);
1308 if (CHIP_REV_IS_EMUL(p_dev)) {
1309 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1310 if (rc != ECORE_SUCCESS)
1315 if (p_hwfn->mcp_info) {
1316 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1317 qm_info->pf_rl_en = 1;
1318 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1319 qm_info->pf_wfq_en = 1;
1322 ecore_qm_common_rt_init(p_hwfn,
1323 p_dev->num_ports_in_engines,
1324 qm_info->max_phys_tcs_per_port,
1325 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1326 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1327 qm_info->qm_port_params);
1329 ecore_cxt_hw_init_common(p_hwfn);
1331 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1332 if (rc != ECORE_SUCCESS)
1335 /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1336 * need to decide with which value, maybe runtime
1338 ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1339 ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1341 if (ECORE_IS_BB(p_dev)) {
1342 /* Workaround clears ROCE search for all functions to prevent
1343 * involving non initialized function in processing ROCE packet.
1345 num_pfs = NUM_OF_ENG_PFS(p_dev);
1346 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1347 ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1348 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1349 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1351 /* pretend to original PF */
1352 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1355 /* Workaround for avoiding CCFC execution error when getting packets
1356 * with CRC errors, and allowing instead the invoking of the FW error
1358 * This is not done inside the init tool since it currently can't
1359 * perform a pretending to VFs.
1361 max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1362 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1363 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1364 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1365 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1366 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1367 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1368 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1370 /* pretend to original PF */
1371 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1377 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1378 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1380 #define PMEG_IF_BYTE_COUNT 8
1382 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1383 struct ecore_ptt *p_ptt,
1384 u32 addr, u64 data, u8 reg_type, u8 port)
1386 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1387 "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1388 ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1389 (8 << PMEG_IF_BYTE_COUNT),
1390 (reg_type << 25) | (addr << 8) | port,
1391 (u32)((data >> 32) & 0xffffffff),
1392 (u32)(data & 0xffffffff));
1394 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1395 (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1396 0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1397 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1398 (reg_type << 25) | (addr << 8) | port);
1399 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1400 ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1401 (data >> 32) & 0xffffffff);
1404 #define XLPORT_MODE_REG (0x20a)
1405 #define XLPORT_MAC_CONTROL (0x210)
1406 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1407 #define XLPORT_ENABLE_REG (0x20b)
1409 #define XLMAC_CTRL (0x600)
1410 #define XLMAC_MODE (0x601)
1411 #define XLMAC_RX_MAX_SIZE (0x608)
1412 #define XLMAC_TX_CTRL (0x604)
1413 #define XLMAC_PAUSE_CTRL (0x60d)
1414 #define XLMAC_PFC_CTRL (0x60e)
1416 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1417 struct ecore_ptt *p_ptt)
1419 u8 loopback = 0, port = p_hwfn->port_id * 2;
1421 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1423 /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1424 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1426 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1427 /* XLMAC: SOFT RESET */
1428 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1429 /* XLMAC: Port Speed >= 10Gbps */
1430 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1431 /* XLMAC: Max Size */
1432 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1433 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1434 0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1436 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1437 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1438 0x30ffffc000ULL, 0, port);
1439 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1440 port); /* XLMAC: TX_EN, RX_EN */
1441 /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1442 ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1443 0x1003 | (loopback << 2), 0, port);
1444 /* Enabled Parallel PFC interface */
1445 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1447 /* XLPORT port enable */
1448 ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1451 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1452 struct ecore_ptt *p_ptt)
1454 u8 port = p_hwfn->port_id;
1455 u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1457 DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1459 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1460 (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1462 CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1463 (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1465 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1466 1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1468 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1469 9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1471 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1472 0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1474 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1475 8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1477 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1479 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1481 ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1483 ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1487 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1488 struct ecore_ptt *p_ptt)
1490 if (ECORE_IS_AH(p_hwfn->p_dev))
1491 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1493 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1496 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1497 struct ecore_ptt *p_ptt, u8 port)
1499 int port_offset = port ? 0x800 : 0;
1500 u32 xmac_rxctrl = 0;
1503 /* FIXME: move to common start */
1504 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1505 MISC_REG_RESET_REG_2_XMAC_BIT); /* Clear */
1507 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1508 MISC_REG_RESET_REG_2_XMAC_BIT); /* Set */
1510 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1512 /* Set the number of ports on the Warp Core to 10G */
1513 ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1515 /* Soft reset of XMAC */
1516 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1517 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1519 ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1520 MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1522 /* FIXME: move to common end */
1523 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1524 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1526 /* Set Max packet size: initialize XMAC block register for port 0 */
1527 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1529 /* CRC append for Tx packets: init XMAC block register for port 1 */
1530 ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1532 /* Enable TX and RX: initialize XMAC block register for port 1 */
1533 ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1534 XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1535 xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1536 XMAC_REG_RX_CTRL_BB + port_offset);
1537 xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1538 ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1542 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1543 struct ecore_ptt *p_ptt,
1546 enum _ecore_status_t rc = ECORE_SUCCESS;
1548 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1550 if (rc != ECORE_SUCCESS)
1553 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1554 return ECORE_SUCCESS;
1556 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1557 if (ECORE_IS_AH(p_hwfn->p_dev))
1558 return ECORE_SUCCESS;
1559 else if (ECORE_IS_BB(p_hwfn->p_dev))
1560 ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1561 } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1562 if (p_hwfn->p_dev->num_hwfns > 1) {
1563 /* Activate OPTE in CMT */
1566 val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1568 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1569 ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1570 ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1571 ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1572 ecore_wr(p_hwfn, p_ptt,
1573 NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1574 ecore_wr(p_hwfn, p_ptt,
1575 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1576 ecore_wr(p_hwfn, p_ptt,
1577 NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1581 ecore_emul_link_init(p_hwfn, p_ptt);
1583 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1590 static enum _ecore_status_t
1591 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1592 struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1594 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1595 u32 dpi_bit_shift, dpi_count;
1598 /* Calculate DPI size
1599 * ------------------
1600 * The PWM region contains Doorbell Pages. The first is reserverd for
1601 * the kernel for, e.g, L2. The others are free to be used by non-
1602 * trusted applications, typically from user space. Each page, called a
1603 * doorbell page is sectioned into windows that allow doorbells to be
1604 * issued in parallel by the kernel/application. The size of such a
1605 * window (a.k.a. WID) is 1kB.
1607 * 1kB WID x N WIDS = DPI page size
1608 * DPI page size x N DPIs = PWM region size
1610 * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1611 * in order to ensure that two applications won't share the same page.
1612 * It also must contain at least one WID per CPU to allow parallelism.
1613 * It also must be a power of 2, since it is stored as a bit shift.
1615 * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1616 * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1617 * containing 4 WIDs.
1619 dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1620 dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1621 dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1622 dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1623 dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1625 dpi_count = pwm_region_size / dpi_page_size;
1627 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1628 min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1631 p_hwfn->dpi_size = dpi_page_size;
1632 p_hwfn->dpi_count = dpi_count;
1634 /* Update registers */
1635 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1637 if (dpi_count < min_dpis)
1638 return ECORE_NORESOURCES;
1640 return ECORE_SUCCESS;
1643 enum ECORE_ROCE_EDPM_MODE {
1644 ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1645 ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1646 ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1649 static enum _ecore_status_t
1650 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1651 struct ecore_ptt *p_ptt)
1653 u32 pwm_regsize, norm_regsize;
1654 u32 non_pwm_conn, min_addr_reg1;
1655 u32 db_bar_size, n_cpus;
1658 int rc = ECORE_SUCCESS;
1661 db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1662 if (p_hwfn->p_dev->num_hwfns > 1)
1665 /* Calculate doorbell regions
1666 * -----------------------------------
1667 * The doorbell BAR is made of two regions. The first is called normal
1668 * region and the second is called PWM region. In the normal region
1669 * each ICID has its own set of addresses so that writing to that
1670 * specific address identifies the ICID. In the Process Window Mode
1671 * region the ICID is given in the data written to the doorbell. The
1672 * above per PF register denotes the offset in the doorbell BAR in which
1673 * the PWM region begins.
1674 * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1675 * non-PWM connection. The calculation below computes the total non-PWM
1676 * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1677 * in units of 4,096 bytes.
1679 non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1680 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1682 ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1683 norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1684 min_addr_reg1 = norm_regsize / 4096;
1685 pwm_regsize = db_bar_size - norm_regsize;
1687 /* Check that the normal and PWM sizes are valid */
1688 if (db_bar_size < norm_regsize) {
1689 DP_ERR(p_hwfn->p_dev,
1690 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1691 db_bar_size, norm_regsize);
1692 return ECORE_NORESOURCES;
1694 if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1695 DP_ERR(p_hwfn->p_dev,
1696 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1697 pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1699 return ECORE_NORESOURCES;
1702 /* Calculate number of DPIs */
1703 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1704 if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1705 ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1706 /* Either EDPM is mandatory, or we are attempting to allocate a
1709 n_cpus = OSAL_NUM_ACTIVE_CPU();
1710 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1713 cond = ((rc) && (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1714 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1715 if (cond || p_hwfn->dcbx_no_edpm) {
1716 /* Either EDPM is disabled from user configuration, or it is
1717 * disabled via DCBx, or it is not mandatory and we failed to
1718 * allocated a WID per CPU.
1721 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1723 /* If we entered this flow due to DCBX then the DPM register is
1724 * already configured.
1729 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1730 norm_regsize, pwm_regsize);
1732 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1733 p_hwfn->dpi_size, p_hwfn->dpi_count,
1734 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1735 "disabled" : "enabled");
1737 /* Check return codes from above calls */
1740 "Failed to allocate enough DPIs\n");
1741 return ECORE_NORESOURCES;
1745 p_hwfn->dpi_start_offset = norm_regsize;
1747 /* Update registers */
1748 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1749 pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1750 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1751 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1753 return ECORE_SUCCESS;
1756 static enum _ecore_status_t
1757 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1758 struct ecore_ptt *p_ptt,
1759 struct ecore_tunn_start_params *p_tunn,
1762 enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1764 u8 rel_pf_id = p_hwfn->rel_pf_id;
1766 enum _ecore_status_t rc = ECORE_SUCCESS;
1770 if (p_hwfn->mcp_info) {
1771 struct ecore_mcp_function_info *p_info;
1773 p_info = &p_hwfn->mcp_info->func_info;
1774 if (p_info->bandwidth_min)
1775 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1777 /* Update rate limit once we'll actually have a link */
1778 p_hwfn->qm_info.pf_rl = 100000;
1780 ecore_cxt_hw_init_pf(p_hwfn);
1782 ecore_int_igu_init_rt(p_hwfn);
1784 /* Set VLAN in NIG if needed */
1785 if (hw_mode & (1 << MODE_MF_SD)) {
1786 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1787 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1788 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1789 p_hwfn->hw_info.ovlan);
1792 /* Enable classification by MAC if needed */
1793 if (hw_mode & (1 << MODE_MF_SI)) {
1794 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1795 "Configuring TAGMAC_CLS_TYPE\n");
1796 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1800 /* Protocl Configuration - @@@TBD - should we set 0 otherwise? */
1801 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1802 (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1803 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1804 (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1805 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1807 /* perform debug configuration when chip is out of reset */
1808 OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1810 /* Cleanup chip from previous driver if such remains exist */
1811 rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1812 if (rc != ECORE_SUCCESS) {
1813 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1817 /* PF Init sequence */
1818 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1822 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1823 rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1827 /* Pure runtime initializations - directly to the HW */
1828 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1830 /* PCI relaxed ordering causes a decrease in the performance on some
1831 * systems. Till a root cause is found, disable this attribute in the
1835 * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1837 * DP_NOTICE(p_hwfn, true,
1838 * "Failed to find the PCIe Cap\n");
1841 * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1842 * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1843 * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1846 rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1850 /* enable interrupts */
1851 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1852 if (rc != ECORE_SUCCESS)
1855 /* send function start command */
1856 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1857 allow_npar_tx_switch);
1859 DP_NOTICE(p_hwfn, true,
1860 "Function start ramrod failed\n");
1862 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1863 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1864 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1866 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1867 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1869 ecore_wr(p_hwfn, p_ptt,
1870 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1873 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1874 "PRS_REG_SEARCH registers after start PFn\n");
1875 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1876 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1877 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1878 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1879 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1880 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1881 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1882 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1883 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1884 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1885 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1886 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1887 prs_reg = ecore_rd(p_hwfn, p_ptt,
1888 PRS_REG_SEARCH_TCP_FIRST_FRAG);
1889 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1890 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1892 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1893 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1894 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1900 static enum _ecore_status_t
1901 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1902 struct ecore_ptt *p_ptt, u8 enable)
1904 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1906 /* Change PF in PXP */
1907 ecore_wr(p_hwfn, p_ptt,
1908 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1910 /* wait until value is set - try for 1 second every 50us */
1911 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1912 val = ecore_rd(p_hwfn, p_ptt,
1913 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1920 if (val != set_val) {
1921 DP_NOTICE(p_hwfn, true,
1922 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1923 return ECORE_UNKNOWN_ERROR;
1926 return ECORE_SUCCESS;
1929 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1930 struct ecore_ptt *p_main_ptt)
1932 /* Read shadow of current MFW mailbox */
1933 ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1934 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1935 p_hwfn->mcp_info->mfw_mb_cur,
1936 p_hwfn->mcp_info->mfw_mb_length);
1939 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1940 struct ecore_hw_init_params *p_params)
1942 enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1943 u32 load_code, param, drv_mb_param;
1944 bool b_default_mtu = true;
1945 struct ecore_hwfn *p_hwfn;
1948 if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1949 (p_dev->num_hwfns > 1)) {
1950 DP_NOTICE(p_dev, false,
1951 "MSI mode is not supported for CMT devices\n");
1956 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1957 if (rc != ECORE_SUCCESS)
1961 for_each_hwfn(p_dev, i) {
1962 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1964 /* If management didn't provide a default, set one of our own */
1965 if (!p_hwfn->hw_info.mtu) {
1966 p_hwfn->hw_info.mtu = 1500;
1967 b_default_mtu = false;
1971 p_hwfn->b_int_enabled = 1;
1975 /* Enable DMAE in PXP */
1976 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1977 if (rc != ECORE_SUCCESS)
1980 rc = ecore_calc_hw_mode(p_hwfn);
1981 if (rc != ECORE_SUCCESS)
1984 /* @@@TBD need to add here:
1985 * Check for fan failure
1988 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
1990 DP_NOTICE(p_hwfn, true,
1991 "Failed sending LOAD_REQ command\n");
1996 * When coming back from hiberbate state, the registers from
1997 * which shadow is read initially are not initialized. It turns
1998 * out that these registers get initialized during the call to
1999 * ecore_mcp_load_req request. So we need to reread them here
2000 * to get the proper shadow register value.
2001 * Note: This is a workaround for the missing MFW
2002 * initialization. It may be removed once the implementation
2005 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2007 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2008 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
2011 /* Only relevant for recovery:
2012 * Clear the indication after the LOAD_REQ command is responded
2015 p_dev->recov_in_prog = false;
2017 p_hwfn->first_on_engine = (load_code ==
2018 FW_MSG_CODE_DRV_LOAD_ENGINE);
2020 if (!qm_lock_init) {
2021 OSAL_SPIN_LOCK_INIT(&qm_lock);
2022 qm_lock_init = true;
2025 switch (load_code) {
2026 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2027 rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2028 p_hwfn->hw_info.hw_mode);
2032 case FW_MSG_CODE_DRV_LOAD_PORT:
2033 rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2034 p_hwfn->hw_info.hw_mode);
2038 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2039 rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2041 p_hwfn->hw_info.hw_mode,
2042 p_params->b_hw_start,
2044 p_params->allow_npar_tx_switch);
2051 if (rc != ECORE_SUCCESS)
2052 DP_NOTICE(p_hwfn, true,
2053 "init phase failed for loadcode 0x%x (rc %d)\n",
2056 /* ACK mfw regardless of success or failure of initialization */
2057 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2058 DRV_MSG_CODE_LOAD_DONE,
2059 0, &load_code, ¶m);
2060 if (rc != ECORE_SUCCESS)
2062 if (mfw_rc != ECORE_SUCCESS) {
2063 DP_NOTICE(p_hwfn, true,
2064 "Failed sending LOAD_DONE command\n");
2068 /* send DCBX attention request command */
2069 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2070 "sending phony dcbx set command to trigger DCBx attention handling\n");
2071 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2072 DRV_MSG_CODE_SET_DCBX,
2073 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2074 &load_code, ¶m);
2075 if (mfw_rc != ECORE_SUCCESS) {
2076 DP_NOTICE(p_hwfn, true,
2077 "Failed to send DCBX attention request\n");
2081 p_hwfn->hw_init_done = true;
2085 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2086 drv_mb_param = (FW_MAJOR_VERSION << 24) |
2087 (FW_MINOR_VERSION << 16) |
2088 (FW_REVISION_VERSION << 8) |
2089 (FW_ENGINEERING_VERSION);
2090 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2091 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2092 drv_mb_param, &load_code, ¶m);
2093 if (rc != ECORE_SUCCESS)
2094 DP_INFO(p_hwfn, "Failed to update firmware version\n");
2097 rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2098 p_hwfn->hw_info.mtu);
2099 if (rc != ECORE_SUCCESS)
2100 DP_INFO(p_hwfn, "Failed to update default mtu\n");
2102 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2104 ECORE_OV_DRIVER_STATE_DISABLED);
2105 if (rc != ECORE_SUCCESS)
2106 DP_INFO(p_hwfn, "Failed to update driver state\n");
2112 #define ECORE_HW_STOP_RETRY_LIMIT (10)
2113 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2114 struct ecore_hwfn *p_hwfn,
2115 struct ecore_ptt *p_ptt)
2120 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2121 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2122 for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2124 if ((!ecore_rd(p_hwfn, p_ptt,
2125 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2126 (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2129 /* Dependent on number of connection/tasks, possibly
2130 * 1ms sleep is required between polls
2135 if (i < ECORE_HW_STOP_RETRY_LIMIT)
2138 DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2139 " [Connection %02x Tasks %02x]\n",
2140 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2141 (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2144 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2148 for_each_hwfn(p_dev, j) {
2149 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2150 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2152 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2156 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2158 enum _ecore_status_t rc = ECORE_SUCCESS, t_rc;
2161 for_each_hwfn(p_dev, j) {
2162 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2163 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2165 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2168 ecore_vf_pf_int_cleanup(p_hwfn);
2172 /* mark the hw as uninitialized... */
2173 p_hwfn->hw_init_done = false;
2175 rc = ecore_sp_pf_stop(p_hwfn);
2177 DP_NOTICE(p_hwfn, true,
2178 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
2180 /* perform debug action after PF stop was sent */
2181 OSAL_AFTER_PF_STOP((void *)p_hwfn->p_dev, p_hwfn->my_id);
2183 /* close NIG to BRB gate */
2184 ecore_wr(p_hwfn, p_ptt,
2185 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2188 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2189 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2190 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2191 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2192 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2194 /* @@@TBD - clean transmission queues (5.b) */
2195 /* @@@TBD - clean BTB (5.c) */
2197 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2199 /* @@@TBD - verify DMAE requests are done (8) */
2201 /* Disable Attention Generation */
2202 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2203 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2204 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2205 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2206 /* Need to wait 1ms to guarantee SBs are cleared */
2211 /* Disable DMAE in PXP - in CMT, this should only be done for
2212 * first hw-function, and only after all transactions have
2213 * stopped for all active hw-functions.
2215 t_rc = ecore_change_pci_hwfn(&p_dev->hwfns[0],
2216 p_dev->hwfns[0].p_main_ptt, false);
2217 if (t_rc != ECORE_SUCCESS)
2224 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2228 for_each_hwfn(p_dev, j) {
2229 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2230 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2233 ecore_vf_pf_int_cleanup(p_hwfn);
2237 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2238 "Shutting down the fastpath\n");
2240 ecore_wr(p_hwfn, p_ptt,
2241 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2243 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2244 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2245 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2246 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2247 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2249 /* @@@TBD - clean transmission queues (5.b) */
2250 /* @@@TBD - clean BTB (5.c) */
2252 /* @@@TBD - verify DMAE requests are done (8) */
2254 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2255 /* Need to wait 1ms to guarantee SBs are cleared */
2260 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2262 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2264 if (IS_VF(p_hwfn->p_dev))
2267 /* If roce info is allocated it means roce is initialized and should
2268 * be enabled in searcher.
2270 if (p_hwfn->p_rdma_info) {
2271 if (p_hwfn->b_rdma_enabled_in_prs)
2272 ecore_wr(p_hwfn, p_ptt,
2273 p_hwfn->rdma_prs_search_reg, 0x1);
2274 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2277 /* Re-open incoming traffic */
2278 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2279 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2282 static enum _ecore_status_t ecore_reg_assert(struct ecore_hwfn *p_hwfn,
2283 struct ecore_ptt *p_ptt, u32 reg,
2286 u32 assert_val = ecore_rd(p_hwfn, p_ptt, reg);
2288 if (assert_val != expected) {
2289 DP_NOTICE(p_hwfn, true, "Value at address 0x%08x != 0x%08x\n",
2291 return ECORE_UNKNOWN_ERROR;
2297 enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev)
2299 enum _ecore_status_t rc = ECORE_SUCCESS;
2300 u32 unload_resp, unload_param;
2303 for_each_hwfn(p_dev, i) {
2304 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2307 rc = ecore_vf_pf_reset(p_hwfn);
2313 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Resetting hw/fw\n");
2315 /* Check for incorrect states */
2316 if (!p_dev->recov_in_prog) {
2317 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2318 QM_REG_USG_CNT_PF_TX, 0);
2319 ecore_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
2320 QM_REG_USG_CNT_PF_OTHER, 0);
2321 /* @@@TBD - assert on incorrect xCFC values (10.b) */
2324 /* Disable PF in HW blocks */
2325 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2326 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
2328 if (p_dev->recov_in_prog) {
2329 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2330 "Recovery is in progress -> skip sending unload_req/done\n");
2334 /* Send unload command to MCP */
2335 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2336 DRV_MSG_CODE_UNLOAD_REQ,
2337 DRV_MB_PARAM_UNLOAD_WOL_MCP,
2338 &unload_resp, &unload_param);
2339 if (rc != ECORE_SUCCESS) {
2340 DP_NOTICE(p_hwfn, true,
2341 "ecore_hw_reset: UNLOAD_REQ failed\n");
2342 /* @@TBD - what to do? for now, assume ENG. */
2343 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
2346 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2347 DRV_MSG_CODE_UNLOAD_DONE,
2348 0, &unload_resp, &unload_param);
2349 if (rc != ECORE_SUCCESS) {
2351 true, "ecore_hw_reset: UNLOAD_DONE failed\n");
2352 /* @@@TBD - Should it really ASSERT here ? */
2360 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2361 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2363 ecore_ptt_pool_free(p_hwfn);
2364 OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2367 /* Setup bar access */
2368 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2370 /* clear indirect access */
2371 if (ECORE_IS_AH(p_hwfn->p_dev)) {
2372 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2373 PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2374 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2375 PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2376 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2377 PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2378 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2379 PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2381 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2382 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2383 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2384 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2385 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2386 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2387 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2388 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2391 /* Clean Previous errors if such exist */
2392 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2393 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2395 /* enable internal target-read */
2396 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2397 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2400 static void get_function_id(struct ecore_hwfn *p_hwfn)
2403 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2404 PXP_PF_ME_OPAQUE_ADDR);
2406 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2408 /* Bits 16-19 from the ME registers are the pf_num */
2409 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2410 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2411 PXP_CONCRETE_FID_PFID);
2412 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2413 PXP_CONCRETE_FID_PORT);
2415 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2416 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2417 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2420 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2422 u32 *feat_num = p_hwfn->hw_info.feat_num;
2423 struct ecore_sb_cnt_info sb_cnt_info;
2424 int num_features = 1;
2426 /* L2 Queues require each: 1 status block. 1 L2 queue */
2427 feat_num[ECORE_PF_L2_QUE] =
2429 RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2430 RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2432 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2433 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2434 feat_num[ECORE_VF_L2_QUE] =
2436 RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2437 FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2438 sb_cnt_info.sb_iov_cnt);
2440 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2441 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
2442 (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2443 (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2444 (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2445 RESC_NUM(p_hwfn, ECORE_SB),
2449 static enum resource_id_enum
2450 ecore_hw_get_mfw_res_id(enum ecore_resources res_id)
2452 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2456 mfw_res_id = RESOURCE_NUM_SB_E;
2458 case ECORE_L2_QUEUE:
2459 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2462 mfw_res_id = RESOURCE_NUM_VPORT_E;
2465 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2468 mfw_res_id = RESOURCE_NUM_PQ_E;
2471 mfw_res_id = RESOURCE_NUM_RL_E;
2475 /* Each VFC resource can accommodate both a MAC and a VLAN */
2476 mfw_res_id = RESOURCE_VFC_FILTER_E;
2479 mfw_res_id = RESOURCE_ILT_E;
2481 case ECORE_LL2_QUEUE:
2482 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2484 case ECORE_RDMA_CNQ_RAM:
2485 case ECORE_CMDQS_CQS:
2486 /* CNQ/CMDQS are the same resource */
2487 mfw_res_id = RESOURCE_CQS_E;
2489 case ECORE_RDMA_STATS_QUEUE:
2490 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2499 static u32 ecore_hw_get_dflt_resc_num(struct ecore_hwfn *p_hwfn,
2500 enum ecore_resources res_id)
2502 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2503 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2504 struct ecore_sb_cnt_info sb_cnt_info;
2505 u32 dflt_resc_num = 0;
2509 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2510 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2511 dflt_resc_num = sb_cnt_info.sb_cnt;
2513 case ECORE_L2_QUEUE:
2514 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2515 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2518 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2519 MAX_NUM_VPORTS_BB) / num_funcs;
2522 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2523 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2526 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2527 MAX_QM_TX_QUEUES_BB) / num_funcs;
2530 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2534 /* Each VFC resource can accommodate both a MAC and a VLAN */
2535 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2538 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2539 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2541 case ECORE_LL2_QUEUE:
2542 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2544 case ECORE_RDMA_CNQ_RAM:
2545 case ECORE_CMDQS_CQS:
2546 /* CNQ/CMDQS are the same resource */
2548 dflt_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2550 case ECORE_RDMA_STATS_QUEUE:
2552 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2553 MAX_NUM_VPORTS_BB) / num_funcs;
2559 return dflt_resc_num;
2562 static const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2567 case ECORE_L2_QUEUE:
2581 case ECORE_RDMA_CNQ_RAM:
2582 return "RDMA_CNQ_RAM";
2585 case ECORE_LL2_QUEUE:
2587 case ECORE_CMDQS_CQS:
2589 case ECORE_RDMA_STATS_QUEUE:
2590 return "RDMA_STATS_QUEUE";
2592 return "UNKNOWN_RESOURCE";
2596 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2597 enum ecore_resources res_id,
2598 bool drv_resc_alloc)
2600 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
2601 u32 *p_resc_num, *p_resc_start;
2602 struct resource_info resc_info;
2603 enum _ecore_status_t rc;
2605 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2606 p_resc_start = &RESC_START(p_hwfn, res_id);
2608 dflt_resc_num = ecore_hw_get_dflt_resc_num(p_hwfn, res_id);
2609 if (!dflt_resc_num) {
2611 "Failed to get default amount for resource %d [%s]\n",
2612 res_id, ecore_hw_get_resc_name(res_id));
2615 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
2618 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2619 *p_resc_num = dflt_resc_num;
2620 *p_resc_start = dflt_resc_start;
2625 OSAL_MEM_ZERO(&resc_info, sizeof(resc_info));
2626 resc_info.res_id = ecore_hw_get_mfw_res_id(res_id);
2627 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
2629 "Failed to match resource %d with MFW resources\n",
2634 rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
2635 &mcp_resp, &mcp_param);
2636 if (rc != ECORE_SUCCESS) {
2637 DP_NOTICE(p_hwfn, true,
2638 "MFW response failure for an allocation request for"
2639 " resource %d [%s]\n",
2640 res_id, ecore_hw_get_resc_name(res_id));
2644 /* Default driver values are applied in the following cases:
2645 * - The resource allocation MB command is not supported by the MFW
2646 * - There is an internal error in the MFW while processing the request
2647 * - The resource ID is unknown to the MFW
2649 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
2650 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
2653 "Resource %d [%s]: No allocation info was received"
2654 " [mcp_resp 0x%x]. Applying default values"
2655 " [num %d, start %d].\n",
2656 res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2657 dflt_resc_num, dflt_resc_start);
2659 *p_resc_num = dflt_resc_num;
2660 *p_resc_start = dflt_resc_start;
2664 /* TBD - remove this when revising the handling of the SB resource */
2665 if (res_id == ECORE_SB) {
2666 /* Excluding the slowpath SB */
2667 resc_info.size -= 1;
2668 resc_info.offset -= p_hwfn->enabled_func_idx;
2671 *p_resc_num = resc_info.size;
2672 *p_resc_start = resc_info.offset;
2674 if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2676 "Resource %d [%s]: MFW allocation [num %d, start %d] differs from default values [num %d, start %d]%s\n",
2677 res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2678 *p_resc_start, dflt_resc_num, dflt_resc_start,
2679 drv_resc_alloc ? " - Applying default values" : "");
2680 if (drv_resc_alloc) {
2681 *p_resc_num = dflt_resc_num;
2682 *p_resc_start = dflt_resc_start;
2686 return ECORE_SUCCESS;
2689 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2690 bool drv_resc_alloc)
2692 bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2693 enum _ecore_status_t rc;
2696 u32 *resc_start = p_hwfn->hw_info.resc_start;
2697 u32 *resc_num = p_hwfn->hw_info.resc_num;
2698 /* For AH, an equal share of the ILT lines between the maximal number of
2699 * PFs is not enough for RoCE. This would be solved by the future
2700 * resource allocation scheme, but isn't currently present for
2701 * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2702 * to work - the BB number of ILT lines divided by its max PFs number.
2704 u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2707 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2708 rc = ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2709 if (rc != ECORE_SUCCESS)
2714 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2715 /* Reduced build contains less PQs */
2716 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2717 resc_num[ECORE_PQ] = 32;
2718 resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2719 p_hwfn->enabled_func_idx;
2722 /* For AH emulation, since we have a possible maximal number of
2723 * 16 enabled PFs, in case there are not enough ILT lines -
2724 * allocate only first PF as RoCE and have all the other ETH
2725 * only with less ILT lines.
2727 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2728 resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2729 resc_num[ECORE_ILT],
2730 roce_min_ilt_lines);
2733 /* Correct the common ILT calculation if PF0 has more */
2734 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2735 p_hwfn->p_dev->b_is_emul_full &&
2736 p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2737 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2738 resc_num[ECORE_ILT];
2741 /* Sanity for ILT */
2742 if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2743 (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2744 DP_NOTICE(p_hwfn, true,
2745 "Can't assign ILT pages [%08x,...,%08x]\n",
2746 RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2752 ecore_hw_set_feat(p_hwfn);
2754 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2755 "The numbers for each resource are:\n");
2756 for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2757 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2758 ecore_hw_get_resc_name(res_id),
2759 RESC_NUM(p_hwfn, res_id),
2760 RESC_START(p_hwfn, res_id));
2762 return ECORE_SUCCESS;
2765 static enum _ecore_status_t
2766 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2767 struct ecore_ptt *p_ptt,
2768 struct ecore_hw_prepare_params *p_params)
2770 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2771 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2772 struct ecore_mcp_link_params *link;
2773 enum _ecore_status_t rc;
2775 /* Read global nvm_cfg address */
2776 nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2778 /* Verify MCP has initialized it */
2779 if (!nvm_cfg_addr) {
2780 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2781 if (p_params->b_relaxed_probe)
2782 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2786 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2788 nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2790 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2791 OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2794 core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2796 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2797 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2798 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2799 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2801 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2802 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2804 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2805 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2807 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2808 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2810 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2811 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2813 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2814 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2816 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2817 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2819 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2820 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2822 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2823 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2825 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2826 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2828 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2829 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2832 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2837 /* Read DCBX configuration */
2838 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2839 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2840 dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2842 OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2843 dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2844 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2845 switch (dcbx_mode) {
2846 case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2847 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2849 case NVM_CFG1_PORT_DCBX_MODE_CEE:
2850 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2852 case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2853 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2856 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2859 /* Read default link configuration */
2860 link = &p_hwfn->mcp_info->link_input;
2861 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2862 OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2863 link_temp = ecore_rd(p_hwfn, p_ptt,
2865 OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2866 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2867 link->speed.advertised_speeds = link_temp;
2869 link_temp = link->speed.advertised_speeds;
2870 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2872 link_temp = ecore_rd(p_hwfn, p_ptt,
2874 OFFSETOF(struct nvm_cfg1_port, link_settings));
2875 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2876 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2877 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2878 link->speed.autoneg = true;
2880 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2881 link->speed.forced_speed = 1000;
2883 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2884 link->speed.forced_speed = 10000;
2886 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2887 link->speed.forced_speed = 25000;
2889 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2890 link->speed.forced_speed = 40000;
2892 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2893 link->speed.forced_speed = 50000;
2895 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2896 link->speed.forced_speed = 100000;
2899 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2902 p_hwfn->mcp_info->link_capabilities.default_speed =
2903 link->speed.forced_speed;
2904 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2905 link->speed.autoneg;
2907 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2908 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2909 link->pause.autoneg = !!(link_temp &
2910 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2911 link->pause.forced_rx = !!(link_temp &
2912 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2913 link->pause.forced_tx = !!(link_temp &
2914 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2915 link->loopback_mode = 0;
2917 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2918 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2919 link->speed.forced_speed, link->speed.advertised_speeds,
2920 link->speed.autoneg, link->pause.autoneg);
2922 /* Read Multi-function information from shmem */
2923 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2924 OFFSETOF(struct nvm_cfg1, glob) +
2925 OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
2927 generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
2929 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2930 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2933 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2934 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
2936 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2937 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
2939 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2940 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
2943 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2944 p_hwfn->p_dev->mf_mode);
2946 /* Read Multi-function information from shmem */
2947 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2948 OFFSETOF(struct nvm_cfg1, glob) +
2949 OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
2951 device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
2952 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2953 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
2954 &p_hwfn->hw_info.device_capabilities);
2955 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2956 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
2957 &p_hwfn->hw_info.device_capabilities);
2958 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2959 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
2960 &p_hwfn->hw_info.device_capabilities);
2961 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2962 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
2963 &p_hwfn->hw_info.device_capabilities);
2964 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
2965 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
2966 &p_hwfn->hw_info.device_capabilities);
2968 rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2969 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
2971 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
2977 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
2978 struct ecore_ptt *p_ptt)
2980 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2981 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2982 struct ecore_dev *p_dev = p_hwfn->p_dev;
2984 num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2986 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2987 * in the other bits are selected.
2988 * Bits 1-15 are for functions 1-15, respectively, and their value is
2989 * '0' only for enabled functions (function 0 always exists and
2991 * In case of CMT in BB, only the "even" functions are enabled, and thus
2992 * the number of functions for both hwfns is learnt from the same bits.
2994 if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
2995 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
2996 MISCS_REG_FUNCTION_HIDE_BB_K2);
2998 reg_function_hide = 0;
3001 if (reg_function_hide & 0x1) {
3002 if (ECORE_IS_BB(p_dev)) {
3003 if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3015 /* Get the number of the enabled functions on the engine */
3016 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3023 /* Get the PF index within the enabled functions */
3024 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3025 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3033 p_hwfn->num_funcs_on_engine = num_funcs;
3034 p_hwfn->enabled_func_idx = enabled_func_idx;
3037 if (CHIP_REV_IS_FPGA(p_dev)) {
3038 DP_NOTICE(p_hwfn, false,
3039 "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3040 p_hwfn->num_funcs_on_engine = 4;
3044 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3045 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3046 p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3047 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3050 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3051 struct ecore_ptt *p_ptt)
3056 /* Read the port mode */
3057 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3059 else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3060 (p_hwfn->p_dev->num_hwfns > 1))
3061 /* In CMT on emulation, assume 1 port */
3065 port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3067 if (port_mode < 3) {
3068 p_hwfn->p_dev->num_ports_in_engines = 1;
3069 } else if (port_mode <= 5) {
3070 p_hwfn->p_dev->num_ports_in_engines = 2;
3072 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3073 p_hwfn->p_dev->num_ports_in_engines);
3075 /* Default num_ports_in_engines to something */
3076 p_hwfn->p_dev->num_ports_in_engines = 1;
3080 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3081 struct ecore_ptt *p_ptt)
3086 p_hwfn->p_dev->num_ports_in_engines = 0;
3089 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3090 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3091 switch ((port & 0xf000) >> 12) {
3093 p_hwfn->p_dev->num_ports_in_engines = 1;
3096 p_hwfn->p_dev->num_ports_in_engines = 2;
3099 p_hwfn->p_dev->num_ports_in_engines = 4;
3102 DP_NOTICE(p_hwfn, false,
3103 "Unknown port mode in ECO_RESERVED %08x\n",
3108 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3109 port = ecore_rd(p_hwfn, p_ptt,
3110 CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3113 p_hwfn->p_dev->num_ports_in_engines++;
3117 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3118 struct ecore_ptt *p_ptt)
3120 if (ECORE_IS_BB(p_hwfn->p_dev))
3121 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3123 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3126 static enum _ecore_status_t
3127 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3128 enum ecore_pci_personality personality,
3129 struct ecore_hw_prepare_params *p_params)
3131 bool drv_resc_alloc = p_params->drv_resc_alloc;
3132 enum _ecore_status_t rc;
3134 /* Since all information is common, only first hwfns should do this */
3135 if (IS_LEAD_HWFN(p_hwfn)) {
3136 rc = ecore_iov_hw_info(p_hwfn);
3137 if (rc != ECORE_SUCCESS) {
3138 if (p_params->b_relaxed_probe)
3139 p_params->p_relaxed_res =
3140 ECORE_HW_PREPARE_BAD_IOV;
3146 /* TODO In get_hw_info, amoungst others:
3147 * Get MCP FW revision and determine according to it the supported
3148 * featrues (e.g. DCB)
3150 * ecore_get_pcie_width_speed, WOL capability.
3151 * Number of global CQ-s (for storage
3153 ecore_hw_info_port_num(p_hwfn, p_ptt);
3156 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3158 rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3159 if (rc != ECORE_SUCCESS)
3165 rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3166 if (rc != ECORE_SUCCESS) {
3167 if (p_params->b_relaxed_probe)
3168 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3174 if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3176 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3177 p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3180 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3182 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3183 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3187 if (ecore_mcp_is_init(p_hwfn)) {
3188 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3189 p_hwfn->hw_info.ovlan =
3190 p_hwfn->mcp_info->func_info.ovlan;
3192 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3195 if (personality != ECORE_PCI_DEFAULT) {
3196 p_hwfn->hw_info.personality = personality;
3197 } else if (ecore_mcp_is_init(p_hwfn)) {
3198 enum ecore_pci_personality protocol;
3200 protocol = p_hwfn->mcp_info->func_info.protocol;
3201 p_hwfn->hw_info.personality = protocol;
3205 /* To overcome ILT lack for emulation, until at least until we'll have
3206 * a definite answer from system about it, allow only PF0 to be RoCE.
3208 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3209 if (!p_hwfn->rel_pf_id)
3210 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3212 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3216 /* although in BB some constellations may support more than 4 tcs,
3217 * that can result in performance penalty in some cases. 4
3218 * represents a good tradeoff between performance and flexibility.
3220 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3222 /* start out with a single active tc. This can be increased either
3223 * by dcbx negotiation or by upper layer driver
3225 p_hwfn->hw_info.num_active_tc = 1;
3227 ecore_get_num_funcs(p_hwfn, p_ptt);
3229 if (ecore_mcp_is_init(p_hwfn))
3230 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3232 /* In case of forcing the driver's default resource allocation, calling
3233 * ecore_hw_get_resc() should come after initializing the personality
3234 * and after getting the number of functions, since the calculation of
3235 * the resources/features depends on them.
3236 * This order is not harmful if not forcing.
3238 rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3239 if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3241 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3247 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3249 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3252 /* Read Vendor Id / Device Id */
3253 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3255 OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3258 /* Determine type */
3259 if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3260 p_dev->type = ECORE_DEV_TYPE_AH;
3262 p_dev->type = ECORE_DEV_TYPE_BB;
3264 p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3265 MISCS_REG_CHIP_NUM);
3266 p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3267 MISCS_REG_CHIP_REV);
3269 MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3271 /* Learn number of HW-functions */
3272 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3273 MISCS_REG_CMT_ENABLED_FOR_PAIR);
3275 if (tmp & (1 << p_hwfn->rel_pf_id)) {
3276 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3277 p_dev->num_hwfns = 2;
3279 p_dev->num_hwfns = 1;
3283 if (CHIP_REV_IS_EMUL(p_dev)) {
3284 /* For some reason we have problems with this register
3285 * in B0 emulation; Simply assume no CMT
3287 DP_NOTICE(p_dev->hwfns, false,
3288 "device on emul - assume no CMT\n");
3289 p_dev->num_hwfns = 1;
3293 p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3294 MISCS_REG_CHIP_TEST_REG) >> 4;
3295 MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3296 p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3297 MISCS_REG_CHIP_METAL);
3298 MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3299 DP_INFO(p_dev->hwfns,
3300 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3301 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3302 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3303 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3306 if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3307 DP_NOTICE(p_dev->hwfns, false,
3308 "The chip type/rev (BB A0) is not supported!\n");
3309 return ECORE_ABORTED;
3312 if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3313 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3314 MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3316 if (CHIP_REV_IS_EMUL(p_dev)) {
3317 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3318 MISCS_REG_ECO_RESERVED);
3319 if (tmp & (1 << 29)) {
3320 DP_NOTICE(p_hwfn, false,
3321 "Emulation: Running on a FULL build\n");
3322 p_dev->b_is_emul_full = true;
3324 DP_NOTICE(p_hwfn, false,
3325 "Emulation: Running on a REDUCED build\n");
3330 return ECORE_SUCCESS;
3333 #ifndef LINUX_REMOVE
3334 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3341 for_each_hwfn(p_dev, j) {
3342 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3344 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3345 "Mark hw/fw uninitialized\n");
3347 p_hwfn->hw_init_done = false;
3348 p_hwfn->first_on_engine = false;
3350 ecore_ptt_invalidate(p_hwfn);
3355 static enum _ecore_status_t
3356 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3357 void OSAL_IOMEM * p_regview,
3358 void OSAL_IOMEM * p_doorbells,
3359 struct ecore_hw_prepare_params *p_params)
3361 struct ecore_dev *p_dev = p_hwfn->p_dev;
3362 struct ecore_mdump_info mdump_info;
3363 enum _ecore_status_t rc = ECORE_SUCCESS;
3365 /* Split PCI bars evenly between hwfns */
3366 p_hwfn->regview = p_regview;
3367 p_hwfn->doorbells = p_doorbells;
3370 return ecore_vf_hw_prepare(p_hwfn);
3372 /* Validate that chip access is feasible */
3373 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3375 "Reading the ME register returns all Fs; Preventing further chip access\n");
3376 if (p_params->b_relaxed_probe)
3377 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3381 get_function_id(p_hwfn);
3383 /* Allocate PTT pool */
3384 rc = ecore_ptt_pool_alloc(p_hwfn);
3386 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3387 if (p_params->b_relaxed_probe)
3388 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3392 /* Allocate the main PTT */
3393 p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3395 /* First hwfn learns basic information, e.g., number of hwfns */
3396 if (!p_hwfn->my_id) {
3397 rc = ecore_get_dev_info(p_dev);
3398 if (rc != ECORE_SUCCESS) {
3399 if (p_params->b_relaxed_probe)
3400 p_params->p_relaxed_res =
3401 ECORE_HW_PREPARE_FAILED_DEV;
3406 ecore_hw_hwfn_prepare(p_hwfn);
3408 /* Initialize MCP structure */
3409 rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3411 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3412 if (p_params->b_relaxed_probe)
3413 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3417 /* Read the device configuration information from the HW and SHMEM */
3418 rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3419 p_params->personality, p_params);
3421 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3425 /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3426 * called, since among others it sets the ports number in an engine.
3428 if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3429 !p_dev->recov_in_prog) {
3430 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3431 if (rc != ECORE_SUCCESS)
3432 DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3435 /* Check if mdump logs are present and update the epoch value */
3436 if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3437 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3439 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3440 DP_NOTICE(p_hwfn, false,
3441 "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3444 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3448 /* Allocate the init RT array and initialize the init-ops engine */
3449 rc = ecore_init_alloc(p_hwfn);
3451 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3452 if (p_params->b_relaxed_probe)
3453 p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3457 if (CHIP_REV_IS_FPGA(p_dev)) {
3458 DP_NOTICE(p_hwfn, false,
3459 "FPGA: workaround; Prevent DMAE parities\n");
3460 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3463 DP_NOTICE(p_hwfn, false,
3464 "FPGA: workaround: Set VF bar0 size\n");
3465 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3466 PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3472 if (IS_LEAD_HWFN(p_hwfn))
3473 ecore_iov_free_hw_info(p_dev);
3474 ecore_mcp_free(p_hwfn);
3476 ecore_hw_hwfn_free(p_hwfn);
3481 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3482 struct ecore_hw_prepare_params *p_params)
3484 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3485 enum _ecore_status_t rc;
3487 p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3489 if (p_params->b_relaxed_probe)
3490 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3492 /* Store the precompiled init data ptrs */
3494 ecore_init_iro_array(p_dev);
3496 /* Initialize the first hwfn - will learn number of hwfns */
3497 rc = ecore_hw_prepare_single(p_hwfn,
3499 p_dev->doorbells, p_params);
3500 if (rc != ECORE_SUCCESS)
3503 p_params->personality = p_hwfn->hw_info.personality;
3505 /* initilalize 2nd hwfn if necessary */
3506 if (p_dev->num_hwfns > 1) {
3507 void OSAL_IOMEM *p_regview, *p_doorbell;
3508 u8 OSAL_IOMEM *addr;
3510 /* adjust bar offset for second engine */
3511 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3512 ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3513 p_regview = (void OSAL_IOMEM *)addr;
3515 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3516 ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3517 p_doorbell = (void OSAL_IOMEM *)addr;
3519 /* prepare second hw function */
3520 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3521 p_doorbell, p_params);
3523 /* in case of error, need to free the previously
3524 * initiliazed hwfn 0.
3526 if (rc != ECORE_SUCCESS) {
3527 if (p_params->b_relaxed_probe)
3528 p_params->p_relaxed_res =
3529 ECORE_HW_PREPARE_FAILED_ENG2;
3532 ecore_init_free(p_hwfn);
3533 ecore_mcp_free(p_hwfn);
3534 ecore_hw_hwfn_free(p_hwfn);
3536 DP_NOTICE(p_dev, true,
3537 "What do we need to free when VF hwfn1 init fails\n");
3546 void ecore_hw_remove(struct ecore_dev *p_dev)
3548 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3552 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3553 ECORE_OV_DRIVER_STATE_NOT_LOADED);
3555 for_each_hwfn(p_dev, i) {
3556 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3559 ecore_vf_pf_release(p_hwfn);
3563 ecore_init_free(p_hwfn);
3564 ecore_hw_hwfn_free(p_hwfn);
3565 ecore_mcp_free(p_hwfn);
3567 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3570 ecore_iov_free_hw_info(p_dev);
3573 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3574 struct ecore_chain *p_chain)
3576 void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3577 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3578 struct ecore_chain_next *p_next;
3584 size = p_chain->elem_size * p_chain->usable_per_page;
3586 for (i = 0; i < p_chain->page_cnt; i++) {
3590 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3591 p_virt_next = p_next->next_virt;
3592 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3594 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3595 ECORE_CHAIN_PAGE_SIZE);
3597 p_virt = p_virt_next;
3598 p_phys = p_phys_next;
3602 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3603 struct ecore_chain *p_chain)
3605 if (!p_chain->p_virt_addr)
3608 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3609 p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3612 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3613 struct ecore_chain *p_chain)
3615 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3616 u8 *p_pbl_virt = (u8 *)p_chain->pbl.p_virt_table;
3617 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3619 if (!pp_virt_addr_tbl)
3622 if (!p_chain->pbl.p_virt_table)
3625 for (i = 0; i < page_cnt; i++) {
3626 if (!pp_virt_addr_tbl[i])
3629 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3630 *(dma_addr_t *)p_pbl_virt,
3631 ECORE_CHAIN_PAGE_SIZE);
3633 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3636 pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3638 if (!p_chain->pbl.external)
3639 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl.p_virt_table,
3640 p_chain->pbl.p_phys_table, pbl_size);
3642 OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3645 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3647 switch (p_chain->mode) {
3648 case ECORE_CHAIN_MODE_NEXT_PTR:
3649 ecore_chain_free_next_ptr(p_dev, p_chain);
3651 case ECORE_CHAIN_MODE_SINGLE:
3652 ecore_chain_free_single(p_dev, p_chain);
3654 case ECORE_CHAIN_MODE_PBL:
3655 ecore_chain_free_pbl(p_dev, p_chain);
3660 static enum _ecore_status_t
3661 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3662 enum ecore_chain_cnt_type cnt_type,
3663 osal_size_t elem_size, u32 page_cnt)
3665 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3667 /* The actual chain size can be larger than the maximal possible value
3668 * after rounding up the requested elements number to pages, and after
3669 * taking into acount the unusuable elements (next-ptr elements).
3670 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3671 * size/capacity fields are of a u32 type.
3673 if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3674 chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3675 (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3676 chain_size > ECORE_U32_MAX)) {
3677 DP_NOTICE(p_dev, true,
3678 "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3679 (unsigned long)chain_size);
3683 return ECORE_SUCCESS;
3686 static enum _ecore_status_t
3687 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3689 void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3690 dma_addr_t p_phys = 0;
3693 for (i = 0; i < p_chain->page_cnt; i++) {
3694 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3695 ECORE_CHAIN_PAGE_SIZE);
3697 DP_NOTICE(p_dev, true,
3698 "Failed to allocate chain memory\n");
3703 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3704 ecore_chain_reset(p_chain);
3706 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3710 p_virt_prev = p_virt;
3712 /* Last page's next element should point to the beginning of the
3715 ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3716 p_chain->p_virt_addr,
3717 p_chain->p_phys_addr);
3719 return ECORE_SUCCESS;
3722 static enum _ecore_status_t
3723 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3725 dma_addr_t p_phys = 0;
3726 void *p_virt = OSAL_NULL;
3728 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3730 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3734 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3735 ecore_chain_reset(p_chain);
3737 return ECORE_SUCCESS;
3740 static enum _ecore_status_t
3741 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3742 struct ecore_chain *p_chain,
3743 struct ecore_chain_ext_pbl *ext_pbl)
3745 void *p_virt = OSAL_NULL;
3746 u8 *p_pbl_virt = OSAL_NULL;
3747 void **pp_virt_addr_tbl = OSAL_NULL;
3748 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3749 u32 page_cnt = p_chain->page_cnt, size, i;
3751 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3752 pp_virt_addr_tbl = (void **)OSAL_VALLOC(p_dev, size);
3753 if (!pp_virt_addr_tbl) {
3754 DP_NOTICE(p_dev, true,
3755 "Failed to allocate memory for the chain virtual addresses table\n");
3758 OSAL_MEM_ZERO(pp_virt_addr_tbl, size);
3760 /* The allocation of the PBL table is done with its full size, since it
3761 * is expected to be successive.
3762 * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3763 * failure, since pp_virt_addr_tbl was previously allocated, and it
3764 * should be saved to allow its freeing during the error flow.
3766 size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3768 if (ext_pbl == OSAL_NULL) {
3769 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3771 p_pbl_virt = ext_pbl->p_pbl_virt;
3772 p_pbl_phys = ext_pbl->p_pbl_phys;
3773 p_chain->pbl.external = true;
3776 ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3779 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3783 for (i = 0; i < page_cnt; i++) {
3784 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3785 ECORE_CHAIN_PAGE_SIZE);
3787 DP_NOTICE(p_dev, true,
3788 "Failed to allocate chain memory\n");
3793 ecore_chain_init_mem(p_chain, p_virt, p_phys);
3794 ecore_chain_reset(p_chain);
3797 /* Fill the PBL table with the physical address of the page */
3798 *(dma_addr_t *)p_pbl_virt = p_phys;
3799 /* Keep the virtual address of the page */
3800 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3802 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3805 return ECORE_SUCCESS;
3808 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3809 enum ecore_chain_use_mode intended_use,
3810 enum ecore_chain_mode mode,
3811 enum ecore_chain_cnt_type cnt_type,
3812 u32 num_elems, osal_size_t elem_size,
3813 struct ecore_chain *p_chain,
3814 struct ecore_chain_ext_pbl *ext_pbl)
3817 enum _ecore_status_t rc = ECORE_SUCCESS;
3819 if (mode == ECORE_CHAIN_MODE_SINGLE)
3822 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3824 rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3827 DP_NOTICE(p_dev, true,
3828 "Cannot allocate a chain with the given arguments:\n"
3829 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3830 intended_use, mode, cnt_type, num_elems, elem_size);
3834 ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3835 mode, cnt_type, p_dev->dp_ctx);
3838 case ECORE_CHAIN_MODE_NEXT_PTR:
3839 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3841 case ECORE_CHAIN_MODE_SINGLE:
3842 rc = ecore_chain_alloc_single(p_dev, p_chain);
3844 case ECORE_CHAIN_MODE_PBL:
3845 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3851 return ECORE_SUCCESS;
3854 ecore_chain_free(p_dev, p_chain);
3858 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3859 u16 src_id, u16 *dst_id)
3861 if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3864 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3865 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3866 DP_NOTICE(p_hwfn, true,
3867 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3873 *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3875 return ECORE_SUCCESS;
3878 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3879 u8 src_id, u8 *dst_id)
3881 if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3884 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3885 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3886 DP_NOTICE(p_hwfn, true,
3887 "vport id [%d] is not valid, available indices [%d - %d]\n",
3893 *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3895 return ECORE_SUCCESS;
3898 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3899 u8 src_id, u8 *dst_id)
3901 if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3904 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3905 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3906 DP_NOTICE(p_hwfn, true,
3907 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3913 *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3915 return ECORE_SUCCESS;
3918 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3919 struct ecore_ptt *p_ptt,
3925 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3926 return ECORE_SUCCESS;
3928 high = p_filter[1] | (p_filter[0] << 8);
3929 low = p_filter[5] | (p_filter[4] << 8) |
3930 (p_filter[3] << 16) | (p_filter[2] << 24);
3932 /* Find a free entry and utilize it */
3933 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3934 en = ecore_rd(p_hwfn, p_ptt,
3935 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3938 ecore_wr(p_hwfn, p_ptt,
3939 NIG_REG_LLH_FUNC_FILTER_VALUE +
3940 2 * i * sizeof(u32), low);
3941 ecore_wr(p_hwfn, p_ptt,
3942 NIG_REG_LLH_FUNC_FILTER_VALUE +
3943 (2 * i + 1) * sizeof(u32), high);
3944 ecore_wr(p_hwfn, p_ptt,
3945 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3946 ecore_wr(p_hwfn, p_ptt,
3947 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3948 i * sizeof(u32), 0);
3949 ecore_wr(p_hwfn, p_ptt,
3950 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3953 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3954 DP_NOTICE(p_hwfn, false,
3955 "Failed to find an empty LLH filter to utilize\n");
3959 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3960 "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
3961 p_filter[0], p_filter[1], p_filter[2],
3962 p_filter[3], p_filter[4], p_filter[5], i);
3964 return ECORE_SUCCESS;
3967 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
3968 struct ecore_ptt *p_ptt, u8 *p_filter)
3973 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3976 high = p_filter[1] | (p_filter[0] << 8);
3977 low = p_filter[5] | (p_filter[4] << 8) |
3978 (p_filter[3] << 16) | (p_filter[2] << 24);
3980 /* Find the entry and clean it */
3981 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3982 if (ecore_rd(p_hwfn, p_ptt,
3983 NIG_REG_LLH_FUNC_FILTER_VALUE +
3984 2 * i * sizeof(u32)) != low)
3986 if (ecore_rd(p_hwfn, p_ptt,
3987 NIG_REG_LLH_FUNC_FILTER_VALUE +
3988 (2 * i + 1) * sizeof(u32)) != high)
3991 ecore_wr(p_hwfn, p_ptt,
3992 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3993 ecore_wr(p_hwfn, p_ptt,
3994 NIG_REG_LLH_FUNC_FILTER_VALUE +
3995 2 * i * sizeof(u32), 0);
3996 ecore_wr(p_hwfn, p_ptt,
3997 NIG_REG_LLH_FUNC_FILTER_VALUE +
3998 (2 * i + 1) * sizeof(u32), 0);
4001 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4002 DP_NOTICE(p_hwfn, false,
4003 "Tried to remove a non-configured filter\n");
4006 enum _ecore_status_t
4007 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4008 struct ecore_ptt *p_ptt,
4009 u16 source_port_or_eth_type,
4011 enum ecore_llh_port_filter_type_t type)
4016 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4017 return ECORE_SUCCESS;
4022 case ECORE_LLH_FILTER_ETHERTYPE:
4023 high = source_port_or_eth_type;
4025 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4026 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4027 low = source_port_or_eth_type << 16;
4029 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4030 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4033 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4034 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4035 low = (source_port_or_eth_type << 16) | dest_port;
4038 DP_NOTICE(p_hwfn, true,
4039 "Non valid LLH protocol filter type %d\n", type);
4042 /* Find a free entry and utilize it */
4043 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4044 en = ecore_rd(p_hwfn, p_ptt,
4045 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4048 ecore_wr(p_hwfn, p_ptt,
4049 NIG_REG_LLH_FUNC_FILTER_VALUE +
4050 2 * i * sizeof(u32), low);
4051 ecore_wr(p_hwfn, p_ptt,
4052 NIG_REG_LLH_FUNC_FILTER_VALUE +
4053 (2 * i + 1) * sizeof(u32), high);
4054 ecore_wr(p_hwfn, p_ptt,
4055 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4056 ecore_wr(p_hwfn, p_ptt,
4057 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4058 i * sizeof(u32), 1 << type);
4059 ecore_wr(p_hwfn, p_ptt,
4060 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4063 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4064 DP_NOTICE(p_hwfn, false,
4065 "Failed to find an empty LLH filter to utilize\n");
4066 return ECORE_NORESOURCES;
4069 case ECORE_LLH_FILTER_ETHERTYPE:
4070 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4071 "ETH type %x is added at %d\n",
4072 source_port_or_eth_type, i);
4074 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4075 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4076 "TCP src port %x is added at %d\n",
4077 source_port_or_eth_type, i);
4079 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4080 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4081 "UDP src port %x is added at %d\n",
4082 source_port_or_eth_type, i);
4084 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4085 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4086 "TCP dst port %x is added at %d\n", dest_port, i);
4088 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4089 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4090 "UDP dst port %x is added at %d\n", dest_port, i);
4092 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4093 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4094 "TCP src/dst ports %x/%x are added at %d\n",
4095 source_port_or_eth_type, dest_port, i);
4097 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4098 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4099 "UDP src/dst ports %x/%x are added at %d\n",
4100 source_port_or_eth_type, dest_port, i);
4103 return ECORE_SUCCESS;
4107 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4108 struct ecore_ptt *p_ptt,
4109 u16 source_port_or_eth_type,
4111 enum ecore_llh_port_filter_type_t type)
4116 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4122 case ECORE_LLH_FILTER_ETHERTYPE:
4123 high = source_port_or_eth_type;
4125 case ECORE_LLH_FILTER_TCP_SRC_PORT:
4126 case ECORE_LLH_FILTER_UDP_SRC_PORT:
4127 low = source_port_or_eth_type << 16;
4129 case ECORE_LLH_FILTER_TCP_DEST_PORT:
4130 case ECORE_LLH_FILTER_UDP_DEST_PORT:
4133 case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4134 case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4135 low = (source_port_or_eth_type << 16) | dest_port;
4138 DP_NOTICE(p_hwfn, true,
4139 "Non valid LLH protocol filter type %d\n", type);
4143 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4144 if (!ecore_rd(p_hwfn, p_ptt,
4145 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4147 if (!ecore_rd(p_hwfn, p_ptt,
4148 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4150 if (!(ecore_rd(p_hwfn, p_ptt,
4151 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4152 i * sizeof(u32)) & (1 << type)))
4154 if (ecore_rd(p_hwfn, p_ptt,
4155 NIG_REG_LLH_FUNC_FILTER_VALUE +
4156 2 * i * sizeof(u32)) != low)
4158 if (ecore_rd(p_hwfn, p_ptt,
4159 NIG_REG_LLH_FUNC_FILTER_VALUE +
4160 (2 * i + 1) * sizeof(u32)) != high)
4163 ecore_wr(p_hwfn, p_ptt,
4164 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4165 ecore_wr(p_hwfn, p_ptt,
4166 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4167 ecore_wr(p_hwfn, p_ptt,
4168 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4169 i * sizeof(u32), 0);
4170 ecore_wr(p_hwfn, p_ptt,
4171 NIG_REG_LLH_FUNC_FILTER_VALUE +
4172 2 * i * sizeof(u32), 0);
4173 ecore_wr(p_hwfn, p_ptt,
4174 NIG_REG_LLH_FUNC_FILTER_VALUE +
4175 (2 * i + 1) * sizeof(u32), 0);
4179 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4180 DP_NOTICE(p_hwfn, false,
4181 "Tried to remove a non-configured filter\n");
4184 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4185 struct ecore_ptt *p_ptt)
4189 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4192 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4193 ecore_wr(p_hwfn, p_ptt,
4194 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4195 ecore_wr(p_hwfn, p_ptt,
4196 NIG_REG_LLH_FUNC_FILTER_VALUE +
4197 2 * i * sizeof(u32), 0);
4198 ecore_wr(p_hwfn, p_ptt,
4199 NIG_REG_LLH_FUNC_FILTER_VALUE +
4200 (2 * i + 1) * sizeof(u32), 0);
4204 enum _ecore_status_t
4205 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4206 struct ecore_ptt *p_ptt)
4208 if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4209 ecore_wr(p_hwfn, p_ptt,
4210 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4211 1 << p_hwfn->abs_pf_id / 2);
4212 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4213 return ECORE_SUCCESS;
4216 DP_NOTICE(p_hwfn, false,
4217 "This function can't be set as default\n");
4221 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4222 struct ecore_ptt *p_ptt,
4223 u32 hw_addr, void *p_eth_qzone,
4224 osal_size_t eth_qzone_size,
4227 struct coalescing_timeset *p_coal_timeset;
4229 if (IS_VF(p_hwfn->p_dev)) {
4230 DP_NOTICE(p_hwfn, true, "VF coalescing config not supported\n");
4234 if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4235 DP_NOTICE(p_hwfn, true,
4236 "Coalescing configuration not enabled\n");
4240 p_coal_timeset = p_eth_qzone;
4241 OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4242 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4243 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4244 ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4246 return ECORE_SUCCESS;
4249 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4250 struct ecore_ptt *p_ptt,
4251 u16 coalesce, u16 qid, u16 sb_id)
4253 struct ustorm_eth_queue_zone eth_qzone;
4254 u8 timeset, timer_res;
4257 enum _ecore_status_t rc;
4259 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4260 if (coalesce <= 0x7F) {
4262 } else if (coalesce <= 0xFF) {
4264 } else if (coalesce <= 0x1FF) {
4267 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4270 timeset = (u8)(coalesce >> timer_res);
4272 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4273 if (rc != ECORE_SUCCESS)
4276 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
4277 if (rc != ECORE_SUCCESS)
4280 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4282 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4283 sizeof(struct ustorm_eth_queue_zone), timeset);
4284 if (rc != ECORE_SUCCESS)
4287 p_hwfn->p_dev->rx_coalesce_usecs = coalesce;
4292 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4293 struct ecore_ptt *p_ptt,
4294 u16 coalesce, u16 qid, u16 sb_id)
4296 struct xstorm_eth_queue_zone eth_qzone;
4297 u8 timeset, timer_res;
4300 enum _ecore_status_t rc;
4302 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4303 if (coalesce <= 0x7F) {
4305 } else if (coalesce <= 0xFF) {
4307 } else if (coalesce <= 0x1FF) {
4310 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4314 timeset = (u8)(coalesce >> timer_res);
4316 rc = ecore_fw_l2_queue(p_hwfn, qid, &fw_qid);
4317 if (rc != ECORE_SUCCESS)
4320 rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
4321 if (rc != ECORE_SUCCESS)
4324 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
4326 rc = ecore_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4327 sizeof(struct xstorm_eth_queue_zone), timeset);
4328 if (rc != ECORE_SUCCESS)
4331 p_hwfn->p_dev->tx_coalesce_usecs = coalesce;
4336 /* Calculate final WFQ values for all vports and configure it.
4337 * After this configuration each vport must have
4338 * approx min rate = vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4340 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4341 struct ecore_ptt *p_ptt,
4344 struct init_qm_vport_params *vport_params;
4347 vport_params = p_hwfn->qm_info.qm_vport_params;
4349 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4350 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4352 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4354 ecore_init_vport_wfq(p_hwfn, p_ptt,
4355 vport_params[i].first_tx_pq_id,
4356 vport_params[i].vport_wfq);
4361 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4365 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4366 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4369 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4370 struct ecore_ptt *p_ptt,
4373 struct init_qm_vport_params *vport_params;
4376 vport_params = p_hwfn->qm_info.qm_vport_params;
4378 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4379 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4380 ecore_init_vport_wfq(p_hwfn, p_ptt,
4381 vport_params[i].first_tx_pq_id,
4382 vport_params[i].vport_wfq);
4386 /* This function performs several validations for WFQ
4387 * configuration and required min rate for a given vport
4388 * 1. req_rate must be greater than one percent of min_pf_rate.
4389 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4390 * rates to get less than one percent of min_pf_rate.
4391 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4393 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4394 u16 vport_id, u32 req_rate,
4397 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4398 int non_requested_count = 0, req_count = 0, i, num_vports;
4400 num_vports = p_hwfn->qm_info.num_vports;
4402 /* Accounting for the vports which are configured for WFQ explicitly */
4404 for (i = 0; i < num_vports; i++) {
4407 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4409 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4410 total_req_min_rate += tmp_speed;
4414 /* Include current vport data as well */
4416 total_req_min_rate += req_rate;
4417 non_requested_count = num_vports - req_count;
4419 /* validate possible error cases */
4420 if (req_rate > min_pf_rate) {
4421 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4422 "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4423 vport_id, req_rate, min_pf_rate);
4427 if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4428 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4429 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4430 vport_id, req_rate, min_pf_rate);
4434 /* TBD - for number of vports greater than 100 */
4435 if (num_vports > ECORE_WFQ_UNIT) {
4436 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4437 "Number of vports is greater than %d\n",
4442 if (total_req_min_rate > min_pf_rate) {
4443 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4444 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4445 total_req_min_rate, min_pf_rate);
4449 /* Data left for non requested vports */
4450 total_left_rate = min_pf_rate - total_req_min_rate;
4451 left_rate_per_vp = total_left_rate / non_requested_count;
4453 /* validate if non requested get < 1% of min bw */
4454 if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4455 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4456 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4457 left_rate_per_vp, min_pf_rate);
4461 /* now req_rate for given vport passes all scenarios.
4462 * assign final wfq rates to all vports.
4464 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4465 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4467 for (i = 0; i < num_vports; i++) {
4468 if (p_hwfn->qm_info.wfq_data[i].configured)
4471 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4474 return ECORE_SUCCESS;
4477 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4478 struct ecore_ptt *p_ptt,
4479 u16 vp_id, u32 rate)
4481 struct ecore_mcp_link_state *p_link;
4482 int rc = ECORE_SUCCESS;
4484 p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4486 if (!p_link->min_pf_rate) {
4487 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4488 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4492 rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4494 if (rc == ECORE_SUCCESS)
4495 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4496 p_link->min_pf_rate);
4498 DP_NOTICE(p_hwfn, false,
4499 "Validation failed while configuring min rate\n");
4504 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4505 struct ecore_ptt *p_ptt,
4508 bool use_wfq = false;
4509 int rc = ECORE_SUCCESS;
4512 /* Validate all pre configured vports for wfq */
4513 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4516 if (!p_hwfn->qm_info.wfq_data[i].configured)
4519 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4522 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4523 if (rc != ECORE_SUCCESS) {
4524 DP_NOTICE(p_hwfn, false,
4525 "WFQ validation failed while configuring min rate\n");
4530 if (rc == ECORE_SUCCESS && use_wfq)
4531 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4533 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4538 /* Main API for ecore clients to configure vport min rate.
4539 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4540 * rate - Speed in Mbps needs to be assigned to a given vport.
4542 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4544 int i, rc = ECORE_INVAL;
4546 /* TBD - for multiple hardware functions - that is 100 gig */
4547 if (p_dev->num_hwfns > 1) {
4548 DP_NOTICE(p_dev, false,
4549 "WFQ configuration is not supported for this device\n");
4553 for_each_hwfn(p_dev, i) {
4554 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4555 struct ecore_ptt *p_ptt;
4557 p_ptt = ecore_ptt_acquire(p_hwfn);
4559 return ECORE_TIMEOUT;
4561 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4563 if (rc != ECORE_SUCCESS) {
4564 ecore_ptt_release(p_hwfn, p_ptt);
4568 ecore_ptt_release(p_hwfn, p_ptt);
4574 /* API to configure WFQ from mcp link change */
4575 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4580 /* TBD - for multiple hardware functions - that is 100 gig */
4581 if (p_dev->num_hwfns > 1) {
4582 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4583 "WFQ configuration is not supported for this device\n");
4587 for_each_hwfn(p_dev, i) {
4588 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4590 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4596 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4597 struct ecore_ptt *p_ptt,
4598 struct ecore_mcp_link_state *p_link,
4601 int rc = ECORE_SUCCESS;
4603 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4605 if (!p_link->line_speed && (max_bw != 100))
4608 p_link->speed = (p_link->line_speed * max_bw) / 100;
4609 p_hwfn->qm_info.pf_rl = p_link->speed;
4611 /* Since the limiter also affects Tx-switched traffic, we don't want it
4612 * to limit such traffic in case there's no actual limit.
4613 * In that case, set limit to imaginary high boundary.
4616 p_hwfn->qm_info.pf_rl = 100000;
4618 rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4619 p_hwfn->qm_info.pf_rl);
4621 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4622 "Configured MAX bandwidth to be %08x Mb/sec\n",
4628 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4629 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4631 int i, rc = ECORE_INVAL;
4633 if (max_bw < 1 || max_bw > 100) {
4634 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4638 for_each_hwfn(p_dev, i) {
4639 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4640 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4641 struct ecore_mcp_link_state *p_link;
4642 struct ecore_ptt *p_ptt;
4644 p_link = &p_lead->mcp_info->link_output;
4646 p_ptt = ecore_ptt_acquire(p_hwfn);
4648 return ECORE_TIMEOUT;
4650 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4653 ecore_ptt_release(p_hwfn, p_ptt);
4655 if (rc != ECORE_SUCCESS)
4662 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4663 struct ecore_ptt *p_ptt,
4664 struct ecore_mcp_link_state *p_link,
4667 int rc = ECORE_SUCCESS;
4669 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4670 p_hwfn->qm_info.pf_wfq = min_bw;
4672 if (!p_link->line_speed)
4675 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4677 rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4679 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4680 "Configured MIN bandwidth to be %d Mb/sec\n",
4681 p_link->min_pf_rate);
4686 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4687 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4689 int i, rc = ECORE_INVAL;
4691 if (min_bw < 1 || min_bw > 100) {
4692 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4696 for_each_hwfn(p_dev, i) {
4697 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4698 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4699 struct ecore_mcp_link_state *p_link;
4700 struct ecore_ptt *p_ptt;
4702 p_link = &p_lead->mcp_info->link_output;
4704 p_ptt = ecore_ptt_acquire(p_hwfn);
4706 return ECORE_TIMEOUT;
4708 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4710 if (rc != ECORE_SUCCESS) {
4711 ecore_ptt_release(p_hwfn, p_ptt);
4715 if (p_link->min_pf_rate) {
4716 u32 min_rate = p_link->min_pf_rate;
4718 rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4723 ecore_ptt_release(p_hwfn, p_ptt);
4729 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4731 struct ecore_mcp_link_state *p_link;
4733 p_link = &p_hwfn->mcp_info->link_output;
4735 if (p_link->min_pf_rate)
4736 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4737 p_link->min_pf_rate);
4739 OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4740 sizeof(*p_hwfn->qm_info.wfq_data) *
4741 p_hwfn->qm_info.num_vports);
4744 int ecore_device_num_engines(struct ecore_dev *p_dev)
4746 return ECORE_IS_BB(p_dev) ? 2 : 1;
4749 int ecore_device_num_ports(struct ecore_dev *p_dev)
4751 /* in CMT always only one port */
4752 if (p_dev->num_hwfns > 1)
4755 return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4758 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4763 ((u8 *)fw_msb)[0] = mac[1];
4764 ((u8 *)fw_msb)[1] = mac[0];
4765 ((u8 *)fw_mid)[0] = mac[3];
4766 ((u8 *)fw_mid)[1] = mac[2];
4767 ((u8 *)fw_lsb)[0] = mac[5];
4768 ((u8 *)fw_lsb)[1] = mac[4];