1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_HSI_COMMON__
8 #define __ECORE_HSI_COMMON__
9 /********************************/
10 /* Add include to common target */
11 /********************************/
12 #include "common_hsi.h"
16 * opcodes for the event ring
18 enum common_event_opcode {
19 COMMON_EVENT_PF_START,
21 COMMON_EVENT_VF_START,
23 COMMON_EVENT_VF_PF_CHANNEL,
25 COMMON_EVENT_PF_UPDATE,
26 COMMON_EVENT_MALICIOUS_VF,
27 COMMON_EVENT_RL_UPDATE,
29 MAX_COMMON_EVENT_OPCODE
34 * Common Ramrod Command IDs
36 enum common_ramrod_cmd_id {
38 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
39 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
40 COMMON_RAMROD_VF_START /* VF Function Start */,
41 COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */,
42 COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */,
43 COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */,
44 COMMON_RAMROD_EMPTY /* Empty Ramrod */,
45 MAX_COMMON_RAMROD_CMD_ID
50 * The core storm context for the Ystorm
52 struct ystorm_core_conn_st_ctx {
57 * The core storm context for the Pstorm
59 struct pstorm_core_conn_st_ctx {
64 * Core Slowpath Connection storm context of Xstorm
66 struct xstorm_core_conn_st_ctx {
67 __le32 spq_base_lo /* SPQ Ring Base Address low dword */;
68 __le32 spq_base_hi /* SPQ Ring Base Address high dword */;
69 /* Consolidation Ring Base Address */
70 struct regpair consolid_base_addr;
71 __le16 spq_cons /* SPQ Ring Consumer */;
72 __le16 consolid_cons /* Consolidation Ring Consumer */;
73 __le32 reserved0[55] /* Pad to 15 cycles */;
76 struct xstorm_core_conn_ag_ctx {
77 u8 reserved0 /* cdu_validation */;
80 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
81 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
82 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
83 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
84 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
85 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
86 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
87 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
88 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
89 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
91 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
94 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
98 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
99 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
100 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
101 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
102 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
103 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
104 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
105 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
106 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
107 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
108 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
109 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
110 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */
111 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
112 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */
113 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
115 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
116 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
117 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
118 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
119 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
120 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
122 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
123 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
125 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
126 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
127 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
128 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
129 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
130 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
131 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
132 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
134 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
135 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
136 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
137 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
138 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
139 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
140 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
141 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
143 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
144 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
145 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
146 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
147 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */
148 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
149 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
150 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
152 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */
153 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
154 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
155 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
156 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */
157 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
158 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */
159 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
161 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
162 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
163 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */
164 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
165 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
166 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
167 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
168 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
169 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
170 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
172 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
173 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
174 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
175 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
176 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
177 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
178 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
179 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
180 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
181 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
182 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
183 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
184 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
185 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
186 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
187 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
189 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
190 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
191 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
192 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
193 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
194 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
195 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
196 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
197 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
198 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
199 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
200 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
201 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */
202 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
204 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
205 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
207 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */
208 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
209 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */
210 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
211 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
212 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
213 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
214 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
215 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
216 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
217 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
218 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
219 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
220 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
221 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
222 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
224 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
225 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
226 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
227 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
228 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */
229 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
230 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
231 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
232 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
233 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
234 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
235 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
236 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
237 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
238 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */
239 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
241 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */
242 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
243 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
244 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
245 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
246 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
247 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
248 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
249 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
250 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
251 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
252 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
253 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
254 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
255 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
256 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
258 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */
259 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
260 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
261 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
265 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
266 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
267 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
268 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
269 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
270 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
271 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
272 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
273 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
275 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
276 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
277 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
278 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
279 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
280 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
281 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
282 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
283 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
284 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
285 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
286 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
287 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
288 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
289 u8 byte2 /* byte2 */;
290 __le16 physical_q0 /* physical_q0 */;
291 __le16 consolid_prod /* physical_q1 */;
292 __le16 reserved16 /* physical_q2 */;
293 __le16 tx_bd_cons /* word3 */;
294 __le16 tx_bd_or_spq_prod /* word4 */;
295 __le16 updated_qm_pq_id /* word5 */;
296 __le16 conn_dpi /* conn_dpi */;
297 u8 byte3 /* byte3 */;
298 u8 byte4 /* byte4 */;
299 u8 byte5 /* byte5 */;
300 u8 byte6 /* byte6 */;
301 __le32 reg0 /* reg0 */;
302 __le32 reg1 /* reg1 */;
303 __le32 reg2 /* reg2 */;
304 __le32 reg3 /* reg3 */;
305 __le32 reg4 /* reg4 */;
306 __le32 reg5 /* cf_array0 */;
307 __le32 reg6 /* cf_array1 */;
308 __le16 word7 /* word7 */;
309 __le16 word8 /* word8 */;
310 __le16 word9 /* word9 */;
311 __le16 word10 /* word10 */;
312 __le32 reg7 /* reg7 */;
313 __le32 reg8 /* reg8 */;
314 __le32 reg9 /* reg9 */;
315 u8 byte7 /* byte7 */;
316 u8 byte8 /* byte8 */;
317 u8 byte9 /* byte9 */;
318 u8 byte10 /* byte10 */;
319 u8 byte11 /* byte11 */;
320 u8 byte12 /* byte12 */;
321 u8 byte13 /* byte13 */;
322 u8 byte14 /* byte14 */;
323 u8 byte15 /* byte15 */;
324 u8 e5_reserved /* e5_reserved */;
325 __le16 word11 /* word11 */;
326 __le32 reg10 /* reg10 */;
327 __le32 reg11 /* reg11 */;
328 __le32 reg12 /* reg12 */;
329 __le32 reg13 /* reg13 */;
330 __le32 reg14 /* reg14 */;
331 __le32 reg15 /* reg15 */;
332 __le32 reg16 /* reg16 */;
333 __le32 reg17 /* reg17 */;
334 __le32 reg18 /* reg18 */;
335 __le32 reg19 /* reg19 */;
336 __le16 word12 /* word12 */;
337 __le16 word13 /* word13 */;
338 __le16 word14 /* word14 */;
339 __le16 word15 /* word15 */;
342 struct tstorm_core_conn_ag_ctx {
343 u8 byte0 /* cdu_validation */;
344 u8 byte1 /* state */;
346 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
347 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
348 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
349 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
350 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
351 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
352 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
353 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
354 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
355 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
356 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
357 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
358 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
359 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
361 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
362 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
363 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
364 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
365 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
366 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
367 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
368 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
370 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
371 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
372 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
373 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
374 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
375 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
376 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
377 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
379 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
380 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
381 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
382 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
383 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
384 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
385 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
386 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
387 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
388 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
389 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
390 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
392 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
393 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
394 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
395 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
396 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
397 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
398 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
399 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
400 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
401 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
402 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
403 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
404 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
405 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
406 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
407 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
409 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
410 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
411 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
412 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
413 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
414 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
415 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
416 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
417 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
418 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
419 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
420 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
421 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
422 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
423 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
424 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
425 __le32 reg0 /* reg0 */;
426 __le32 reg1 /* reg1 */;
427 __le32 reg2 /* reg2 */;
428 __le32 reg3 /* reg3 */;
429 __le32 reg4 /* reg4 */;
430 __le32 reg5 /* reg5 */;
431 __le32 reg6 /* reg6 */;
432 __le32 reg7 /* reg7 */;
433 __le32 reg8 /* reg8 */;
434 u8 byte2 /* byte2 */;
435 u8 byte3 /* byte3 */;
436 __le16 word0 /* word0 */;
437 u8 byte4 /* byte4 */;
438 u8 byte5 /* byte5 */;
439 __le16 word1 /* word1 */;
440 __le16 word2 /* conn_dpi */;
441 __le16 word3 /* word3 */;
442 __le32 reg9 /* reg9 */;
443 __le32 reg10 /* reg10 */;
446 struct ustorm_core_conn_ag_ctx {
447 u8 reserved /* cdu_validation */;
448 u8 byte1 /* state */;
450 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
451 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
452 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
453 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
454 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
455 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
456 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
457 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
458 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
459 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
461 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
462 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
463 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
464 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
465 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
466 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
467 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
468 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
470 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
471 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
472 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
473 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
474 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
475 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
476 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
477 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
478 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
479 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
480 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
481 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
482 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
483 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
484 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
485 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
487 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
488 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
489 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
490 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
491 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
492 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
493 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
494 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
495 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
496 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
497 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
498 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
499 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
500 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
501 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
502 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
503 u8 byte2 /* byte2 */;
504 u8 byte3 /* byte3 */;
505 __le16 word0 /* conn_dpi */;
506 __le16 word1 /* word1 */;
507 __le32 rx_producers /* reg0 */;
508 __le32 reg1 /* reg1 */;
509 __le32 reg2 /* reg2 */;
510 __le32 reg3 /* reg3 */;
511 __le16 word2 /* word2 */;
512 __le16 word3 /* word3 */;
516 * The core storm context for the Mstorm
518 struct mstorm_core_conn_st_ctx {
523 * The core storm context for the Ustorm
525 struct ustorm_core_conn_st_ctx {
530 * The core storm context for the Tstorm
532 struct tstorm_core_conn_st_ctx {
537 * core connection context
539 struct core_conn_context {
540 /* ystorm storm context */
541 struct ystorm_core_conn_st_ctx ystorm_st_context;
542 struct regpair ystorm_st_padding[2] /* padding */;
543 /* pstorm storm context */
544 struct pstorm_core_conn_st_ctx pstorm_st_context;
545 struct regpair pstorm_st_padding[2] /* padding */;
546 /* xstorm storm context */
547 struct xstorm_core_conn_st_ctx xstorm_st_context;
548 /* xstorm aggregative context */
549 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
550 /* tstorm aggregative context */
551 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
552 /* ustorm aggregative context */
553 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
554 /* mstorm storm context */
555 struct mstorm_core_conn_st_ctx mstorm_st_context;
556 /* ustorm storm context */
557 struct ustorm_core_conn_st_ctx ustorm_st_context;
558 struct regpair ustorm_st_padding[2] /* padding */;
559 /* tstorm storm context */
560 struct tstorm_core_conn_st_ctx tstorm_st_context;
561 struct regpair tstorm_st_padding[2] /* padding */;
566 * How ll2 should deal with packet upon errors
568 enum core_error_handle {
569 LL2_DROP_PACKET /* If error occurs drop packet */,
570 LL2_DO_NOTHING /* If error occurs do nothing */,
571 LL2_ASSERT /* If error occurs assert */,
572 MAX_CORE_ERROR_HANDLE
577 * opcodes for the event ring
579 enum core_event_opcode {
580 CORE_EVENT_TX_QUEUE_START,
581 CORE_EVENT_TX_QUEUE_STOP,
582 CORE_EVENT_RX_QUEUE_START,
583 CORE_EVENT_RX_QUEUE_STOP,
584 CORE_EVENT_RX_QUEUE_FLUSH,
585 CORE_EVENT_TX_QUEUE_UPDATE,
586 CORE_EVENT_QUEUE_STATS_QUERY,
587 MAX_CORE_EVENT_OPCODE
592 * The L4 pseudo checksum mode for Core
594 enum core_l4_pseudo_checksum_mode {
595 /* Pseudo Checksum on packet is calculated with the correct packet length. */
596 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
597 /* Pseudo Checksum on packet is calculated with zero length. */
598 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
599 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
604 * Light-L2 RX Producers in Tstorm RAM
606 struct core_ll2_port_stats {
607 struct regpair gsi_invalid_hdr;
608 struct regpair gsi_invalid_pkt_length;
609 struct regpair gsi_unsupported_pkt_typ;
610 struct regpair gsi_crcchksm_error;
615 * LL2 TX Per Queue Stats
617 struct core_ll2_pstorm_per_queue_stat {
618 /* number of total bytes sent without errors */
619 struct regpair sent_ucast_bytes;
620 /* number of total bytes sent without errors */
621 struct regpair sent_mcast_bytes;
622 /* number of total bytes sent without errors */
623 struct regpair sent_bcast_bytes;
624 /* number of total packets sent without errors */
625 struct regpair sent_ucast_pkts;
626 /* number of total packets sent without errors */
627 struct regpair sent_mcast_pkts;
628 /* number of total packets sent without errors */
629 struct regpair sent_bcast_pkts;
630 /* number of total packets dropped due to errors */
631 struct regpair error_drop_pkts;
635 struct core_ll2_tstorm_per_queue_stat {
636 /* Number of packets discarded because they are bigger than MTU */
637 struct regpair packet_too_big_discard;
638 /* Number of packets discarded due to lack of host buffers */
639 struct regpair no_buff_discard;
642 struct core_ll2_ustorm_per_queue_stat {
643 struct regpair rcv_ucast_bytes;
644 struct regpair rcv_mcast_bytes;
645 struct regpair rcv_bcast_bytes;
646 struct regpair rcv_ucast_pkts;
647 struct regpair rcv_mcast_pkts;
648 struct regpair rcv_bcast_pkts;
653 * Light-L2 RX Producers
655 struct core_ll2_rx_prod {
656 __le16 bd_prod /* BD Producer */;
657 __le16 cqe_prod /* CQE Producer */;
662 struct core_ll2_tx_per_queue_stat {
663 /* PSTORM per queue statistics */
664 struct core_ll2_pstorm_per_queue_stat pstorm_stat;
670 * Structure for doorbell data, in PWM mode, for RX producers update.
672 struct core_pwm_prod_update_data {
673 __le16 icid /* internal CID */;
676 /* aggregative command. Set DB_AGG_CMD_SET for producer update
677 * (use enum db_agg_cmd_sel)
679 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
680 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
681 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0. */
682 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
683 struct core_ll2_rx_prod prod /* Producers. */;
688 * Ramrod data for rx/tx queue statistics query ramrod
690 struct core_queue_stats_query_ramrod_data {
691 u8 rx_stat /* If set, collect RX queue statistics. */;
692 u8 tx_stat /* If set, collect TX queue statistics. */;
694 /* Address of RX statistic buffer. core_ll2_rx_per_queue_stat struct will be
695 * write to this address.
697 struct regpair rx_stat_addr;
698 /* Address of TX statistic buffer. core_ll2_tx_per_queue_stat struct will be
699 * write to this address.
701 struct regpair tx_stat_addr;
706 * Core Ramrod Command IDs (light L2)
708 enum core_ramrod_cmd_id {
710 CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
711 CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
712 CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
713 CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
714 CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */,
715 CORE_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */,
716 CORE_RAMROD_QUEUE_STATS_QUERY /* Queue Statist Query Ramrod */,
717 MAX_CORE_RAMROD_CMD_ID
722 * Core RX CQE Type for Light L2
724 enum core_roce_flavor_type {
727 MAX_CORE_ROCE_FLAVOR_TYPE
732 * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff
734 struct core_rx_action_on_error {
736 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */
737 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
738 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
739 /* ll2 how to handle error with no_buff (use enum core_error_handle) */
740 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
741 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
742 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
743 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
748 * Core RX BD for Light L2
757 * Core RX CM offload BD for Light L2
759 struct core_rx_bd_with_buff_len {
766 * Core RX CM offload BD for Light L2
768 union core_rx_bd_union {
769 struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */;
770 /* Core Rx Bd with dynamic buffer length */
771 struct core_rx_bd_with_buff_len rx_bd_with_len;
777 * Opaque Data for Light L2 RX CQE .
779 struct core_rx_cqe_opaque_data {
780 __le32 data[2] /* Opaque CQE Data */;
785 * Core RX CQE Type for Light L2
787 enum core_rx_cqe_type {
788 CORE_RX_CQE_ILLIGAL_TYPE /* Bad RX Cqe type */,
789 CORE_RX_CQE_TYPE_REGULAR /* Regular Core RX CQE */,
790 CORE_RX_CQE_TYPE_GSI_OFFLOAD /* Fp Gsi offload RX CQE */,
791 CORE_RX_CQE_TYPE_SLOW_PATH /* Slow path Core RX CQE */,
797 * Core RX CQE for Light L2 .
799 struct core_rx_fast_path_cqe {
800 u8 type /* CQE type */;
801 /* Offset (in bytes) of the packet from start of the buffer */
803 /* Parsing and error flags from the parser */
804 struct parsing_and_err_flags parse_flags;
805 __le16 packet_length /* Total packet length (from the parser) */;
806 __le16 vlan /* 802.1q VLAN tag */;
807 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
808 /* bit- map: each bit represents a specific error. errors indications are
809 * provided by the cracker. see spec for detailed description
811 struct parsing_err_flags err_flags;
817 * Core Rx CM offload CQE .
819 struct core_rx_gsi_offload_cqe {
820 u8 type /* CQE type */;
821 u8 data_length_error /* set if gsi data is bigger than buff */;
822 /* Parsing and error flags from the parser */
823 struct parsing_and_err_flags parse_flags;
824 __le16 data_length /* Total packet length (from the parser) */;
825 __le16 vlan /* 802.1q VLAN tag */;
826 __le32 src_mac_addrhi /* hi 4 bytes source mac address */;
827 __le16 src_mac_addrlo /* lo 2 bytes of source mac address */;
828 /* These are the lower 16 bit of QP id in RoCE BTH header */
830 __le32 src_qp /* Source QP from DETH header */;
831 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
836 * Core RX CQE for Light L2 .
838 struct core_rx_slow_path_cqe {
839 u8 type /* CQE type */;
842 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */;
847 * Core RX CM offload BD for Light L2
849 union core_rx_cqe_union {
850 struct core_rx_fast_path_cqe rx_cqe_fp /* Fast path CQE */;
851 struct core_rx_gsi_offload_cqe rx_cqe_gsi /* GSI offload CQE */;
852 struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */;
860 * Ramrod data for rx queue start ramrod
862 struct core_rx_start_ramrod_data {
863 struct regpair bd_base /* Address of the first BD page */;
864 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
865 __le16 mtu /* MTU */;
866 __le16 sb_id /* Status block ID */;
867 u8 sb_index /* Status block index */;
868 u8 complete_cqe_flg /* if set - post completion to the CQE ring */;
869 u8 complete_event_flg /* if set - post completion to the event ring */;
870 u8 drop_ttl0_flg /* if set - drop packet with ttl=0 */;
871 __le16 num_of_pbl_pages /* Number of pages in CQE PBL */;
872 /* if set - 802.1q tag will be removed and copied to CQE */
873 u8 inner_vlan_stripping_en;
874 /* if set - outer tag wont be stripped, valid only in MF OVLAN mode. */
875 u8 outer_vlan_stripping_dis;
876 u8 queue_id /* Light L2 RX Queue ID */;
877 u8 main_func_queue /* Set if this is the main PFs LL2 queue */;
878 /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if
879 * main_func_queue is set.
881 u8 mf_si_bcast_accept_all;
882 /* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if
883 * main_func_queue is set.
885 u8 mf_si_mcast_accept_all;
886 /* If set, the inner vlan (802.1q tag) priority that is written to cqe will be
887 * zero out, used for TenantDcb
889 /* Specifies how ll2 should deal with RX packets errors */
890 struct core_rx_action_on_error action_on_error;
891 u8 gsi_offload_flag /* set for GSI offload mode */;
892 /* If set, queue is subject for RX VFC classification. */
894 u8 vport_id /* Queue VPORT for RX VFC classification. */;
895 u8 zero_prod_flg /* If set, zero RX producers. */;
896 /* If set, the inner vlan (802.1q tag) priority that is written to cqe will be
897 * zero out, used for TenantDcb
899 u8 wipe_inner_vlan_pri_en;
905 * Ramrod data for rx queue stop ramrod
907 struct core_rx_stop_ramrod_data {
908 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
909 u8 complete_event_flg /* post completion to the event ring if set */;
910 u8 queue_id /* Light L2 RX Queue ID */;
917 * Flags for Core TX BD
919 struct core_tx_bd_data {
921 /* Do not allow additional VLAN manipulations on this packet (DCB) */
922 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
923 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
924 /* Insert VLAN into packet. Cannot be set for LB packets
925 * (tx_dst == CORE_TX_DEST_LB)
927 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
928 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
929 /* This is the first BD of the packet (for debug) */
930 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
931 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
932 /* Calculate the IP checksum for the packet */
933 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
934 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
935 /* Calculate the L4 checksum for the packet */
936 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
937 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
938 /* Packet is IPv6 with extensions */
939 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
940 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
941 /* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol:
944 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
945 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
946 /* The pseudo checksum mode to place in the L4 checksum field. Required only
947 * when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode)
949 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
950 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
951 /* Number of BDs that make up one packet - width wide enough to present
952 * CORE_LL2_TX_MAX_BDS_PER_PACKET
954 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
955 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
956 /* Use roce_flavor enum - Differentiate between Roce flavors is valid when
957 * connType is ROCE (use enum core_roce_flavor_type)
959 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
960 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
961 /* Calculate ip length */
962 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
963 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
964 /* disables the STAG insertion, relevant only in MF OVLAN mode. */
965 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
966 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
967 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
968 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
972 * Core TX BD for Light L2
975 struct regpair addr /* Buffer Address */;
976 __le16 nbytes /* Number of Bytes in Buffer */;
977 /* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack
978 * packets: echo data to pass to Rx
980 __le16 nw_vlan_or_lb_echo;
981 struct core_tx_bd_data bd_data /* BD Flags */;
983 /* L4 Header Offset from start of packet (in Words). This is needed if both
984 * l4_csum and ipv6_ext are set
986 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
987 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
988 /* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */
989 #define CORE_TX_BD_TX_DST_MASK 0x3
990 #define CORE_TX_BD_TX_DST_SHIFT 14
996 * Light L2 TX Destination
999 CORE_TX_DEST_NW /* TX Destination to the Network */,
1000 CORE_TX_DEST_LB /* TX Destination to the Loopback */,
1001 CORE_TX_DEST_RESERVED,
1002 CORE_TX_DEST_DROP /* TX Drop */,
1008 * Ramrod data for tx queue start ramrod
1010 struct core_tx_start_ramrod_data {
1011 struct regpair pbl_base_addr /* Address of the pbl page */;
1012 __le16 mtu /* Maximum transmission unit */;
1013 __le16 sb_id /* Status block ID */;
1014 u8 sb_index /* Status block protocol index */;
1015 u8 stats_en /* Statistics Enable */;
1016 u8 stats_id /* Statistics Counter ID */;
1017 u8 conn_type /* connection type that loaded ll2 */;
1018 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1019 __le16 qm_pq_id /* QM PQ ID */;
1020 u8 gsi_offload_flag /* set for GSI offload mode */;
1021 u8 ctx_stats_en /* Context statistics enable */;
1022 /* If set, queue is part of VPORT and subject for TX switching. */
1024 /* vport id of the current connection, used to access non_rdma_in_to_in_pri_map
1025 * which is per vport
1032 * Ramrod data for tx queue stop ramrod
1034 struct core_tx_stop_ramrod_data {
1035 __le32 reserved0[2];
1040 * Ramrod data for tx queue update ramrod
1042 struct core_tx_update_ramrod_data {
1043 u8 update_qm_pq_id_flg /* Flag to Update QM PQ ID */;
1045 __le16 qm_pq_id /* Updated QM PQ ID */;
1046 __le32 reserved1[1];
1051 * Enum flag for what type of dcb data to update
1053 enum dcb_dscp_update_mode {
1054 /* use when no change should be done to DCB data */
1055 DONT_UPDATE_DCB_DSCP,
1056 UPDATE_DCB /* use to update only L2 (vlan) priority */,
1057 UPDATE_DSCP /* use to update only IP DSCP */,
1058 UPDATE_DCB_DSCP /* update vlan pri and DSCP */,
1059 MAX_DCB_DSCP_UPDATE_FLAG
1063 struct eth_mstorm_per_pf_stat {
1064 struct regpair gre_discard_pkts /* Dropped GRE RX packets */;
1065 struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */;
1066 struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */;
1067 struct regpair lb_discard_pkts /* Dropped Tx switched packets */;
1071 struct eth_mstorm_per_queue_stat {
1072 /* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (IPv6) */
1073 struct regpair ttl0_discard;
1074 /* Number of packets discarded because they are bigger than MTU */
1075 struct regpair packet_too_big_discard;
1076 /* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */
1077 struct regpair no_buff_discard;
1078 /* Number of packets discarded because of no active Rx connection */
1079 struct regpair not_active_discard;
1080 /* number of coalesced packets in all TPA aggregations */
1081 struct regpair tpa_coalesced_pkts;
1082 /* total number of TPA aggregations */
1083 struct regpair tpa_coalesced_events;
1084 /* number of aggregations, which abnormally ended */
1085 struct regpair tpa_aborts_num;
1086 /* total TCP payload length in all TPA aggregations */
1087 struct regpair tpa_coalesced_bytes;
1092 * Ethernet TX Per PF
1094 struct eth_pstorm_per_pf_stat {
1095 /* number of total ucast bytes sent on loopback port without errors */
1096 struct regpair sent_lb_ucast_bytes;
1097 /* number of total mcast bytes sent on loopback port without errors */
1098 struct regpair sent_lb_mcast_bytes;
1099 /* number of total bcast bytes sent on loopback port without errors */
1100 struct regpair sent_lb_bcast_bytes;
1101 /* number of total ucast packets sent on loopback port without errors */
1102 struct regpair sent_lb_ucast_pkts;
1103 /* number of total mcast packets sent on loopback port without errors */
1104 struct regpair sent_lb_mcast_pkts;
1105 /* number of total bcast packets sent on loopback port without errors */
1106 struct regpair sent_lb_bcast_pkts;
1107 struct regpair sent_gre_bytes /* Sent GRE bytes */;
1108 struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */;
1109 struct regpair sent_geneve_bytes /* Sent GENEVE bytes */;
1110 struct regpair sent_mpls_bytes /* Sent MPLS bytes */;
1111 struct regpair sent_gre_mpls_bytes /* Sent GRE MPLS bytes (E5 Only) */;
1112 struct regpair sent_udp_mpls_bytes /* Sent GRE MPLS bytes (E5 Only) */;
1113 struct regpair sent_gre_pkts /* Sent GRE packets (E5 Only) */;
1114 struct regpair sent_vxlan_pkts /* Sent VXLAN packets */;
1115 struct regpair sent_geneve_pkts /* Sent GENEVE packets */;
1116 struct regpair sent_mpls_pkts /* Sent MPLS packets (E5 Only) */;
1117 struct regpair sent_gre_mpls_pkts /* Sent GRE MPLS packets (E5 Only) */;
1118 struct regpair sent_udp_mpls_pkts /* Sent UDP MPLS packets (E5 Only) */;
1119 struct regpair gre_drop_pkts /* Dropped GRE TX packets */;
1120 struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */;
1121 struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */;
1122 struct regpair mpls_drop_pkts /* Dropped MPLS TX packets (E5 Only) */;
1123 /* Dropped GRE MPLS TX packets (E5 Only) */
1124 struct regpair gre_mpls_drop_pkts;
1125 /* Dropped UDP MPLS TX packets (E5 Only) */
1126 struct regpair udp_mpls_drop_pkts;
1131 * Ethernet TX Per Queue Stats
1133 struct eth_pstorm_per_queue_stat {
1134 /* number of total bytes sent without errors */
1135 struct regpair sent_ucast_bytes;
1136 /* number of total bytes sent without errors */
1137 struct regpair sent_mcast_bytes;
1138 /* number of total bytes sent without errors */
1139 struct regpair sent_bcast_bytes;
1140 /* number of total packets sent without errors */
1141 struct regpair sent_ucast_pkts;
1142 /* number of total packets sent without errors */
1143 struct regpair sent_mcast_pkts;
1144 /* number of total packets sent without errors */
1145 struct regpair sent_bcast_pkts;
1146 /* number of total packets dropped due to errors */
1147 struct regpair error_drop_pkts;
1152 * ETH Rx producers data
1154 struct eth_rx_rate_limit {
1155 /* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) */
1157 /* Constant term to add (or subtract from number of cycles) */
1159 u8 add_sub_cnst /* Add (1) or subtract (0) constant term */;
1165 /* Update RSS indirection table entry command. One outstanding command supported
1168 struct eth_tstorm_rss_update_data {
1169 /* Valid flag. Driver must set this flag, FW clear valid flag when ready for new
1170 * RSS update command.
1173 /* Global VPORT ID. If RSS is disable for VPORT, RSS update command will be
1177 u8 ind_table_index /* RSS indirect table index that will be updated. */;
1179 __le16 ind_table_value /* RSS indirect table new value. */;
1180 __le16 reserved1 /* reserved. */;
1184 struct eth_ustorm_per_pf_stat {
1185 /* number of total ucast bytes received on loopback port without errors */
1186 struct regpair rcv_lb_ucast_bytes;
1187 /* number of total mcast bytes received on loopback port without errors */
1188 struct regpair rcv_lb_mcast_bytes;
1189 /* number of total bcast bytes received on loopback port without errors */
1190 struct regpair rcv_lb_bcast_bytes;
1191 /* number of total ucast packets received on loopback port without errors */
1192 struct regpair rcv_lb_ucast_pkts;
1193 /* number of total mcast packets received on loopback port without errors */
1194 struct regpair rcv_lb_mcast_pkts;
1195 /* number of total bcast packets received on loopback port without errors */
1196 struct regpair rcv_lb_bcast_pkts;
1197 struct regpair rcv_gre_bytes /* Received GRE bytes */;
1198 struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */;
1199 struct regpair rcv_geneve_bytes /* Received GENEVE bytes */;
1200 struct regpair rcv_gre_pkts /* Received GRE packets */;
1201 struct regpair rcv_vxlan_pkts /* Received VXLAN packets */;
1202 struct regpair rcv_geneve_pkts /* Received GENEVE packets */;
1206 struct eth_ustorm_per_queue_stat {
1207 struct regpair rcv_ucast_bytes;
1208 struct regpair rcv_mcast_bytes;
1209 struct regpair rcv_bcast_bytes;
1210 struct regpair rcv_ucast_pkts;
1211 struct regpair rcv_mcast_pkts;
1212 struct regpair rcv_bcast_pkts;
1217 * Event Ring VF-PF Channel data
1219 struct vf_pf_channel_eqe_data {
1220 struct regpair msg_addr /* VF-PF message address */;
1224 * Event Ring malicious VF data
1226 struct malicious_vf_eqe_data {
1227 u8 vf_id /* Malicious VF ID */;
1228 u8 err_id /* Malicious VF error (use enum malicious_vf_error_id) */;
1233 * Event Ring initial cleanup data
1235 struct initial_cleanup_eqe_data {
1236 u8 vf_id /* VF ID */;
1243 union event_ring_data {
1244 u8 bytes[8] /* Byte Array */;
1245 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
1246 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
1247 /* Dedicated fields to iscsi connect done results */
1248 struct iscsi_connect_done_results iscsi_conn_done_info;
1249 union rdma_eqe_data rdma_data /* Dedicated field for RDMA data */;
1250 struct nvmf_eqe_data nvmf_data /* Dedicated field for NVMf data */;
1251 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
1252 /* VF Initial Cleanup data */
1253 struct initial_cleanup_eqe_data vf_init_cleanup;
1260 struct event_ring_entry {
1261 u8 protocol_id /* Event Protocol ID (use enum protocol_type) */;
1262 u8 opcode /* Event Opcode (Per Protocol Type) */;
1263 u8 reserved0 /* Reserved */;
1264 u8 vfId /* vfId for this event, 0xFF if this is a PF event */;
1265 __le16 echo /* Echo value from ramrod data on the host */;
1266 /* FW return code for SP ramrods. Use (according to protocol) eth_return_code,
1267 * or rdma_fw_return_code, or fcoe_completion_status
1271 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
1272 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1273 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1274 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1275 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
1276 union event_ring_data data;
1280 * Event Ring Next Page Address
1282 struct event_ring_next_addr {
1283 struct regpair addr /* Next Page Address */;
1284 __le32 reserved[2] /* Reserved */;
1288 * Event Ring Element
1290 union event_ring_element {
1291 struct event_ring_entry entry /* Event Ring Entry */;
1292 /* Event Ring Next Page Address */
1293 struct event_ring_next_addr next_addr;
1301 enum fw_flow_ctrl_mode {
1304 MAX_FW_FLOW_CTRL_MODE
1311 enum gft_profile_type {
1312 /* tunnel type, inner 4 tuple, IP type and L4 type match. */
1313 GFT_PROFILE_TYPE_4_TUPLE,
1314 /* tunnel type, inner L4 destination port, IP type and L4 type match. */
1315 GFT_PROFILE_TYPE_L4_DST_PORT,
1316 /* tunnel type, inner IP destination address and IP type match. */
1317 GFT_PROFILE_TYPE_IP_DST_ADDR,
1318 /* tunnel type, inner IP source address and IP type match. */
1319 GFT_PROFILE_TYPE_IP_SRC_ADDR,
1320 GFT_PROFILE_TYPE_TUNNEL_TYPE /* tunnel type and outer IP type match. */,
1321 MAX_GFT_PROFILE_TYPE
1326 * Major and Minor hsi Versions
1328 struct hsi_fp_ver_struct {
1329 u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */;
1330 u8 major_ver_arr[2] /* Major Version of driver loading pf */;
1338 INTEG_PHASE_BB_A0_LATEST = 3 /* BB A0 latest integration phase */,
1339 INTEG_PHASE_BB_B0_NO_MCP = 10 /* BB B0 without MCP */,
1340 INTEG_PHASE_BB_B0_WITH_MCP = 11 /* BB B0 with MCP */,
1348 enum iwarp_ll2_tx_queues {
1349 /* LL2 queue for OOO packets sent in-order by the driver */
1350 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1351 /* LL2 queue for unaligned packets sent aligned by the driver */
1352 IWARP_LL2_ALIGNED_TX_QUEUE,
1353 /* LL2 queue for unaligned packets sent aligned and was right-trimmed by the
1356 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1357 IWARP_LL2_ERROR /* Error indication */,
1358 MAX_IWARP_LL2_TX_QUEUES
1363 * Malicious VF error ID
1365 enum malicious_vf_error_id {
1366 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */,
1367 /* Writing to VF/PF channel when it is not ready */
1368 VF_PF_CHANNEL_NOT_READY,
1369 VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */,
1370 VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */,
1371 /* TX packet is shorter then reported on BDs or from minimal size */
1372 ETH_PACKET_TOO_SMALL,
1373 /* Tx packet with marked as insert VLAN when its illegal */
1374 ETH_ILLEGAL_VLAN_MODE,
1375 ETH_MTU_VIOLATION /* TX packet is greater then MTU */,
1376 /* TX packet has illegal inband tags marked */
1377 ETH_ILLEGAL_INBAND_TAGS,
1378 /* Vlan cant be added to inband tag */
1379 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1380 /* indicated number of BDs for the packet is illegal */
1382 ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */,
1383 /* There are not enough BDs for transmission of even one packet */
1384 ETH_INSUFFICIENT_BDS,
1385 ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */,
1386 ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */,
1387 /* empty BD (which not contains control flags) is illegal */
1389 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit */,
1390 /* In LSO its expected that on the local BD ring there will be at least MSS
1393 ETH_INSUFFICIENT_PAYLOAD,
1394 ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */,
1395 /* Tunneled packet with IPv6+Ext without a proper number of BDs */
1396 ETH_TUNN_IPV6_EXT_NBD_ERR,
1397 ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */,
1398 ETH_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */,
1399 /* packet scanned is too large (can be 9700 at most) */
1400 ETH_PACKET_SIZE_TOO_LARGE,
1401 /* Tx packet with marked as insert VLAN when its illegal */
1402 CORE_ILLEGAL_VLAN_MODE,
1403 /* indicated number of BDs for the packet is illegal */
1405 CORE_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */,
1406 /* There are not enough BDs for transmission of even one packet */
1407 CORE_INSUFFICIENT_BDS,
1408 /* TX packet is shorter then reported on BDs or from minimal size */
1409 CORE_PACKET_TOO_SMALL,
1410 CORE_ILLEGAL_INBAND_TAGS /* TX packet has illegal inband tags marked */,
1411 CORE_VLAN_INSERT_AND_INBAND_VLAN /* Vlan cant be added to inband tag */,
1412 CORE_MTU_VIOLATION /* TX packet is greater then MTU */,
1413 CORE_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */,
1414 CORE_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */,
1415 MAX_MALICIOUS_VF_ERROR_ID
1421 * Mstorm non-triggering VF zone
1423 struct mstorm_non_trigger_vf_zone {
1424 /* VF statistic bucket */
1425 struct eth_mstorm_per_queue_stat eth_queue_stat;
1426 /* VF RX queues producers */
1427 struct eth_rx_prod_data
1428 eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1435 struct mstorm_vf_zone {
1436 /* non-interrupt-triggering zone */
1437 struct mstorm_non_trigger_vf_zone non_trigger;
1442 * vlan header including TPID and TCI fields
1444 struct vlan_header {
1445 __le16 tpid /* Tag Protocol Identifier */;
1446 __le16 tci /* Tag Control Information */;
1450 * outer tag configurations
1452 struct outer_tag_config_struct {
1453 /* Enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette
1454 * Davis, UFP with Host Control mode, and UFP with DCB over base interface.
1457 u8 enable_stag_pri_change;
1458 /* If inner_to_outer_pri_map is initialize then set pri_map_valid */
1461 /* In case mf_mode is MF_OVLAN, this field specifies the outer tag protocol
1462 * identifier and outer tag control information
1464 struct vlan_header outer_tag;
1465 /* Map from inner to outer priority. Set pri_map_valid when init map */
1466 u8 inner_to_outer_pri_map[8];
1471 * personality per PF
1473 enum personality_type {
1474 BAD_PERSONALITY_TYP,
1475 PERSONALITY_ISCSI /* iSCSI and LL2 */,
1476 PERSONALITY_FCOE /* Fcoe and LL2 */,
1477 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp, Eth and LL2 */,
1478 PERSONALITY_RDMA /* Roce and LL2 */,
1479 PERSONALITY_CORE /* CORE(LL2) */,
1480 PERSONALITY_ETH /* Ethernet */,
1481 PERSONALITY_TOE /* Toe and LL2 */,
1482 MAX_PERSONALITY_TYPE
1487 * tunnel configuration
1489 struct pf_start_tunnel_config {
1490 /* Set VXLAN tunnel UDP destination port to vxlan_udp_port. If not set -
1491 * FW will use a default port
1493 u8 set_vxlan_udp_port_flg;
1494 /* Set GENEVE tunnel UDP destination port to geneve_udp_port. If not set -
1495 * FW will use a default port
1497 u8 set_geneve_udp_port_flg;
1498 /* Set no-innet-L2 VXLAN tunnel UDP destination port to
1499 * no_inner_l2_vxlan_udp_port. If not set - FW will use a default port
1501 u8 set_no_inner_l2_vxlan_udp_port_flg;
1502 u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */;
1503 /* Rx classification scheme for l2 GENEVE tunnel. */
1504 u8 tunnel_clss_l2geneve;
1505 /* Rx classification scheme for ip GENEVE tunnel. */
1506 u8 tunnel_clss_ipgeneve;
1507 u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */;
1508 u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */;
1509 /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */
1510 __le16 vxlan_udp_port;
1511 /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */
1512 __le16 geneve_udp_port;
1513 /* no-innet-L2 VXLAN tunnel UDP destination port. Valid if
1514 * set_no_inner_l2_vxlan_udp_port_flg=1
1516 __le16 no_inner_l2_vxlan_udp_port;
1521 * Ramrod data for PF start ramrod
1523 struct pf_start_ramrod_data {
1524 struct regpair event_ring_pbl_addr /* Address of event ring PBL */;
1525 /* PBL address of consolidation queue */
1526 struct regpair consolid_q_pbl_addr;
1527 /* tunnel configuration. */
1528 struct pf_start_tunnel_config tunnel_config;
1529 __le16 event_ring_sb_id /* Status block ID */;
1530 /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */
1532 u8 num_vfs /* Amount of vfs owned by PF */;
1533 u8 event_ring_num_pages /* Number of PBL pages in event ring */;
1534 u8 event_ring_sb_index /* Status block index */;
1535 u8 path_id /* HW path ID (engine ID) */;
1536 u8 warning_as_error /* In FW asserts, treat warning as error */;
1537 /* If not set - throw a warning for each ramrod (for debug) */
1538 u8 dont_log_ramrods;
1539 u8 personality /* define what type of personality is new PF */;
1540 /* Log type mask. Each bit set enables a corresponding event type logging.
1541 * Event types are defined as ASSERT_LOG_TYPE_xxx
1543 __le16 log_type_mask;
1544 u8 mf_mode /* Multi function mode */;
1545 u8 integ_phase /* Integration phase */;
1546 /* If set, inter-pf tx switching is allowed in Switch Independent func mode */
1547 u8 allow_npar_tx_switching;
1549 /* FP HSI version to be used by FW */
1550 struct hsi_fp_ver_struct hsi_fp_ver;
1551 /* Outer tag configurations */
1552 struct outer_tag_config_struct outer_tag_config;
1558 * Per protocol DCB data
1560 struct protocol_dcb_data {
1561 u8 dcb_enable_flag /* Enable DCB */;
1562 u8 dscp_enable_flag /* Enable updating DSCP value */;
1563 u8 dcb_priority /* DCB priority */;
1564 u8 dcb_tc /* DCB TC */;
1565 u8 dscp_val /* DSCP value to write if dscp_enable_flag is set */;
1566 /* When DCB is enabled - if this flag is set, dont add VLAN 0 tag to untagged
1569 u8 dcb_dont_add_vlan0;
1573 * Update tunnel configuration
1575 struct pf_update_tunnel_config {
1576 /* Update RX per PF tunnel classification scheme. */
1577 u8 update_rx_pf_clss;
1578 /* Update per PORT default tunnel RX classification scheme for traffic with
1579 * unknown unicast outer MAC in NPAR mode.
1581 u8 update_rx_def_ucast_clss;
1582 /* Update per PORT default tunnel RX classification scheme for traffic with non
1583 * unicast outer MAC in NPAR mode.
1585 u8 update_rx_def_non_ucast_clss;
1586 /* Update VXLAN tunnel UDP destination port. */
1587 u8 set_vxlan_udp_port_flg;
1588 /* Update GENEVE tunnel UDP destination port. */
1589 u8 set_geneve_udp_port_flg;
1590 /* Update no-innet-L2 VXLAN tunnel UDP destination port. */
1591 u8 set_no_inner_l2_vxlan_udp_port_flg;
1592 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
1593 /* Classification scheme for l2 GENEVE tunnel. */
1594 u8 tunnel_clss_l2geneve;
1595 /* Classification scheme for ip GENEVE tunnel. */
1596 u8 tunnel_clss_ipgeneve;
1597 u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */;
1598 u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;
1600 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
1601 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;
1602 /* no-innet-L2 VXLAN tunnel UDP destination port. */
1603 __le16 no_inner_l2_vxlan_udp_port;
1604 __le16 reserved1[3];
1608 * Data for port update ramrod
1610 struct pf_update_ramrod_data {
1611 /* Update Eth DCB data indication (use enum dcb_dscp_update_mode) */
1612 u8 update_eth_dcb_data_mode;
1613 /* Update FCOE DCB data indication (use enum dcb_dscp_update_mode) */
1614 u8 update_fcoe_dcb_data_mode;
1615 /* Update iSCSI DCB data indication (use enum dcb_dscp_update_mode) */
1616 u8 update_iscsi_dcb_data_mode;
1617 u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication */;
1618 /* Update RROCE (RoceV2) DCB data indication */
1619 u8 update_rroce_dcb_data_mode;
1620 u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication */;
1621 u8 update_mf_vlan_flag /* Update MF outer vlan Id */;
1622 /* Update Enable STAG Priority Change indication */
1623 u8 update_enable_stag_pri_change;
1624 struct protocol_dcb_data eth_dcb_data /* core eth related fields */;
1625 struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */;
1626 /* core iscsi related fields */
1627 struct protocol_dcb_data iscsi_dcb_data;
1628 struct protocol_dcb_data roce_dcb_data /* core roce related fields */;
1629 /* core roce related fields */
1630 struct protocol_dcb_data rroce_dcb_data;
1631 /* core iwarp related fields */
1632 struct protocol_dcb_data iwarp_dcb_data;
1633 __le16 mf_vlan /* new outer vlan id value */;
1634 /* enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette
1635 * Davis, UFP with Host Control mode, and UFP with DCB over base interface.
1638 u8 enable_stag_pri_change;
1640 /* tunnel configuration. */
1641 struct pf_update_tunnel_config tunnel_config;
1650 ENGX2_PORTX1 /* 2 engines x 1 port */,
1651 ENGX2_PORTX2 /* 2 engines x 2 ports */,
1652 ENGX1_PORTX1 /* 1 engine x 1 port */,
1653 ENGX1_PORTX2 /* 1 engine x 2 ports */,
1654 ENGX1_PORTX4 /* 1 engine x 4 ports */,
1661 * use to index in hsi_fp_[major|minor]_ver_arr per protocol
1663 enum protocol_version_array_key {
1666 MAX_PROTOCOL_VERSION_ARRAY_KEY
1674 struct rdma_sent_stats {
1675 struct regpair sent_bytes /* number of total RDMA bytes sent */;
1676 struct regpair sent_pkts /* number of total RDMA packets sent */;
1680 * Pstorm non-triggering VF zone
1682 struct pstorm_non_trigger_vf_zone {
1683 /* VF statistic bucket */
1684 struct eth_pstorm_per_queue_stat eth_queue_stat;
1685 struct rdma_sent_stats rdma_stats /* RoCE sent statistics */;
1692 struct pstorm_vf_zone {
1693 /* non-interrupt-triggering zone */
1694 struct pstorm_non_trigger_vf_zone non_trigger;
1695 struct regpair reserved[7] /* vf_zone size mus be power of 2 */;
1700 * Ramrod Header of SPQE
1702 struct ramrod_header {
1703 __le32 cid /* Slowpath Connection CID */;
1704 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */;
1705 u8 protocol_id /* Ramrod Protocol ID */;
1706 __le16 echo /* Ramrod echo */;
1713 struct rdma_rcv_stats {
1714 struct regpair rcv_bytes /* number of total RDMA bytes received */;
1715 struct regpair rcv_pkts /* number of total RDMA packets received */;
1721 * Data for update QCN/DCQCN RL ramrod
1723 struct rl_update_ramrod_data {
1724 u8 qcn_update_param_flg /* Update QCN global params: timeout. */;
1725 /* Update DCQCN global params: timeout, g, k. */
1726 u8 dcqcn_update_param_flg;
1727 u8 rl_init_flg /* Init RL parameters, when RL disabled. */;
1728 u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */;
1729 u8 rl_stop_flg /* Stop RL. */;
1730 u8 rl_id_first /* ID of first or single RL, that will be updated. */;
1731 /* ID of last RL, that will be updated. If clear, single RL will updated. */
1733 u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */;
1734 /* If set, alpha will be reset to 1 when the state machine is idle. */
1735 u8 dcqcn_reset_alpha_on_idle;
1736 /* Byte counter threshold to change rate increase stage. */
1738 /* Timer threshold to change rate increase stage. */
1739 u8 rl_timer_stage_th;
1741 __le32 rl_bc_rate /* Byte Counter Limit. */;
1742 __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */;
1743 __le16 rl_r_ai /* Active increase rate. */;
1744 __le16 rl_r_hai /* Hyper active increase rate. */;
1745 __le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */;
1746 __le32 dcqcn_k_us /* DCQCN Alpha update interval. */;
1747 __le32 dcqcn_timeuot_us /* DCQCN timeout. */;
1748 __le32 qcn_timeuot_us /* QCN timeout. */;
1754 * Slowpath Element (SPQE)
1756 struct slow_path_element {
1757 struct ramrod_header hdr /* Ramrod Header */;
1758 struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */;
1763 * Tstorm non-triggering VF zone
1765 struct tstorm_non_trigger_vf_zone {
1766 struct rdma_rcv_stats rdma_stats /* RoCE received statistics */;
1770 struct tstorm_per_port_stat {
1771 /* packet is dropped because it was truncated in NIG */
1772 struct regpair trunc_error_discard;
1773 /* packet is dropped because of Ethernet FCS error */
1774 struct regpair mac_error_discard;
1775 /* packet is dropped because classification was unsuccessful */
1776 struct regpair mftag_filter_discard;
1777 /* packet was passed to Ethernet and dropped because of no mac filter match */
1778 struct regpair eth_mac_filter_discard;
1779 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1782 struct regpair ll2_mac_filter_discard;
1783 /* packet passed to Light L2 and dropped because Light L2 is not configured for
1786 struct regpair ll2_conn_disabled_discard;
1787 /* packet is an ISCSI irregular packet */
1788 struct regpair iscsi_irregular_pkt;
1789 /* packet is an FCOE irregular packet */
1790 struct regpair fcoe_irregular_pkt;
1791 /* packet is an ROCE irregular packet */
1792 struct regpair roce_irregular_pkt;
1793 /* packet is an IWARP irregular packet */
1794 struct regpair iwarp_irregular_pkt;
1795 /* packet is an ETH irregular packet */
1796 struct regpair eth_irregular_pkt;
1797 /* packet is an TOE irregular packet */
1798 struct regpair toe_irregular_pkt;
1799 /* packet is an PREROCE irregular packet */
1800 struct regpair preroce_irregular_pkt;
1801 struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */;
1802 /* VXLAN dropped packets */
1803 struct regpair eth_vxlan_tunn_filter_discard;
1804 /* GENEVE dropped packets */
1805 struct regpair eth_geneve_tunn_filter_discard;
1806 struct regpair eth_gft_drop_pkt /* GFT dropped packets */;
1813 struct tstorm_vf_zone {
1814 /* non-interrupt-triggering zone */
1815 struct tstorm_non_trigger_vf_zone non_trigger;
1820 * Tunnel classification scheme
1823 /* Use MAC and VLAN from first L2 header for vport classification. */
1824 TUNNEL_CLSS_MAC_VLAN = 0,
1825 /* Use MAC from first L2 header and VNI from tunnel header for vport
1828 TUNNEL_CLSS_MAC_VNI,
1829 /* Use MAC and VLAN from last L2 header for vport classification */
1830 TUNNEL_CLSS_INNER_MAC_VLAN,
1831 /* Use MAC from last L2 header and VNI from tunnel header for vport
1834 TUNNEL_CLSS_INNER_MAC_VNI,
1835 /* Use MAC and VLAN from last L2 header for vport classification. If no exact
1836 * match, use MAC and VLAN from first L2 header for classification.
1838 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1845 * Ustorm non-triggering VF zone
1847 struct ustorm_non_trigger_vf_zone {
1848 /* VF statistic bucket */
1849 struct eth_ustorm_per_queue_stat eth_queue_stat;
1850 struct regpair vf_pf_msg_addr /* VF-PF message address */;
1855 * Ustorm triggering VF zone
1857 struct ustorm_trigger_vf_zone {
1858 u8 vf_pf_msg_valid /* VF-PF message valid flag */;
1866 struct ustorm_vf_zone {
1867 /* non-interrupt-triggering zone */
1868 struct ustorm_non_trigger_vf_zone non_trigger;
1869 struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */;
1874 * VF-PF channel data
1876 struct vf_pf_channel_data {
1877 /* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel
1878 * is ready for a new transaction.
1881 /* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is
1891 * Ramrod data for VF start ramrod
1893 struct vf_start_ramrod_data {
1894 u8 vf_id /* VF ID */;
1895 /* If set, initial cleanup ack will be sent to parent PF SP event queue */
1897 __le16 opaque_fid /* VF opaque FID */;
1898 u8 personality /* define what type of personality is new VF */;
1900 /* FP HSI version to be used by FW */
1901 struct hsi_fp_ver_struct hsi_fp_ver;
1906 * Ramrod data for VF start ramrod
1908 struct vf_stop_ramrod_data {
1909 u8 vf_id /* VF ID */;
1917 * VF zone size mode.
1919 enum vf_zone_size_mode {
1920 /* Default VF zone size. Up to 192 VF supported. */
1921 VF_ZONE_SIZE_MODE_DEFAULT,
1922 /* Doubled VF zone size. Up to 96 VF supported. */
1923 VF_ZONE_SIZE_MODE_DOUBLE,
1924 /* Quad VF zone size. Up to 48 VF supported. */
1925 VF_ZONE_SIZE_MODE_QUAD,
1926 MAX_VF_ZONE_SIZE_MODE
1933 * Xstorm non-triggering VF zone
1935 struct xstorm_non_trigger_vf_zone {
1936 struct regpair non_edpm_ack_pkts /* RoCE received statistics */;
1943 struct xstorm_vf_zone {
1944 /* non-interrupt-triggering zone */
1945 struct xstorm_non_trigger_vf_zone non_trigger;
1951 * Attentions status block
1953 struct atten_status_block {
1957 __le16 sb_index /* status block running index */;
1967 /* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */
1968 #define DMAE_CMD_SRC_MASK 0x1
1969 #define DMAE_CMD_SRC_SHIFT 0
1970 /* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None
1971 * (use enum dmae_cmd_dst_enum)
1973 #define DMAE_CMD_DST_MASK 0x3
1974 #define DMAE_CMD_DST_SHIFT 1
1975 /* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */
1976 #define DMAE_CMD_C_DST_MASK 0x1
1977 #define DMAE_CMD_C_DST_SHIFT 3
1978 /* Reset the CRC result (do not use the previous result as the seed) */
1979 #define DMAE_CMD_CRC_RESET_MASK 0x1
1980 #define DMAE_CMD_CRC_RESET_SHIFT 4
1981 /* Reset the source address in the next go to the same source address of the
1984 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1985 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1986 /* Reset the destination address in the next go to the same destination address
1987 * of the previous go
1989 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1990 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1991 /* 0 completion function is the same as src function, 1 - 0 completion
1992 * function is the same as dst function (use enum dmae_cmd_comp_func_enum)
1994 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1995 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1996 /* 0 - Do not write a completion word, 1 - Write a completion word
1997 * (use enum dmae_cmd_comp_word_en_enum)
1999 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
2000 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
2001 /* 0 - Do not write a CRC word, 1 - Write a CRC word
2002 * (use enum dmae_cmd_comp_crc_en_enum)
2004 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
2005 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
2006 /* The CRC word should be taken from the DMAE address space from address 9+X,
2007 * where X is the value in these bits.
2009 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
2010 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
2011 #define DMAE_CMD_RESERVED1_MASK 0x1
2012 #define DMAE_CMD_RESERVED1_SHIFT 13
2013 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
2014 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
2015 /* The field specifies how the completion word is affected by PCIe read error. 0
2016 * Send a regular completion, 1 - Send a completion with an error indication,
2017 * 2 do not send a completion (use enum dmae_cmd_error_handling_enum)
2019 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
2020 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
2021 /* The port ID to be placed on the RF FID field of the GRC bus. this field is
2022 * used both when GRC is the destination and when it is the source of the DMAE
2025 #define DMAE_CMD_PORT_ID_MASK 0x3
2026 #define DMAE_CMD_PORT_ID_SHIFT 18
2027 /* Source PCI function number [3:0] */
2028 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
2029 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
2030 /* Destination PCI function number [3:0] */
2031 #define DMAE_CMD_DST_PF_ID_MASK 0xF
2032 #define DMAE_CMD_DST_PF_ID_SHIFT 24
2033 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 /* Source VFID valid */
2034 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
2035 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 /* Destination VFID valid */
2036 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
2037 #define DMAE_CMD_RESERVED2_MASK 0x3
2038 #define DMAE_CMD_RESERVED2_SHIFT 30
2039 /* PCIe source address low in bytes or GRC source address in DW */
2041 /* PCIe source address high in bytes or reserved (if source is GRC) */
2043 /* PCIe destination address low in bytes or GRC destination address in DW */
2045 /* PCIe destination address high in bytes or reserved (if destination is GRC) */
2047 __le16 length_dw /* Length in DW */;
2049 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */
2050 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
2051 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */
2052 #define DMAE_CMD_DST_VF_ID_SHIFT 8
2053 /* PCIe completion address low in bytes or GRC completion address in DW */
2054 __le32 comp_addr_lo;
2055 /* PCIe completion address high in bytes or reserved (if completion address is
2058 __le32 comp_addr_hi;
2059 __le32 comp_val /* Value to write to completion address */;
2060 __le32 crc32 /* crc16 result */;
2061 __le32 crc_32_c /* crc32_c result */;
2062 __le16 crc16 /* crc16 result */;
2063 __le16 crc16_c /* crc16_c result */;
2064 __le16 crc10 /* crc_t10 result */;
2065 __le16 error_bit_reserved;
2066 #define DMAE_CMD_ERROR_BIT_MASK 0x1 /* Error bit */
2067 #define DMAE_CMD_ERROR_BIT_SHIFT 0
2068 #define DMAE_CMD_RESERVED_MASK 0x7FFF
2069 #define DMAE_CMD_RESERVED_SHIFT 1
2070 __le16 xsum16 /* checksum16 result */;
2071 __le16 xsum8 /* checksum8 result */;
2075 enum dmae_cmd_comp_crc_en_enum {
2076 dmae_cmd_comp_crc_disabled /* Do not write a CRC word */,
2077 dmae_cmd_comp_crc_enabled /* Write a CRC word */,
2078 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
2082 enum dmae_cmd_comp_func_enum {
2083 /* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */
2084 dmae_cmd_comp_func_to_src,
2085 /* completion word and/or CRC will be sent to DST-PCI function/DST VFID */
2086 dmae_cmd_comp_func_to_dst,
2087 MAX_DMAE_CMD_COMP_FUNC_ENUM
2091 enum dmae_cmd_comp_word_en_enum {
2092 dmae_cmd_comp_word_disabled /* Do not write a completion word */,
2093 dmae_cmd_comp_word_enabled /* Write the completion word */,
2094 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
2098 enum dmae_cmd_c_dst_enum {
2099 dmae_cmd_c_dst_pcie,
2101 MAX_DMAE_CMD_C_DST_ENUM
2105 enum dmae_cmd_dst_enum {
2106 dmae_cmd_dst_none_0,
2109 dmae_cmd_dst_none_3,
2110 MAX_DMAE_CMD_DST_ENUM
2114 enum dmae_cmd_error_handling_enum {
2115 /* Send a regular completion (with no error indication) */
2116 dmae_cmd_error_handling_send_regular_comp,
2117 /* Send a completion with an error indication (i.e. set bit 31 of the completion
2120 dmae_cmd_error_handling_send_comp_with_err,
2121 dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */,
2122 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
2126 enum dmae_cmd_src_enum {
2127 dmae_cmd_src_pcie /* The source is the PCIe */,
2128 dmae_cmd_src_grc /* The source is the GRC */,
2129 MAX_DMAE_CMD_SRC_ENUM
2136 struct dmae_params {
2138 /* If set and the source is a block of length DMAE_MAX_RW_SIZE and the
2139 * destination is larger, the source block will be duplicated as many
2140 * times as required to fill the destination block. This is used mostly
2141 * to write a zeroed buffer to destination address using DMA
2143 #define DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
2144 #define DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
2145 /* If set, the source is a VF, and the source VF ID is taken from the
2146 * src_vf_id parameter.
2148 #define DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
2149 #define DMAE_PARAMS_SRC_VF_VALID_SHIFT 1
2150 /* If set, the destination is a VF, and the destination VF ID is taken
2151 * from the dst_vf_id parameter.
2153 #define DMAE_PARAMS_DST_VF_VALID_MASK 0x1
2154 #define DMAE_PARAMS_DST_VF_VALID_SHIFT 2
2155 /* If set, a completion is sent to the destination function.
2156 * Otherwise its sent to the source function.
2158 #define DMAE_PARAMS_COMPLETION_DST_MASK 0x1
2159 #define DMAE_PARAMS_COMPLETION_DST_SHIFT 3
2160 /* If set, the port ID is taken from the port_id parameter.
2161 * Otherwise, the current port ID is used.
2163 #define DMAE_PARAMS_PORT_VALID_MASK 0x1
2164 #define DMAE_PARAMS_PORT_VALID_SHIFT 4
2165 /* If set, the source PF ID is taken from the src_pf_id parameter.
2166 * Otherwise, the current PF ID is used.
2168 #define DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
2169 #define DMAE_PARAMS_SRC_PF_VALID_SHIFT 5
2170 /* If set, the destination PF ID is taken from the dst_pf_id parameter.
2171 * Otherwise, the current PF ID is used
2173 #define DMAE_PARAMS_DST_PF_VALID_MASK 0x1
2174 #define DMAE_PARAMS_DST_PF_VALID_SHIFT 6
2175 #define DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
2176 #define DMAE_PARAMS_RESERVED_SHIFT 7
2177 u8 src_vf_id /* Source VF ID, valid only if src_vf_valid is set */;
2178 u8 dst_vf_id /* Destination VF ID, valid only if dst_vf_valid is set */;
2179 u8 port_id /* Port ID, valid only if port_valid is set */;
2180 u8 src_pf_id /* Source PF ID, valid only if src_pf_valid is set */;
2181 u8 dst_pf_id /* Destination PF ID, valid only if dst_pf_valid is set */;
2187 struct fw_asserts_ram_section {
2188 /* The offset of the section in the RAM in RAM lines (64-bit units) */
2189 __le16 section_ram_line_offset;
2190 /* The size of the section in RAM lines (64-bit units) */
2191 __le16 section_ram_line_size;
2192 /* The offset of the asserts list within the section in dwords */
2193 u8 list_dword_offset;
2194 /* The size of an assert list element in dwords */
2195 u8 list_element_dword_size;
2196 u8 list_num_elements /* The number of elements in the asserts list */;
2197 /* The offset of the next list index field within the section in dwords */
2198 u8 list_next_index_dword_offset;
2203 u8 major /* Firmware major version number */;
2204 u8 minor /* Firmware minor version number */;
2205 u8 rev /* Firmware revision version number */;
2206 u8 eng /* Firmware engineering version number (for bootleg versions) */;
2209 struct fw_ver_info {
2210 __le16 tools_ver /* Tools version number */;
2211 u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
2213 struct fw_ver_num num /* FW version number */;
2214 __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
2219 struct fw_ver_info ver /* FW version information */;
2220 /* Info regarding the FW asserts section in the Storm RAM */
2221 struct fw_asserts_ram_section fw_asserts_section;
2225 struct fw_info_location {
2226 __le32 grc_addr /* GRC address where the fw_info struct is located. */;
2227 /* Size of the fw_info structure (thats located at the grc_addr). */
2235 * IGU cleanup command
2237 struct igu_cleanup {
2238 __le32 sb_id_and_flags;
2239 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
2240 #define IGU_CLEANUP_RESERVED0_SHIFT 0
2241 /* cleanup clear - 0, set - 1 */
2242 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
2243 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
2244 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
2245 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
2246 /* must always be set (use enum command_type_bit) */
2247 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1U
2248 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
2254 * IGU firmware driver command
2257 struct igu_prod_cons_update prod_cons_update;
2258 struct igu_cleanup cleanup;
2263 * IGU firmware driver command
2265 struct igu_command_reg_ctrl {
2267 __le16 igu_command_reg_ctrl_fields;
2268 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
2269 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
2270 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
2271 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
2272 /* command typ: 0 - read, 1 - write */
2273 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
2274 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
2279 * IGU mapping line structure
2281 struct igu_mapping_line {
2282 __le32 igu_mapping_line_fields;
2283 #define IGU_MAPPING_LINE_VALID_MASK 0x1
2284 #define IGU_MAPPING_LINE_VALID_SHIFT 0
2285 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
2286 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
2287 /* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */
2288 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
2289 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
2290 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */
2291 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
2292 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
2293 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
2294 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
2295 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
2300 * IGU MSIX line structure
2302 struct igu_msix_vector {
2303 struct regpair address;
2305 __le32 msix_vector_fields;
2306 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
2307 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
2308 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
2309 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
2310 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
2311 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
2312 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
2313 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
2317 struct mstorm_core_conn_ag_ctx {
2318 u8 byte0 /* cdu_validation */;
2319 u8 byte1 /* state */;
2321 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2322 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2323 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2324 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2325 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2326 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2327 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2328 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2329 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2330 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2332 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2333 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2334 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2335 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2336 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2337 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2338 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2339 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2340 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2341 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2342 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2343 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2344 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2345 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2346 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2347 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2348 __le16 word0 /* word0 */;
2349 __le16 word1 /* word1 */;
2350 __le32 reg0 /* reg0 */;
2351 __le32 reg1 /* reg1 */;
2356 * per encapsulation type enabling flags
2358 struct prs_reg_encapsulation_type_en {
2360 /* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */
2361 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
2362 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
2363 /* Enable bit for IP-over-GRE (IP GRE) encapsulation. */
2364 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
2365 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
2366 /* Enable bit for VXLAN encapsulation. */
2367 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
2368 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
2369 /* Enable bit for T-Tag encapsulation. */
2370 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
2371 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
2372 /* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */
2373 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
2374 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
2375 /* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */
2376 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
2377 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
2378 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
2379 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
2383 enum pxp_tph_st_hint {
2384 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
2385 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
2386 /* Device Write and Host Read, or Host Write and Device Read */
2388 /* Device Write and Host Read, or Host Write and Device Read - with temporal
2391 TPH_ST_HINT_TARGET_PRIO,
2397 * QM hardware structure of enable bypass credit mask
2399 struct qm_rf_bypass_mask {
2401 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
2402 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
2403 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
2404 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
2405 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
2406 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
2407 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
2408 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
2409 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
2410 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
2411 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
2412 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
2413 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
2414 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
2415 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
2416 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
2421 * QM hardware structure of opportunistic credit mask
2423 struct qm_rf_opportunistic_mask {
2425 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
2426 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
2427 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
2428 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
2429 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
2430 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
2431 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
2432 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
2433 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
2434 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
2435 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
2436 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
2437 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
2438 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
2439 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
2440 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
2441 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
2442 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
2443 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
2444 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
2449 * QM hardware structure of QM map memory
2451 struct qm_rf_pq_map {
2453 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */
2454 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
2455 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */
2456 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1
2457 /* the first PQ associated with the VPORT and VOQ of this PQ */
2458 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
2459 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
2460 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */
2461 #define QM_RF_PQ_MAP_VOQ_SHIFT 18
2462 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
2463 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
2464 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */
2465 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
2466 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
2467 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26
2472 * Completion params for aggregated interrupt completion
2474 struct sdm_agg_int_comp_params {
2476 /* the number of aggregated interrupt, 0-31 */
2477 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
2478 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
2479 /* 1 - set a bit in aggregated vector, 0 - dont set */
2480 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
2481 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
2482 /* Number of bit in the aggregated vector, 0-279 (TBD) */
2483 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
2484 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
2489 * SDM operation gen command (generate aggregative interrupt)
2493 /* completion parameters 0-15 */
2494 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
2495 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2496 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */
2497 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
2498 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */
2499 #define SDM_OP_GEN_RESERVED_SHIFT 20
2502 struct ystorm_core_conn_ag_ctx {
2503 u8 byte0 /* cdu_validation */;
2504 u8 byte1 /* state */;
2506 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
2507 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
2508 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
2509 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
2510 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
2511 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
2512 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
2513 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
2514 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
2515 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
2517 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
2518 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
2519 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
2520 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
2521 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
2522 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
2523 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
2524 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
2525 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
2526 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
2527 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
2528 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
2529 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
2530 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
2531 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
2532 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
2533 u8 byte2 /* byte2 */;
2534 u8 byte3 /* byte3 */;
2535 __le16 word0 /* word0 */;
2536 __le32 reg0 /* reg0 */;
2537 __le32 reg1 /* reg1 */;
2538 __le16 word1 /* word1 */;
2539 __le16 word2 /* word2 */;
2540 __le16 word3 /* word3 */;
2541 __le16 word4 /* word4 */;
2542 __le32 reg2 /* reg2 */;
2543 __le32 reg3 /* reg3 */;
2546 #endif /* __ECORE_HSI_COMMON__ */