2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_ETH__
10 #define __ECORE_HSI_ETH__
11 /************************************************************************/
12 /* Add include to common eth target for both eCore and protocol driver */
13 /************************************************************************/
14 #include "eth_common.h"
17 * The eth storm context for the Tstorm
19 struct tstorm_eth_conn_st_ctx {
24 * The eth storm context for the Pstorm
26 struct pstorm_eth_conn_st_ctx {
31 * The eth storm context for the Xstorm
33 struct xstorm_eth_conn_st_ctx {
37 struct xstorm_eth_conn_ag_ctx {
38 u8 reserved0 /* cdu_validation */;
39 u8 eth_state /* state */;
42 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
43 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
45 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
46 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
48 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
49 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
51 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
52 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
54 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
55 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
57 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
58 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
60 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
61 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
63 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
64 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
67 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
68 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
70 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
71 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
73 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
74 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
76 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
77 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
79 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
80 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
82 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
83 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
85 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
86 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
88 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
89 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
92 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
93 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
95 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
96 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
98 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
99 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
101 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
102 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
105 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
106 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
108 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
109 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
111 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
112 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
114 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
115 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
118 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
119 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
121 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
122 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
124 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
125 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
127 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
128 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
131 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
132 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
134 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
135 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
137 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
138 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
140 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
141 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
144 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
145 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
147 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
148 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
150 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
151 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
153 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
154 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
157 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
158 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
160 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
161 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
163 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
164 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
166 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
167 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
169 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
170 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
173 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
174 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
176 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
177 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
179 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
180 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
182 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
183 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
185 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
186 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
188 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
189 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
191 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
192 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
194 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
195 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
198 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
199 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
201 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
202 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
204 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
205 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
207 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
208 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
210 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
211 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
213 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
214 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
216 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
217 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
219 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
220 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
223 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
224 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
226 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
227 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
229 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
230 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
232 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
233 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
235 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
236 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
238 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
239 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
241 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
242 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
244 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
245 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
248 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
249 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
251 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
252 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
254 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
255 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
257 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
258 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
260 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
261 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
263 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
264 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
266 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
267 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
269 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
270 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
273 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
274 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
276 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
277 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
279 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
280 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
282 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
283 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
285 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
286 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
288 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
289 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
291 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
292 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
294 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
295 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
298 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
299 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
301 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
302 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
304 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
305 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
307 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
308 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
310 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
311 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
313 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
314 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
316 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
317 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
319 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
320 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
323 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
324 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
326 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
327 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
329 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
330 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
332 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
333 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
335 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
336 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
338 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
339 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
341 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
342 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
343 u8 edpm_event_id /* byte2 */;
344 __le16 physical_q0 /* physical_q0 */;
345 __le16 quota /* physical_q1 */;
346 __le16 edpm_num_bds /* physical_q2 */;
347 __le16 tx_bd_cons /* word3 */;
348 __le16 tx_bd_prod /* word4 */;
349 __le16 tx_class /* word5 */;
350 __le16 conn_dpi /* conn_dpi */;
351 u8 byte3 /* byte3 */;
352 u8 byte4 /* byte4 */;
353 u8 byte5 /* byte5 */;
354 u8 byte6 /* byte6 */;
355 __le32 reg0 /* reg0 */;
356 __le32 reg1 /* reg1 */;
357 __le32 reg2 /* reg2 */;
358 __le32 reg3 /* reg3 */;
359 __le32 reg4 /* reg4 */;
360 __le32 reg5 /* cf_array0 */;
361 __le32 reg6 /* cf_array1 */;
362 __le16 word7 /* word7 */;
363 __le16 word8 /* word8 */;
364 __le16 word9 /* word9 */;
365 __le16 word10 /* word10 */;
366 __le32 reg7 /* reg7 */;
367 __le32 reg8 /* reg8 */;
368 __le32 reg9 /* reg9 */;
369 u8 byte7 /* byte7 */;
370 u8 byte8 /* byte8 */;
371 u8 byte9 /* byte9 */;
372 u8 byte10 /* byte10 */;
373 u8 byte11 /* byte11 */;
374 u8 byte12 /* byte12 */;
375 u8 byte13 /* byte13 */;
376 u8 byte14 /* byte14 */;
377 u8 byte15 /* byte15 */;
378 u8 byte16 /* byte16 */;
379 __le16 word11 /* word11 */;
380 __le32 reg10 /* reg10 */;
381 __le32 reg11 /* reg11 */;
382 __le32 reg12 /* reg12 */;
383 __le32 reg13 /* reg13 */;
384 __le32 reg14 /* reg14 */;
385 __le32 reg15 /* reg15 */;
386 __le32 reg16 /* reg16 */;
387 __le32 reg17 /* reg17 */;
388 __le32 reg18 /* reg18 */;
389 __le32 reg19 /* reg19 */;
390 __le16 word12 /* word12 */;
391 __le16 word13 /* word13 */;
392 __le16 word14 /* word14 */;
393 __le16 word15 /* word15 */;
397 * The eth storm context for the Ystorm
399 struct ystorm_eth_conn_st_ctx {
403 struct ystorm_eth_conn_ag_ctx {
404 u8 byte0 /* cdu_validation */;
405 u8 state /* state */;
408 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
409 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
411 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
412 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
413 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */
414 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
415 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */
416 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
417 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
418 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
421 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
422 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
424 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
425 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
427 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
428 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
430 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
431 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
433 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
434 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
436 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
437 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
439 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
440 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
442 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
443 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
444 u8 tx_q0_int_coallecing_timeset /* byte2 */;
445 u8 byte3 /* byte3 */;
446 __le16 word0 /* word0 */;
447 __le32 terminate_spqe /* reg0 */;
448 __le32 reg1 /* reg1 */;
449 __le16 tx_bd_cons_upd /* word1 */;
450 __le16 word2 /* word2 */;
451 __le16 word3 /* word3 */;
452 __le16 word4 /* word4 */;
453 __le32 reg2 /* reg2 */;
454 __le32 reg3 /* reg3 */;
457 struct tstorm_eth_conn_ag_ctx {
458 u8 byte0 /* cdu_validation */;
459 u8 byte1 /* state */;
461 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
462 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
463 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
464 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
465 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
466 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
467 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
468 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
469 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
470 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
471 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
472 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
473 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
474 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
476 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
477 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
478 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
479 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
480 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
481 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
482 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
483 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
485 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
486 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
487 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
488 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
489 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
490 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
491 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
492 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
494 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
495 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
496 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
497 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
498 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
499 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
500 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
501 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
502 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
503 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
504 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
505 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
507 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
508 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
509 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
510 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
511 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
512 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
513 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
514 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
515 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
516 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
517 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
518 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
519 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
520 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
521 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
522 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
524 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
525 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
526 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
527 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
528 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
529 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
530 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
531 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
532 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
533 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
534 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */
535 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
536 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
537 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
538 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
539 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
540 __le32 reg0 /* reg0 */;
541 __le32 reg1 /* reg1 */;
542 __le32 reg2 /* reg2 */;
543 __le32 reg3 /* reg3 */;
544 __le32 reg4 /* reg4 */;
545 __le32 reg5 /* reg5 */;
546 __le32 reg6 /* reg6 */;
547 __le32 reg7 /* reg7 */;
548 __le32 reg8 /* reg8 */;
549 u8 byte2 /* byte2 */;
550 u8 byte3 /* byte3 */;
551 __le16 rx_bd_cons /* word0 */;
552 u8 byte4 /* byte4 */;
553 u8 byte5 /* byte5 */;
554 __le16 rx_bd_prod /* word1 */;
555 __le16 word2 /* conn_dpi */;
556 __le16 word3 /* word3 */;
557 __le32 reg9 /* reg9 */;
558 __le32 reg10 /* reg10 */;
561 struct ustorm_eth_conn_ag_ctx {
562 u8 byte0 /* cdu_validation */;
563 u8 byte1 /* state */;
566 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
567 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
569 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
570 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
572 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
573 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
575 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
576 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
578 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
579 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
582 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
583 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
585 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
586 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
588 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
589 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
591 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
592 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
595 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
596 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
598 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
599 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
601 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
602 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
604 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
605 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
607 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
608 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
610 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
611 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
613 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
614 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
616 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
617 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
620 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
621 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
623 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
624 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
626 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
627 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
629 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
630 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
632 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
633 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
635 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
636 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
638 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
639 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
641 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
642 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
643 u8 byte2 /* byte2 */;
644 u8 byte3 /* byte3 */;
645 __le16 word0 /* conn_dpi */;
646 __le16 tx_bd_cons /* word1 */;
647 __le32 reg0 /* reg0 */;
648 __le32 reg1 /* reg1 */;
649 __le32 reg2 /* reg2 */;
650 __le32 tx_int_coallecing_timeset /* reg3 */;
651 __le16 tx_drv_bd_cons /* word2 */;
652 __le16 rx_drv_cqe_cons /* word3 */;
656 * The eth storm context for the Ustorm
658 struct ustorm_eth_conn_st_ctx {
663 * The eth storm context for the Mstorm
665 struct mstorm_eth_conn_st_ctx {
670 * eth connection context
672 struct eth_conn_context {
673 /* tstorm storm context */
674 struct tstorm_eth_conn_st_ctx tstorm_st_context;
675 struct regpair tstorm_st_padding[2] /* padding */;
676 /* pstorm storm context */
677 struct pstorm_eth_conn_st_ctx pstorm_st_context;
678 /* xstorm storm context */
679 struct xstorm_eth_conn_st_ctx xstorm_st_context;
680 /* xstorm aggregative context */
681 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
682 /* ystorm storm context */
683 struct ystorm_eth_conn_st_ctx ystorm_st_context;
684 /* ystorm aggregative context */
685 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
686 /* tstorm aggregative context */
687 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
688 /* ustorm aggregative context */
689 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
690 /* ustorm storm context */
691 struct ustorm_eth_conn_st_ctx ustorm_st_context;
692 /* mstorm storm context */
693 struct mstorm_eth_conn_st_ctx mstorm_st_context;
698 * Ethernet filter types: mac/vlan/pair
700 enum eth_error_code {
701 ETH_OK = 0x00 /* command succeeded */,
702 /* mac add filters command failed due to cam full state */
703 ETH_FILTERS_MAC_ADD_FAIL_FULL,
704 /* mac add filters command failed due to mtt2 full state */
705 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
706 /* mac add filters command failed due to duplicate mac address */
707 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
708 /* mac add filters command failed due to duplicate mac address */
709 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
710 /* mac delete filters command failed due to not found state */
711 ETH_FILTERS_MAC_DEL_FAIL_NOF,
712 /* mac delete filters command failed due to not found state */
713 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
714 /* mac delete filters command failed due to not found state */
715 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
716 /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */
717 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
718 /* vlan add filters command failed due to cam full state */
719 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
720 /* vlan add filters command failed due to duplicate VLAN filter */
721 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
722 /* vlan delete filters command failed due to not found state */
723 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
724 /* vlan delete filters command failed due to not found state */
725 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
726 /* pair add filters command failed due to duplicate request */
727 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
728 /* pair add filters command failed due to full state */
729 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
730 /* pair add filters command failed due to full state */
731 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
732 /* pair add filters command failed due not found state */
733 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
734 /* pair add filters command failed due not found state */
735 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
736 /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */
737 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
738 /* vni add filters command failed due to cam full state */
739 ETH_FILTERS_VNI_ADD_FAIL_FULL,
740 /* vni add filters command failed due to duplicate VNI filter */
741 ETH_FILTERS_VNI_ADD_FAIL_DUP,
747 * opcodes for the event ring
749 enum eth_event_opcode {
751 ETH_EVENT_VPORT_START,
752 ETH_EVENT_VPORT_UPDATE,
753 ETH_EVENT_VPORT_STOP,
754 ETH_EVENT_TX_QUEUE_START,
755 ETH_EVENT_TX_QUEUE_STOP,
756 ETH_EVENT_RX_QUEUE_START,
757 ETH_EVENT_RX_QUEUE_UPDATE,
758 ETH_EVENT_RX_QUEUE_STOP,
759 ETH_EVENT_FILTERS_UPDATE,
760 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
761 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
762 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
763 ETH_EVENT_RX_ADD_UDP_FILTER,
764 ETH_EVENT_RX_DELETE_UDP_FILTER,
765 ETH_EVENT_RX_CREATE_GFT_ACTION,
766 ETH_EVENT_RX_GFT_UPDATE_FILTER,
772 * Classify rule types in E2/E3
774 enum eth_filter_action {
775 ETH_FILTER_ACTION_UNUSED,
776 ETH_FILTER_ACTION_REMOVE,
777 ETH_FILTER_ACTION_ADD,
778 /* Remove all filters of given type and vport ID. */
779 ETH_FILTER_ACTION_REMOVE_ALL,
780 MAX_ETH_FILTER_ACTION
785 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$
787 struct eth_filter_cmd {
788 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) */;
789 u8 vport_id /* the vport id */;
790 u8 action /* filter command action: add/remove/replace */;
801 * $$KEEP_ENDIANNESS$$
803 struct eth_filter_cmd_header {
804 u8 rx /* If set, apply these commands to the RX path */;
805 u8 tx /* If set, apply these commands to the TX path */;
806 u8 cmd_cnt /* Number of filter commands */;
807 /* 0 - dont assert in case of filter configuration error. Just return an error
808 * code. 1 - assert in case of filter configuration error.
816 * Ethernet filter types: mac/vlan/pair
818 enum eth_filter_type {
819 ETH_FILTER_TYPE_UNUSED,
820 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */,
821 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */,
822 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */,
823 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */,
824 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */,
825 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */,
826 /* Add/remove a inner MAC-VNI pair */
827 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
828 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */,
829 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */,
835 * eth IPv4 Fragment Type
837 enum eth_ipv4_frag_type {
838 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */,
839 /* First Fragment of IPv4 Packet (contains headers) */
841 /* Non-First Fragment of IPv4 Packet (does not contain headers) */
842 ETH_IPV4_NON_FIRST_FRAG,
843 MAX_ETH_IPV4_FRAG_TYPE
848 * eth IPv4 Fragment Type
858 * Ethernet Ramrod Command IDs
860 enum eth_ramrod_cmd_id {
862 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */,
863 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */,
864 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */,
865 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */,
866 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
867 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */,
868 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
869 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
870 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
871 /* RX - Create an Openflow Action */
872 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
873 /* RX - Add an Openflow Filter to the Searcher */
874 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
875 /* RX - Delete an Openflow Filter to the Searcher */
876 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
877 /* RX - Add a UDP Filter to the Searcher */
878 ETH_RAMROD_RX_ADD_UDP_FILTER,
879 /* RX - Delete a UDP Filter to the Searcher */
880 ETH_RAMROD_RX_DELETE_UDP_FILTER,
881 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
882 /* RX - Add/Delete a GFT Filter to the Searcher */
883 ETH_RAMROD_GFT_UPDATE_FILTER,
884 MAX_ETH_RAMROD_CMD_ID
889 * return code from eth sp ramrods
891 struct eth_return_code {
893 /* error code (use enum eth_error_code) */
894 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
895 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
896 #define ETH_RETURN_CODE_RESERVED_MASK 0x3
897 #define ETH_RETURN_CODE_RESERVED_SHIFT 5
898 /* rx path - 0, tx path - 1 */
899 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
900 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
905 * What to do in case an error occurs
908 ETH_TX_ERR_DROP /* Drop erroneous packet. */,
909 /* Assert an interrupt for PF, declare as malicious for VF */
910 ETH_TX_ERR_ASSERT_MALICIOUS,
916 * Array of the different error type behaviors
918 struct eth_tx_err_vals {
920 /* Wrong VLAN insertion mode (use enum eth_tx_err) */
921 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
922 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
923 /* Packet is below minimal size (use enum eth_tx_err) */
924 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
925 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
926 /* Vport has sent spoofed packet (use enum eth_tx_err) */
927 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
928 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
929 /* Packet with illegal type of inband tag (use enum eth_tx_err) */
930 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
931 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
932 /* Packet marked for VLAN insertion when inband tag is present
933 * (use enum eth_tx_err)
935 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
936 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
937 /* Non LSO packet larger than MTU (use enum eth_tx_err) */
938 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
939 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
940 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not
941 * allowed to (use enum eth_tx_err)
943 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
944 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
945 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
946 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
951 * vport rss configuration data
953 struct eth_vport_rss_config {
955 /* configuration of the IpV4 2-tuple capability */
956 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
957 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
958 /* configuration of the IpV6 2-tuple capability */
959 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
960 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
961 /* configuration of the IpV4 4-tuple capability for TCP */
962 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
963 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
964 /* configuration of the IpV6 4-tuple capability for TCP */
965 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
966 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
967 /* configuration of the IpV4 4-tuple capability for UDP */
968 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
969 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
970 /* configuration of the IpV6 4-tuple capability for UDP */
971 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
972 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
973 /* configuration of the 5-tuple capability */
974 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
975 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
976 /* if set update the rss keys */
977 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
978 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
979 /* The RSS engine ID. Must be allocated to each vport with RSS enabled.
980 * Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type.
983 u8 rss_mode /* The RSS mode for this function */;
984 u8 update_rss_key /* if set update the rss key */;
985 u8 update_rss_ind_table /* if set update the indirection table */;
986 u8 update_rss_capabilities /* if set update the capabilities */;
987 u8 tbl_size /* rss mask (Tbl size) */;
989 /* RSS indirection table */
990 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
991 /* RSS key supplied to us by OS */
992 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
1000 enum eth_vport_rss_mode {
1001 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */,
1002 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
1003 MAX_ETH_VPORT_RSS_MODE
1008 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1010 struct eth_vport_rx_mode {
1012 /* drop all unicast packets */
1013 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
1014 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
1015 /* accept all unicast packets (subject to vlan) */
1016 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1017 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1018 /* accept all unmatched unicast packets */
1019 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
1020 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
1021 /* drop all multicast packets */
1022 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
1023 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
1024 /* accept all multicast packets (subject to vlan) */
1025 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1026 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
1027 /* accept all broadcast packets (subject to vlan) */
1028 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1029 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
1030 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
1031 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
1032 __le16 reserved2[3];
1037 * Command for setting tpa parameters
1039 struct eth_vport_tpa_param {
1040 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */;
1041 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */;
1042 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */;
1043 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */;
1044 /* If set, start each tpa segment on new SGE (GRO mode). One SGE per segment
1047 u8 tpa_pkt_split_flg;
1048 /* If set, put header of first TPA segment on bd and data on SGE */
1049 u8 tpa_hdr_data_split_flg;
1050 /* If set, GRO data consistent will checked for TPA continue */
1051 u8 tpa_gro_consistent_flg;
1052 /* maximum number of opened aggregations per v-port */
1053 u8 tpa_max_aggs_num;
1054 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */;
1055 /* minimum TCP payload size for a packet to start aggregation */
1056 __le16 tpa_min_size_to_start;
1057 /* minimum TCP payload size for a packet to continue aggregation */
1058 __le16 tpa_min_size_to_cont;
1059 /* maximal number of buffers that can be used for one aggregation */
1066 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$
1068 struct eth_vport_tx_mode {
1070 /* drop all unicast packets */
1071 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
1072 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
1073 /* accept all unicast packets (subject to vlan) */
1074 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
1075 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
1076 /* drop all multicast packets */
1077 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
1078 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
1079 /* accept all multicast packets (subject to vlan) */
1080 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
1081 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
1082 /* accept all broadcast packets (subject to vlan) */
1083 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
1084 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
1085 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
1086 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
1087 __le16 reserved2[3];
1092 * Ramrod data for rx create gft action
1094 enum gft_filter_update_action {
1097 MAX_GFT_FILTER_UPDATE_ACTION
1102 * Ramrod data for rx create gft action
1104 enum gft_logic_filter_type {
1105 GFT_FILTER_TYPE /* flow FW is GFT-logic as well */,
1106 RFS_FILTER_TYPE /* flow FW is A-RFS-logic */,
1107 MAX_GFT_LOGIC_FILTER_TYPE
1114 * Ramrod data for rx add openflow filter
1116 struct rx_add_openflow_filter_data {
1117 __le16 action_icid /* CID of Action to run for this filter */;
1118 u8 priority /* Searcher String - Packet priority */;
1120 __le32 tenant_id /* Searcher String - Tenant ID */;
1121 /* Searcher String - Destination Mac Bytes 0 to 1 */
1123 /* Searcher String - Destination Mac Bytes 2 to 3 */
1125 /* Searcher String - Destination Mac Bytes 4 to 5 */
1127 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */;
1128 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */;
1129 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */;
1130 __le16 vlan_id /* Searcher String - Vlan ID */;
1131 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */;
1132 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */;
1133 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type */;
1134 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */;
1135 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1136 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */;
1137 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */;
1138 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */;
1139 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */;
1144 * Ramrod data for rx create gft action
1146 struct rx_create_gft_action_data {
1147 u8 vport_id /* Vport Id of GFT Action */;
1153 * Ramrod data for rx create openflow action
1155 struct rx_create_openflow_action_data {
1156 u8 vport_id /* ID of RX queue */;
1162 * Ramrod data for rx queue start ramrod
1164 struct rx_queue_start_ramrod_data {
1165 __le16 rx_queue_id /* ID of RX queue */;
1166 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
1167 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
1168 __le16 sb_id /* Status block ID */;
1169 u8 sb_index /* index of the protocol index */;
1170 u8 vport_id /* ID of virtual port */;
1171 u8 default_rss_queue_flg /* set queue as default rss queue if set */;
1172 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1173 u8 complete_event_flg /* post completion to the event ring if set */;
1174 u8 stats_counter_id /* Statistics counter ID */;
1175 u8 pin_context /* Pin context in CCFC to improve performance */;
1176 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */;
1177 /* PXP command TPH Valid - for packet placement */
1178 u8 pxp_tph_valid_pkt;
1179 /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */
1181 __le16 pxp_st_index /* PXP command Steering tag index */;
1182 /* Indicates that current queue belongs to poll-mode driver */
1184 /* Indicates that the current queue is using the TX notification queue
1185 * mechanism - should be set only for PMD queue
1188 /* Initial value for the toggle valid bit - used in PMD mode */
1190 /* Index of RX producers in VF zone. Used for VF only. */
1191 u8 vf_rx_prod_index;
1192 /* Backward compatibility mode. If set, unprotected mStorm queue zone will used
1193 * for VF RX producers instead of VF zone.
1195 u8 vf_rx_prod_use_zone_a;
1197 __le16 reserved1 /* FW reserved. */;
1198 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
1199 struct regpair bd_base /* bd address of the first bd page */;
1200 struct regpair reserved2 /* FW reserved. */;
1205 * Ramrod data for rx queue stop ramrod
1207 struct rx_queue_stop_ramrod_data {
1208 __le16 rx_queue_id /* ID of RX queue */;
1209 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1210 u8 complete_event_flg /* post completion to the event ring if set */;
1211 u8 vport_id /* ID of virtual port */;
1217 * Ramrod data for rx queue update ramrod
1219 struct rx_queue_update_ramrod_data {
1220 __le16 rx_queue_id /* ID of RX queue */;
1221 u8 complete_cqe_flg /* post completion to the CQE ring if set */;
1222 u8 complete_event_flg /* post completion to the event ring if set */;
1223 u8 vport_id /* ID of virtual port */;
1225 u8 reserved1 /* FW reserved. */;
1226 u8 reserved2 /* FW reserved. */;
1227 u8 reserved3 /* FW reserved. */;
1228 __le16 reserved4 /* FW reserved. */;
1229 __le16 reserved5 /* FW reserved. */;
1230 struct regpair reserved6 /* FW reserved. */;
1235 * Ramrod data for rx Add UDP Filter
1237 struct rx_udp_filter_data {
1238 __le16 action_icid /* CID of Action to run for this filter */;
1239 __le16 vlan_id /* Searcher String - Vlan ID */;
1240 u8 ip_type /* Searcher String - IP Type */;
1241 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */;
1243 /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */
1244 __le32 ip_dst_addr[4];
1245 /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */
1246 __le32 ip_src_addr[4];
1247 __le16 udp_dst_port /* Searcher String - UDP Destination Port */;
1248 __le16 udp_src_port /* Searcher String - UDP Source Port */;
1249 __le32 tenant_id /* Searcher String - Tenant ID */;
1254 * Ramrod to add filter - filter is packet headr of type of packet wished to
1255 * pass certin FW flow
1257 struct rx_update_gft_filter_data {
1258 /* Pointer to Packet Header That Defines GFT Filter */
1259 struct regpair pkt_hdr_addr;
1260 __le16 pkt_hdr_length /* Packet Header Length */;
1261 /* If is_rfs flag is set: Queue Id to associate filter with else: action icid */
1262 __le16 rx_qid_or_action_icid;
1263 /* Field is used if is_rfs flag is set: vport Id of which to associate filter
1267 /* Use enum to set type of flow using gft HW logic blocks */
1269 u8 filter_action /* Use to set type of action on filter */;
1276 * Ramrod data for tx queue start ramrod
1278 struct tx_queue_start_ramrod_data {
1279 __le16 sb_id /* Status block ID */;
1280 u8 sb_index /* Status block protocol index */;
1281 u8 vport_id /* VPort ID */;
1282 u8 reserved0 /* FW reserved. (qcn_rl_en) */;
1283 u8 stats_counter_id /* Statistics counter ID to use */;
1284 __le16 qm_pq_id /* QM PQ ID */;
1286 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */
1287 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
1288 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
1289 /* If set, Test Mode - packets will be duplicated by Xstorm handler */
1290 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
1291 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
1292 /* If set, Test Mode - packets destination will be determined by dest_port_mode
1295 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
1296 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
1297 /* Indicates that current queue belongs to poll-mode driver */
1298 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
1299 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
1300 /* Indicates that the current queue is using the TX notification queue
1301 * mechanism - should be set only for PMD queue
1303 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
1304 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
1305 /* Pin context in CCFC to improve performance */
1306 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
1307 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
1308 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
1309 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
1310 u8 pxp_st_hint /* PXP command Steering tag hint */;
1311 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */;
1312 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */;
1313 __le16 pxp_st_index /* PXP command Steering tag index */;
1314 /* TX completion min agg size - for PMD queues */
1315 __le16 comp_agg_size;
1316 __le16 queue_zone_id /* queue zone ID to use */;
1317 __le16 reserved2 /* FW reserved. (test_dup_count) */;
1318 __le16 pbl_size /* Number of BD pages pointed by PBL */;
1319 /* unique Queue ID - currently used only by PMD flow */
1321 /* Unique Same-As-Last Resource ID - improves performance for same-as-last
1322 * packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
1325 __le16 same_as_last_id;
1327 struct regpair pbl_base_addr /* address of the pbl page */;
1328 /* BD consumer address in host - for PMD queues */
1329 struct regpair bd_cons_address;
1334 * Ramrod data for tx queue stop ramrod
1336 struct tx_queue_stop_ramrod_data {
1343 * Ramrod data for vport update ramrod
1345 struct vport_filter_update_ramrod_data {
1346 /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */
1347 struct eth_filter_cmd_header filter_cmd_hdr;
1348 /* Filter Commands */
1349 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
1354 * Ramrod data for vport start ramrod
1356 struct vport_start_ramrod_data {
1360 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */;
1361 u8 inner_vlan_removal_en;
1362 struct eth_vport_rx_mode rx_mode /* Rx filter data */;
1363 struct eth_vport_tx_mode tx_mode /* Tx filter data */;
1364 /* TPA configuration parameters */
1365 struct eth_vport_tpa_param tpa_param;
1366 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1367 u8 tx_switching_en /* Tx switching is enabled for current Vport */;
1368 /* Anti-spoofing verification is set for current Vport */
1369 u8 anti_spoofing_en;
1370 /* If set, the default Vlan value is forced by the FW */
1372 /* If set, the vport handles PTP Timesync Packets */
1374 /* If enable then innerVlan will be striped and not written to cqe */
1375 u8 silent_vlan_removal_en;
1376 /* If set untagged filter (vlan0) is added to current Vport, otherwise port is
1377 * marked as any-vlan
1380 /* Desired behavior per TX error type */
1381 struct eth_tx_err_vals tx_err_behav;
1382 /* If set, ETH header padding will not inserted. placement_offset will be zero.
1384 u8 zero_placement_offset;
1385 /* If set, Contorl frames will be filtered according to MAC check. */
1386 u8 ctl_frame_mac_check_en;
1387 /* If set, Contorl frames will be filtered according to ethtype check. */
1388 u8 ctl_frame_ethtype_check_en;
1394 * Ramrod data for vport stop ramrod
1396 struct vport_stop_ramrod_data {
1403 * Ramrod data for vport update ramrod
1405 struct vport_update_ramrod_data_cmn {
1407 u8 update_rx_active_flg /* set if rx active flag should be handled */;
1408 u8 rx_active_flg /* rx active flag value */;
1409 u8 update_tx_active_flg /* set if tx active flag should be handled */;
1410 u8 tx_active_flg /* tx active flag value */;
1411 u8 update_rx_mode_flg /* set if rx state data should be handled */;
1412 u8 update_tx_mode_flg /* set if tx state data should be handled */;
1413 /* set if approx. mcast data should be handled */
1414 u8 update_approx_mcast_flg;
1415 u8 update_rss_flg /* set if rss data should be handled */;
1416 /* set if inner_vlan_removal_en should be handled */
1417 u8 update_inner_vlan_removal_en_flg;
1418 u8 inner_vlan_removal_en;
1419 /* set if tpa parameters should be handled, TPA must be disable before */
1420 u8 update_tpa_param_flg;
1421 u8 update_tpa_en_flg /* set if tpa enable changes */;
1422 /* set if tx switching en flag should be handled */
1423 u8 update_tx_switching_en_flg;
1424 u8 tx_switching_en /* tx switching en value */;
1425 /* set if anti spoofing flag should be handled */
1426 u8 update_anti_spoofing_en_flg;
1427 u8 anti_spoofing_en /* Anti-spoofing verification en value */;
1428 /* set if handle_ptp_pkts should be handled. */
1429 u8 update_handle_ptp_pkts;
1430 /* If set, the vport handles PTP Timesync Packets */
1432 /* If set, the default Vlan enable flag is updated */
1433 u8 update_default_vlan_en_flg;
1434 /* If set, the default Vlan value is forced by the FW */
1436 /* If set, the default Vlan value is updated */
1437 u8 update_default_vlan_flg;
1438 __le16 default_vlan /* Default Vlan value to be forced by FW */;
1439 /* set if accept_any_vlan should be handled */
1440 u8 update_accept_any_vlan_flg;
1441 u8 accept_any_vlan /* accept_any_vlan updated value */;
1442 /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled
1443 * as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data
1445 u8 silent_vlan_removal_en;
1446 /* If set, MTU will be updated. Vport must be not active. */
1448 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */;
1449 /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be
1452 u8 update_ctl_frame_checks_en_flg;
1453 /* If set, Contorl frames will be filtered according to MAC check. */
1454 u8 ctl_frame_mac_check_en;
1455 /* If set, Contorl frames will be filtered according to ethtype check. */
1456 u8 ctl_frame_ethtype_check_en;
1460 struct vport_update_ramrod_mcast {
1461 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */;
1465 * Ramrod data for vport update ramrod
1467 struct vport_update_ramrod_data {
1468 /* Common data for all vport update ramrods */
1469 struct vport_update_ramrod_data_cmn common;
1470 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */;
1471 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */;
1472 /* TPA configuration parameters */
1473 struct eth_vport_tpa_param tpa_param;
1474 struct vport_update_ramrod_mcast approx_mcast;
1475 struct eth_vport_rss_config rss_config /* rss config data */;
1484 * GFT CAM line struct
1486 struct gft_cam_line {
1488 /* Indication if the line is valid. */
1489 #define GFT_CAM_LINE_VALID_MASK 0x1
1490 #define GFT_CAM_LINE_VALID_SHIFT 0
1491 /* Data bits, the word that compared with the profile key */
1492 #define GFT_CAM_LINE_DATA_MASK 0x3FFF
1493 #define GFT_CAM_LINE_DATA_SHIFT 1
1494 /* Mask bits, indicate the bits in the data that are Dont-Care */
1495 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
1496 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15
1497 #define GFT_CAM_LINE_RESERVED1_MASK 0x7
1498 #define GFT_CAM_LINE_RESERVED1_SHIFT 29
1503 * GFT CAM line struct (for driversim use)
1505 struct gft_cam_line_mapped {
1507 /* Indication if the line is valid. */
1508 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
1509 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
1510 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1511 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
1512 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
1513 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1514 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
1515 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
1516 /* use enum gft_profile_upper_protocol_type
1517 * (use enum gft_profile_upper_protocol_type)
1519 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
1520 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
1521 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
1522 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
1523 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
1524 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
1525 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
1526 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1527 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
1528 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
1529 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1530 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
1531 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
1532 /* use enum gft_profile_upper_protocol_type
1533 * (use enum gft_profile_upper_protocol_type)
1535 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
1536 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
1537 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
1538 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
1539 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
1540 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
1541 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
1542 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
1543 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
1547 union gft_cam_line_union {
1548 struct gft_cam_line cam_line;
1549 struct gft_cam_line_mapped cam_line_mapped;
1554 * Used in gft_profile_key: Indication for ip version
1556 enum gft_profile_ip_version {
1557 GFT_PROFILE_IPV4 = 0,
1558 GFT_PROFILE_IPV6 = 1,
1559 MAX_GFT_PROFILE_IP_VERSION
1564 * Profile key stucr fot GFT logic in Prs
1566 struct gft_profile_key {
1568 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1569 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
1570 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
1571 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */
1572 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
1573 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
1574 /* use enum gft_profile_upper_protocol_type
1575 * (use enum gft_profile_upper_protocol_type)
1577 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
1578 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
1579 /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */
1580 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
1581 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
1582 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
1583 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
1584 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
1585 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
1590 * Used in gft_profile_key: Indication for tunnel type
1592 enum gft_profile_tunnel_type {
1593 GFT_PROFILE_NO_TUNNEL = 0,
1594 GFT_PROFILE_VXLAN_TUNNEL = 1,
1595 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
1596 GFT_PROFILE_GRE_IP_TUNNEL = 3,
1597 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
1598 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
1599 MAX_GFT_PROFILE_TUNNEL_TYPE
1604 * Used in gft_profile_key: Indication for protocol type
1606 enum gft_profile_upper_protocol_type {
1607 GFT_PROFILE_ROCE_PROTOCOL = 0,
1608 GFT_PROFILE_RROCE_PROTOCOL = 1,
1609 GFT_PROFILE_FCOE_PROTOCOL = 2,
1610 GFT_PROFILE_ICMP_PROTOCOL = 3,
1611 GFT_PROFILE_ARP_PROTOCOL = 4,
1612 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
1613 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
1614 GFT_PROFILE_TCP_PROTOCOL = 7,
1615 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
1616 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
1617 GFT_PROFILE_UDP_PROTOCOL = 10,
1618 GFT_PROFILE_USER_IP_1_INNER = 11,
1619 GFT_PROFILE_USER_IP_2_OUTER = 12,
1620 GFT_PROFILE_USER_ETH_1_INNER = 13,
1621 GFT_PROFILE_USER_ETH_2_OUTER = 14,
1622 GFT_PROFILE_RAW = 15,
1623 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
1628 * GFT RAM line struct
1630 struct gft_ram_line {
1632 /* (use enum gft_vlan_select) */
1633 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
1634 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
1635 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
1636 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
1637 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
1638 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
1639 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
1640 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
1641 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
1642 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
1643 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
1644 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
1645 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
1646 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
1647 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
1648 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
1649 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
1650 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
1651 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
1652 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
1653 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
1654 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
1655 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
1656 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
1657 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
1658 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
1659 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
1660 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
1661 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
1662 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
1663 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
1664 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
1665 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
1666 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
1667 #define GFT_RAM_LINE_TTL_MASK 0x1
1668 #define GFT_RAM_LINE_TTL_SHIFT 18
1669 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
1670 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
1671 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
1672 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
1673 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
1674 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
1675 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
1676 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
1677 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
1678 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
1679 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
1680 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
1681 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
1682 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
1683 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
1684 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
1685 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
1686 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
1687 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
1688 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
1689 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
1690 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
1691 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
1692 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
1693 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
1694 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
1696 #define GFT_RAM_LINE_DSCP_MASK 0x1
1697 #define GFT_RAM_LINE_DSCP_SHIFT 0
1698 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
1699 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
1700 #define GFT_RAM_LINE_DST_IP_MASK 0x1
1701 #define GFT_RAM_LINE_DST_IP_SHIFT 2
1702 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
1703 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
1704 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
1705 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
1706 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
1707 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
1708 #define GFT_RAM_LINE_VLAN_MASK 0x1
1709 #define GFT_RAM_LINE_VLAN_SHIFT 6
1710 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
1711 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
1712 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
1713 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
1714 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
1715 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
1716 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
1717 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
1722 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask
1724 enum gft_vlan_select {
1725 INNER_PROVIDER_VLAN = 0,
1727 OUTER_PROVIDER_VLAN = 2,
1733 struct mstorm_eth_conn_ag_ctx {
1734 u8 byte0 /* cdu_validation */;
1735 u8 byte1 /* state */;
1738 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
1739 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
1741 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
1742 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
1743 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1744 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
1745 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1746 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
1747 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1748 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
1750 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1751 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
1752 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1753 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
1754 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1755 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
1756 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1757 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
1758 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1759 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
1760 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1761 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
1762 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1763 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
1764 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1765 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
1766 __le16 word0 /* word0 */;
1767 __le16 word1 /* word1 */;
1768 __le32 reg0 /* reg0 */;
1769 __le32 reg1 /* reg1 */;
1775 struct xstormEthConnAgCtxDqExtLdPart {
1776 u8 reserved0 /* cdu_validation */;
1777 u8 eth_state /* state */;
1780 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
1781 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
1783 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
1784 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
1786 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
1787 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
1789 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
1790 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
1792 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
1793 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
1794 /* cf_array_active */
1795 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
1796 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
1798 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
1799 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
1801 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
1802 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
1805 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
1806 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
1808 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
1809 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
1811 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
1812 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
1814 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
1815 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
1817 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
1818 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
1820 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
1821 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
1823 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
1824 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
1826 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
1827 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
1830 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
1831 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
1833 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
1834 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
1836 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
1837 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
1838 /* timer_stop_all */
1839 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
1840 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
1843 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
1844 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
1846 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
1847 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
1849 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
1850 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
1852 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
1853 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
1856 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
1857 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
1859 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
1860 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
1862 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
1863 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
1865 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
1866 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
1869 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
1870 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
1872 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
1873 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
1875 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
1876 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
1878 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
1879 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
1882 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
1883 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
1885 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
1886 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
1888 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
1889 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
1891 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
1892 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
1895 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
1896 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
1898 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
1899 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
1901 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
1902 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
1904 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
1905 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
1907 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
1908 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
1911 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
1912 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
1914 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
1915 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
1917 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
1918 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
1920 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
1921 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
1923 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
1924 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
1926 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
1927 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
1929 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
1930 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
1932 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
1933 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
1936 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
1937 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
1939 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
1940 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
1942 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
1943 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
1945 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
1946 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
1948 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
1949 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
1951 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
1952 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
1954 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
1955 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
1956 /* cf_array_cf_en */
1957 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
1958 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
1961 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
1962 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
1964 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
1965 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
1967 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
1968 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
1970 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
1971 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
1973 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
1974 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
1976 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
1977 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
1979 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
1980 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
1982 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
1983 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
1986 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
1987 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
1989 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
1990 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
1992 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
1993 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
1995 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
1996 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
1998 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
1999 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
2001 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
2002 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
2004 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
2005 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
2007 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
2008 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
2011 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
2012 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
2014 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
2015 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
2017 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
2018 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
2020 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
2021 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
2023 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
2024 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
2026 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
2027 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
2029 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
2030 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
2032 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
2033 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
2036 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
2037 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
2039 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
2040 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
2042 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
2043 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
2045 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
2046 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
2048 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
2049 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
2051 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
2052 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
2054 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
2055 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
2057 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
2058 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
2061 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
2062 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
2064 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
2065 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
2067 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
2068 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
2070 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
2071 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2073 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
2074 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
2076 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
2077 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
2079 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
2080 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
2081 u8 edpm_event_id /* byte2 */;
2082 __le16 physical_q0 /* physical_q0 */;
2083 __le16 quota /* physical_q1 */;
2084 __le16 edpm_num_bds /* physical_q2 */;
2085 __le16 tx_bd_cons /* word3 */;
2086 __le16 tx_bd_prod /* word4 */;
2087 __le16 tx_class /* word5 */;
2088 __le16 conn_dpi /* conn_dpi */;
2089 u8 byte3 /* byte3 */;
2090 u8 byte4 /* byte4 */;
2091 u8 byte5 /* byte5 */;
2092 u8 byte6 /* byte6 */;
2093 __le32 reg0 /* reg0 */;
2094 __le32 reg1 /* reg1 */;
2095 __le32 reg2 /* reg2 */;
2096 __le32 reg3 /* reg3 */;
2097 __le32 reg4 /* reg4 */;
2102 struct xstorm_eth_hw_conn_ag_ctx {
2103 u8 reserved0 /* cdu_validation */;
2104 u8 eth_state /* state */;
2107 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
2108 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2110 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
2111 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
2113 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
2114 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
2116 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
2117 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2119 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
2120 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
2121 /* cf_array_active */
2122 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
2123 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
2125 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
2126 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
2128 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
2129 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
2132 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
2133 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
2135 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
2136 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
2138 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
2139 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
2141 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
2142 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
2144 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
2145 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
2147 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
2148 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
2150 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
2151 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
2153 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
2154 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
2157 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
2158 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
2160 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
2161 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
2163 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
2164 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
2165 /* timer_stop_all */
2166 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
2167 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
2170 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
2171 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
2173 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
2174 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
2176 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
2177 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
2179 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
2180 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
2183 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
2184 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
2186 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
2187 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
2189 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
2190 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
2192 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
2193 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
2196 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
2197 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
2199 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
2200 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
2202 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
2203 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
2205 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
2206 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
2209 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
2210 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
2212 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
2213 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
2215 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
2216 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
2218 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
2219 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
2222 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
2223 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
2225 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
2226 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
2228 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
2229 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2231 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
2232 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
2234 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
2235 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
2238 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
2239 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
2241 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
2242 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
2244 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
2245 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
2247 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
2248 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
2250 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
2251 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
2253 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
2254 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
2256 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
2257 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
2259 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
2260 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
2263 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
2264 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
2266 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
2267 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
2269 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
2270 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
2272 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
2273 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
2275 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
2276 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
2278 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
2279 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
2281 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
2282 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2283 /* cf_array_cf_en */
2284 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2285 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2288 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
2289 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2291 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
2292 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2294 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
2295 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2297 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
2298 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
2300 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
2301 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2303 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
2304 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2306 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
2307 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
2309 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
2310 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
2313 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
2314 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
2316 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
2317 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
2319 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
2320 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2322 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
2323 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
2325 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
2326 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
2328 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
2329 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
2331 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
2332 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2334 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
2335 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
2338 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
2339 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
2341 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
2342 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
2344 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
2345 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2347 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
2348 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2350 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
2351 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
2353 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
2354 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
2356 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
2357 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
2359 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
2360 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
2363 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
2364 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
2366 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
2367 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
2369 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
2370 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2372 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
2373 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2375 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
2376 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2378 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
2379 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2381 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
2382 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2384 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
2385 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2388 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
2389 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2391 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
2392 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2394 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
2395 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2397 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
2398 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2400 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
2401 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2403 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
2404 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2406 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
2407 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2408 u8 edpm_event_id /* byte2 */;
2409 __le16 physical_q0 /* physical_q0 */;
2410 __le16 quota /* physical_q1 */;
2411 __le16 edpm_num_bds /* physical_q2 */;
2412 __le16 tx_bd_cons /* word3 */;
2413 __le16 tx_bd_prod /* word4 */;
2414 __le16 tx_class /* word5 */;
2415 __le16 conn_dpi /* conn_dpi */;
2419 #endif /* __ECORE_HSI_ETH__ */