2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_HSI_INIT_TOOL__
10 #define __ECORE_HSI_INIT_TOOL__
11 /**************************************/
12 /* Init Tool HSI constants and macros */
13 /**************************************/
15 /* Width of GRC address in bits (addresses are specified in dwords) */
16 #define GRC_ADDR_BITS 23
17 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
19 /* indicates an init that should be applied to any phase ID */
20 #define ANY_PHASE_ID 0xffff
22 /* Max size in dwords of a zipped array */
23 #define MAX_ZIPPED_SIZE 8192
34 * Binary buffer header
36 struct bin_buffer_hdr {
37 /* buffer offset in bytes from the beginning of the binary file */
39 u32 length /* buffer length in bytes */;
44 * binary init buffer types
46 enum bin_init_buffer_type {
47 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
48 BIN_BUF_INIT_CMD /* init commands */,
49 BIN_BUF_INIT_VAL /* init data */,
50 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
51 BIN_BUF_INIT_IRO /* internal RAM offsets */,
52 MAX_BIN_INIT_BUFFER_TYPE
57 * init array header: raw
59 struct init_array_raw_hdr {
61 /* Init array type, from init_array_types enum */
62 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
63 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
64 /* init array params */
65 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
66 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
70 * init array header: standard
72 struct init_array_standard_hdr {
74 /* Init array type, from init_array_types enum */
75 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
76 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
77 /* Init array size (in dwords) */
78 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
79 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
83 * init array header: zipped
85 struct init_array_zipped_hdr {
87 /* Init array type, from init_array_types enum */
88 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
89 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
90 /* Init array zipped size (in bytes) */
91 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
92 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
96 * init array header: pattern
98 struct init_array_pattern_hdr {
100 /* Init array type, from init_array_types enum */
101 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
102 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
103 /* pattern size in dword */
104 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
105 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
106 /* pattern repetitions */
107 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
108 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
112 * init array header union
114 union init_array_hdr {
115 struct init_array_raw_hdr raw /* raw init array header */;
116 /* standard init array header */
117 struct init_array_standard_hdr standard;
118 struct init_array_zipped_hdr zipped /* zipped init array header */;
119 struct init_array_pattern_hdr pattern /* pattern init array header */;
124 MODE_BB_A0_DEPRECATED,
135 MODE_PORTS_PER_ENG_1,
136 MODE_PORTS_PER_ENG_2,
137 MODE_PORTS_PER_ENG_4,
154 enum init_split_types {
167 enum init_array_types {
168 INIT_ARR_STANDARD /* standard init array */,
169 INIT_ARR_ZIPPED /* zipped init array */,
170 INIT_ARR_PATTERN /* a repeated pattern */,
177 * init operation: callback
179 struct init_callback_op {
181 /* Init operation, from init_op_types enum */
182 #define INIT_CALLBACK_OP_OP_MASK 0xF
183 #define INIT_CALLBACK_OP_OP_SHIFT 0
184 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
185 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
186 u16 callback_id /* Callback ID */;
187 u16 block_id /* Blocks ID */;
192 * init operation: delay
194 struct init_delay_op {
196 /* Init operation, from init_op_types enum */
197 #define INIT_DELAY_OP_OP_MASK 0xF
198 #define INIT_DELAY_OP_OP_SHIFT 0
199 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
200 #define INIT_DELAY_OP_RESERVED_SHIFT 4
201 __le32 delay /* delay in us */;
206 * init operation: if_mode
208 struct init_if_mode_op {
210 /* Init operation, from init_op_types enum */
211 #define INIT_IF_MODE_OP_OP_MASK 0xF
212 #define INIT_IF_MODE_OP_OP_SHIFT 0
213 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
214 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
215 /* Commands to skip if the modes dont match */
216 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
217 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
219 u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */;
224 * init operation: if_phase
226 struct init_if_phase_op {
228 /* Init operation, from init_op_types enum */
229 #define INIT_IF_PHASE_OP_OP_MASK 0xF
230 #define INIT_IF_PHASE_OP_OP_SHIFT 0
231 /* Indicates if DMAE is enabled in this phase */
232 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
233 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
234 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
235 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
236 /* Commands to skip if the phases dont match */
237 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
238 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
240 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
241 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
242 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
243 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
244 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
245 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
250 * init mode operators
253 INIT_MODE_OP_NOT /* init mode not operator */,
254 INIT_MODE_OP_OR /* init mode or operator */,
255 INIT_MODE_OP_AND /* init mode and operator */,
261 * init operation: raw
265 /* Init operation, from init_op_types enum */
266 #define INIT_RAW_OP_OP_MASK 0xF
267 #define INIT_RAW_OP_OP_SHIFT 0
268 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
269 #define INIT_RAW_OP_PARAM1_SHIFT 4
270 u32 param2 /* Init param 2 */;
276 struct init_op_array_params {
277 u16 size /* array size in dwords */;
278 u16 offset /* array start offset in dwords */;
282 * Write init operation arguments
284 union init_write_args {
285 /* value to write, used when init source is INIT_SRC_INLINE */
287 /* number of zeros to write, used when init source is INIT_SRC_ZEROS */
289 /* array offset to write, used when init source is INIT_SRC_ARRAY */
291 /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */
292 struct init_op_array_params runtime;
296 * init operation: write
298 struct init_write_op {
300 /* init operation, from init_op_types enum */
301 #define INIT_WRITE_OP_OP_MASK 0xF
302 #define INIT_WRITE_OP_OP_SHIFT 0
303 /* init source type, taken from init_source_types enum */
304 #define INIT_WRITE_OP_SOURCE_MASK 0x7
305 #define INIT_WRITE_OP_SOURCE_SHIFT 4
306 #define INIT_WRITE_OP_RESERVED_MASK 0x1
307 #define INIT_WRITE_OP_RESERVED_SHIFT 7
308 /* indicates if the register is wide-bus */
309 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
310 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
311 /* internal (absolute) GRC address, in dwords */
312 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
313 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
314 union init_write_args args /* Write init operation arguments */;
318 * init operation: read
320 struct init_read_op {
322 /* init operation, from init_op_types enum */
323 #define INIT_READ_OP_OP_MASK 0xF
324 #define INIT_READ_OP_OP_SHIFT 0
325 /* polling type, from init_poll_types enum */
326 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
327 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
328 #define INIT_READ_OP_RESERVED_MASK 0x1
329 #define INIT_READ_OP_RESERVED_SHIFT 8
330 /* internal (absolute) GRC address, in dwords */
331 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
332 #define INIT_READ_OP_ADDRESS_SHIFT 9
333 /* expected polling value, used only when polling is done */
338 * Init operations union
341 struct init_raw_op raw /* raw init operation */;
342 struct init_write_op write /* write init operation */;
343 struct init_read_op read /* read init operation */;
344 struct init_if_mode_op if_mode /* if_mode init operation */;
345 struct init_if_phase_op if_phase /* if_phase init operation */;
346 struct init_callback_op callback /* callback init operation */;
347 struct init_delay_op delay /* delay init operation */;
353 * Init command operation types
356 INIT_OP_READ /* GRC read init command */,
357 INIT_OP_WRITE /* GRC write init command */,
358 /* Skip init commands if the init modes expression doesn't match */
360 /* Skip init commands if the init phase doesn't match */
362 INIT_OP_DELAY /* delay init command */,
363 INIT_OP_CALLBACK /* callback init command */,
371 enum init_poll_types {
372 INIT_POLL_NONE /* No polling */,
373 INIT_POLL_EQ /* init value is included in the init command */,
374 INIT_POLL_OR /* init value is all zeros */,
375 INIT_POLL_AND /* init value is an array of values */,
385 enum init_source_types {
386 INIT_SRC_INLINE /* init value is included in the init command */,
387 INIT_SRC_ZEROS /* init value is all zeros */,
388 INIT_SRC_ARRAY /* init value is an array of values */,
389 INIT_SRC_RUNTIME /* init value is provided during runtime */,
390 MAX_INIT_SOURCE_TYPES
397 * Internal RAM Offsets macro data
400 u32 base /* RAM field offset */;
401 u16 m1 /* multiplier 1 */;
402 u16 m2 /* multiplier 2 */;
403 u16 m3 /* multiplier 3 */;
404 u16 size /* RAM field size */;
407 #endif /* __ECORE_HSI_INIT_TOOL__ */