1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef _ECORE_IGU_DEF_H_
8 #define _ECORE_IGU_DEF_H_
10 /* Fields of IGU PF CONFIGRATION REGISTER */
12 #define IGU_PF_CONF_FUNC_EN (0x1 << 0)
14 #define IGU_PF_CONF_MSI_MSIX_EN (0x1 << 1)
16 #define IGU_PF_CONF_INT_LINE_EN (0x1 << 2)
17 /* attention enable */
18 #define IGU_PF_CONF_ATTN_BIT_EN (0x1 << 3)
19 /* single ISR mode enable */
20 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)
21 /* simd all ones mode */
22 #define IGU_PF_CONF_SIMD_MODE (0x1 << 5)
24 /* Fields of IGU VF CONFIGRATION REGISTER */
26 #define IGU_VF_CONF_FUNC_EN (0x1 << 0)
28 #define IGU_VF_CONF_MSI_MSIX_EN (0x1 << 1)
29 /* single ISR mode enable */
30 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1 << 4)
32 #define IGU_VF_CONF_PARENT_MASK (0xF)
34 #define IGU_VF_CONF_PARENT_SHIFT 5
36 /* Igu control commands
44 /* Control register for the IGU command register
48 #define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */
49 #define IGU_CTRL_REG_FID_SHIFT 0
50 #define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */
51 #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16
52 #define IGU_CTRL_REG_RESERVED_MASK 0x1
53 #define IGU_CTRL_REG_RESERVED_SHIFT 28
54 #define IGU_CTRL_REG_TYPE_MASK 0x1U /* use enum igu_ctrl_cmd */
55 #define IGU_CTRL_REG_TYPE_SHIFT 31