1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
9 #include "ecore_init_ops.h"
11 #include "ecore_rt_defs.h"
12 #include "ecore_hsi_init_func.h"
13 #include "ecore_hsi_init_tool.h"
14 #include "ecore_iro.h"
15 #include "ecore_init_fw_funcs.h"
16 static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = {
17 { 400, 336, 352, 368, 304, 384, 416, 352}, /* region 3 offsets */
18 { 528, 496, 416, 512, 448, 512, 544, 480}, /* region 4 offsets */
19 { 608, 544, 496, 576, 576, 592, 624, 560} /* region 5 offsets */
21 static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = {
22 { 240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
25 /* General constants */
26 #define QM_PQ_MEM_4KB(pq_size) \
27 (pq_size ? DIV_ROUND_UP((pq_size + 1) * QM_PQ_ELEMENT_SIZE, 0x1000) : 0)
28 #define QM_PQ_SIZE_256B(pq_size) \
29 (pq_size ? DIV_ROUND_UP(pq_size, 0x100) - 1 : 0)
30 #define QM_INVALID_PQ_ID 0xffff
32 /* Max link speed (in Mbps) */
33 #define QM_MAX_LINK_SPEED 100000
36 #define QM_BYPASS_EN 1
37 #define QM_BYTE_CRD_EN 1
39 /* Other PQ constants */
40 #define QM_OTHER_PQS_PER_PF 4
43 #define MAX_NUM_VOQS (MAX_NUM_PORTS_K2 * NUM_TCS_4PORT_K2)
44 #define VOQS_BIT_MASK ((1 << MAX_NUM_VOQS) - 1)
48 /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
49 #define QM_WFQ_UPPER_BOUND 62500000
51 /* Bit of VOQ in WFQ VP PQ map */
52 #define QM_WFQ_VP_PQ_VOQ_SHIFT 0
54 /* Bit of PF in WFQ VP PQ map */
55 #define QM_WFQ_VP_PQ_PF_SHIFT 5
57 /* 0x9000 = 4*9*1024 */
58 #define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
60 /* Max WFQ increment value is 0.7 * upper bound */
61 #define QM_WFQ_MAX_INC_VAL ((QM_WFQ_UPPER_BOUND * 7) / 10)
66 #define QM_RL_PERIOD 5
68 /* Period in 25MHz cycles */
69 #define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
71 /* RL increment value - rate is specified in mbps. the factor of 1.01 was
72 * added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC
73 * 2544 test. In this scenario the PF RL was reducing the line rate to 99%
74 * although the credit increment value was the correct one and FW calculated
75 * correct packet sizes. The reason for the inaccuracy of the RL is unknown at
78 #define QM_RL_INC_VAL(rate) \
79 OSAL_MAX_T(u32, (u32)(((rate ? rate : 100000) * QM_RL_PERIOD * 101) / \
82 /* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
83 #define QM_PF_RL_UPPER_BOUND 62500000
85 /* Max PF RL increment value is 0.7 * upper bound */
86 #define QM_PF_RL_MAX_INC_VAL ((QM_PF_RL_UPPER_BOUND * 7) / 10)
88 /* Vport RL Upper bound, link speed is in Mpbs */
89 #define QM_VP_RL_UPPER_BOUND(speed) \
90 ((u32)OSAL_MAX_T(u32, QM_RL_INC_VAL(speed), 9700 + 1000))
92 /* Max Vport RL increment value is the Vport RL upper bound */
93 #define QM_VP_RL_MAX_INC_VAL(speed) QM_VP_RL_UPPER_BOUND(speed)
95 /* Vport RL credit threshold in case of QM bypass */
96 #define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1)
98 /* AFullOprtnstcCrdMask constants */
99 #define QM_OPPOR_LINE_VOQ_DEF 1
100 #define QM_OPPOR_FW_STOP_DEF 0
101 #define QM_OPPOR_PQ_EMPTY_DEF 1
103 /* Command Queue constants: */
105 /* Pure LB CmdQ lines (+spare) */
106 #define PBF_CMDQ_PURE_LB_LINES 150
108 #define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
109 (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
111 (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
112 PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
114 #define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
115 (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
117 (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
118 PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
120 #define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
121 ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
123 /* BTB: blocks constants (block size = 256B) */
125 /* 256B blocks in 9700B packet */
126 #define BTB_JUMBO_PKT_BLOCKS 38
128 /* Headroom per-port */
129 #define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
130 #define BTB_PURE_LB_FACTOR 10
132 /* Factored (hence really 0.7) */
133 #define BTB_PURE_LB_RATIO 7
135 /* QM stop command constants */
136 #define QM_STOP_PQ_MASK_WIDTH 32
137 #define QM_STOP_CMD_ADDR 2
138 #define QM_STOP_CMD_STRUCT_SIZE 2
139 #define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
140 #define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
141 #define QM_STOP_CMD_PAUSE_MASK_MASK 0xffffffff /* @DPDK */
142 #define QM_STOP_CMD_GROUP_ID_OFFSET 1
143 #define QM_STOP_CMD_GROUP_ID_SHIFT 16
144 #define QM_STOP_CMD_GROUP_ID_MASK 15
145 #define QM_STOP_CMD_PQ_TYPE_OFFSET 1
146 #define QM_STOP_CMD_PQ_TYPE_SHIFT 24
147 #define QM_STOP_CMD_PQ_TYPE_MASK 1
148 #define QM_STOP_CMD_MAX_POLL_COUNT 100
149 #define QM_STOP_CMD_POLL_PERIOD_US 500
151 /* QM command macros */
152 #define QM_CMD_STRUCT_SIZE(cmd) cmd##_STRUCT_SIZE
153 #define QM_CMD_SET_FIELD(var, cmd, field, value) \
154 SET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value)
156 #define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, \
157 rl_valid, rl_id, voq, wrr) \
159 OSAL_MEMSET(&(map), 0, sizeof(map)); \
160 SET_FIELD(map.reg, QM_RF_PQ_MAP_PQ_VALID, 1); \
161 SET_FIELD(map.reg, QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0); \
162 SET_FIELD(map.reg, QM_RF_PQ_MAP_RL_ID, rl_id); \
163 SET_FIELD(map.reg, QM_RF_PQ_MAP_VP_PQ_ID, vp_pq_id); \
164 SET_FIELD(map.reg, QM_RF_PQ_MAP_VOQ, voq); \
165 SET_FIELD(map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, wrr); \
166 STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \
170 #define WRITE_PQ_INFO_TO_RAM 1
172 #define PQ_INFO_ELEMENT(vp_pq_id, pf, tc, port, rl_valid, rl_id) \
173 (((vp_pq_id) << 0) | ((pf) << 12) | ((tc) << 16) | ((port) << 20) | \
174 ((rl_valid ? 1 : 0) << 22) | (((rl_id) & 255) << 24) | \
175 (((rl_id) >> 8) << 9))
177 #define PQ_INFO_RAM_GRC_ADDRESS(pq_id) (XSEM_REG_FAST_MEMORY + \
178 SEM_FAST_REG_INT_RAM + XSTORM_PQ_INFO_OFFSET(pq_id))
180 /******************** INTERNAL IMPLEMENTATION *********************/
182 /* Prepare PF RL enable/disable runtime init values */
183 static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn, bool pf_rl_en)
185 STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
187 /* Enable RLs for all VOQs */
188 STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET,
191 /* Write RL period */
192 STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIOD_RT_OFFSET,
193 QM_RL_PERIOD_CLK_25M);
194 STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIODTIMER_RT_OFFSET,
195 QM_RL_PERIOD_CLK_25M);
197 /* Set credit threshold for QM bypass flow */
199 STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
200 QM_PF_RL_UPPER_BOUND);
204 /* Prepare PF WFQ enable/disable runtime init values */
205 static void ecore_enable_pf_wfq(struct ecore_hwfn *p_hwfn, bool pf_wfq_en)
207 STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
209 /* Set credit threshold for QM bypass flow */
210 if (pf_wfq_en && QM_BYPASS_EN)
211 STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET,
215 /* Prepare global RL enable/disable runtime init values */
216 static void ecore_enable_global_rl(struct ecore_hwfn *p_hwfn,
219 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET,
220 global_rl_en ? 1 : 0);
222 /* Write RL period (use timer 0 only) */
223 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIOD_0_RT_OFFSET,
224 QM_RL_PERIOD_CLK_25M);
225 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET,
226 QM_RL_PERIOD_CLK_25M);
228 /* Set credit threshold for QM bypass flow */
231 QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
232 QM_VP_RL_BYPASS_THRESH_SPEED);
236 /* Prepare VPORT WFQ enable/disable runtime init values */
237 static void ecore_enable_vport_wfq(struct ecore_hwfn *p_hwfn, bool vport_wfq_en)
239 STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET,
240 vport_wfq_en ? 1 : 0);
242 /* Set credit threshold for QM bypass flow */
243 if (vport_wfq_en && QM_BYPASS_EN)
244 STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET,
248 /* Prepare runtime init values to allocate PBF command queue lines for
251 static void ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn *p_hwfn,
255 u32 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
257 OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq),
259 STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + voq, qm_line_crd);
260 STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + voq,
264 /* Prepare runtime init values to allocate PBF command queue lines. */
265 static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
266 u8 max_ports_per_engine,
267 u8 max_phys_tcs_per_port,
268 struct init_qm_port_params
269 port_params[MAX_NUM_PORTS])
271 u8 tc, voq, port_id, num_tcs_in_port;
273 /* Clear PBF lines of all VOQs */
274 for (voq = 0; voq < MAX_NUM_VOQS; voq++)
275 STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
277 for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
278 u16 phys_lines, phys_lines_per_tc;
280 if (!port_params[port_id].active)
283 /* Find number of command queue lines to divide between the
284 * active physical TCs.
286 phys_lines = port_params[port_id].num_pbf_cmd_lines;
287 phys_lines -= PBF_CMDQ_PURE_LB_LINES;
289 /* Find #lines per active physical TC */
291 for (tc = 0; tc < max_phys_tcs_per_port; tc++)
292 if (((port_params[port_id].active_phys_tcs >> tc) &
295 phys_lines_per_tc = phys_lines / num_tcs_in_port;
297 /* Init registers per active TC */
298 for (tc = 0; tc < max_phys_tcs_per_port; tc++) {
299 voq = VOQ(port_id, tc, max_phys_tcs_per_port);
300 if (((port_params[port_id].active_phys_tcs >>
302 ecore_cmdq_lines_voq_rt_init(p_hwfn, voq,
306 /* Init registers for pure LB TC */
307 voq = VOQ(port_id, PURE_LB_TC, max_phys_tcs_per_port);
308 ecore_cmdq_lines_voq_rt_init(p_hwfn, voq,
309 PBF_CMDQ_PURE_LB_LINES);
314 * Prepare runtime init values to allocate guaranteed BTB blocks for the
315 * specified port. The guaranteed BTB space is divided between the TCs as
316 * follows (shared space Is currently not used):
318 * B BTB blocks for this port
319 * C Number of physical TCs for this port
321 * a. 38 blocks (9700B jumbo frame) are allocated for global per port
323 * b. B = B 38 (remainder after global headroom allocation)
324 * c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ.
325 * d. B = B MAX(38, B/(C+0.7)) (remainder after pure LB allocation).
326 * e. B/C blocks are allocated for each physical TC.
328 * - MTU is up to 9700 bytes (38 blocks)
329 * - All TCs are considered symmetrical (same rate and packet size)
330 * - No optimization for lossy TC (all are considered lossless). Shared space is
331 * not enabled and allocated for each TC.
333 static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
334 u8 max_ports_per_engine,
335 u8 max_phys_tcs_per_port,
336 struct init_qm_port_params
337 port_params[MAX_NUM_PORTS])
339 u32 usable_blocks, pure_lb_blocks, phys_blocks;
340 u8 tc, voq, port_id, num_tcs_in_port;
342 for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
343 if (!port_params[port_id].active)
346 /* Subtract headroom blocks */
347 usable_blocks = port_params[port_id].num_btb_blocks -
350 /* Find blocks per physical TC. use factor to avoid floating
354 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
355 if (((port_params[port_id].active_phys_tcs >> tc) &
359 pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) /
360 (num_tcs_in_port * BTB_PURE_LB_FACTOR +
362 pure_lb_blocks = OSAL_MAX_T(u32, BTB_JUMBO_PKT_BLOCKS,
365 phys_blocks = (usable_blocks - pure_lb_blocks) /
368 /* Init physical TCs */
369 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
370 if (((port_params[port_id].active_phys_tcs >> tc) &
372 voq = VOQ(port_id, tc, max_phys_tcs_per_port);
374 PBF_BTB_GUARANTEED_RT_OFFSET(voq),
379 /* Init pure LB TC */
380 voq = VOQ(port_id, PURE_LB_TC, max_phys_tcs_per_port);
381 STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(voq),
386 /* Prepare runtime init values for the specified RL.
387 * If global_rl_params is OSAL_NULL, max link speed (100Gbps) is used instead.
388 * Return -1 on error.
390 static int ecore_global_rl_rt_init(struct ecore_hwfn *p_hwfn,
391 struct init_qm_global_rl_params
392 global_rl_params[COMMON_MAX_QM_GLOBAL_RLS])
394 u32 upper_bound = QM_VP_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) |
395 (u32)QM_RL_CRD_REG_SIGN_BIT;
399 /* Go over all global RLs */
400 for (rl_id = 0; rl_id < MAX_QM_GLOBAL_RLS; rl_id++) {
401 u32 rate_limit = global_rl_params ?
402 global_rl_params[rl_id].rate_limit : 0;
404 inc_val = QM_RL_INC_VAL(rate_limit ?
405 rate_limit : QM_MAX_LINK_SPEED);
406 if (inc_val > QM_VP_RL_MAX_INC_VAL(QM_MAX_LINK_SPEED)) {
407 DP_NOTICE(p_hwfn, true, "Invalid rate limit configuration.\n");
411 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + rl_id,
412 (u32)QM_RL_CRD_REG_SIGN_BIT);
413 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + rl_id,
415 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + rl_id,
422 /* Prepare Tx PQ mapping runtime init values for the specified PF */
423 static int ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
424 struct ecore_ptt *p_ptt,
426 u8 max_phys_tcs_per_port,
434 u32 base_mem_addr_4kb,
435 struct init_qm_pq_params *pq_params,
436 struct init_qm_vport_params *vport_params)
438 /* A bit per Tx PQ indicating if the PQ is associated with a VF */
439 u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
440 u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
441 u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group;
442 u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
443 #if (WRITE_PQ_INFO_TO_RAM != 0)
447 num_pqs = num_pf_pqs + num_vf_pqs;
449 first_pq_group = start_pq / QM_PF_QUEUE_GROUP_SIZE;
450 last_pq_group = (start_pq + num_pqs - 1) / QM_PF_QUEUE_GROUP_SIZE;
452 pq_mem_4kb = QM_PQ_MEM_4KB(num_pf_cids);
453 vport_pq_mem_4kb = QM_PQ_MEM_4KB(num_vf_cids);
454 mem_addr_4kb = base_mem_addr_4kb;
456 /* Set mapping from PQ group to PF */
457 for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
458 STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group,
462 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET,
463 QM_PQ_SIZE_256B(num_pf_cids));
464 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET,
465 QM_PQ_SIZE_256B(num_vf_cids));
467 /* Go over all Tx PQs */
468 for (i = 0, pq_id = start_pq; i < num_pqs; i++, pq_id++) {
469 u16 first_tx_pq_id, vport_id_in_pf;
470 struct qm_rf_pq_map tx_pq_map;
474 voq = VOQ(pq_params[i].port_id, pq_params[i].tc_id,
475 max_phys_tcs_per_port);
476 is_vf_pq = (i >= num_pf_pqs);
478 /* Update first Tx PQ of VPORT/TC */
479 vport_id_in_pf = pq_params[i].vport_id - start_vport;
481 vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id];
482 if (first_tx_pq_id == QM_INVALID_PQ_ID) {
483 u32 map_val = (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
484 (pf_id << QM_WFQ_VP_PQ_PF_SHIFT);
486 /* Create new VP PQ */
487 vport_params[vport_id_in_pf].
488 first_tx_pq_id[pq_params[i].tc_id] = pq_id;
489 first_tx_pq_id = pq_id;
491 /* Map VP PQ to VOQ and PF */
492 STORE_RT_REG(p_hwfn, QM_REG_WFQVPMAP_RT_OFFSET +
493 first_tx_pq_id, map_val);
496 /* Prepare PQ map entry */
497 QM_INIT_TX_PQ_MAP(p_hwfn, tx_pq_map, pq_id, first_tx_pq_id,
498 pq_params[i].rl_valid, pq_params[i].rl_id,
499 voq, pq_params[i].wrr_group);
501 /* Set PQ base address */
502 STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
505 /* Clear PQ pointer table entry (64 bit) */
507 for (j = 0; j < 2; j++)
508 STORE_RT_REG(p_hwfn, QM_REG_PTRTBLTX_RT_OFFSET +
511 /* Write PQ info to RAM */
512 #if (WRITE_PQ_INFO_TO_RAM != 0)
513 pq_info = PQ_INFO_ELEMENT(first_tx_pq_id, pf_id,
515 pq_params[i].port_id,
516 pq_params[i].rl_valid,
518 ecore_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id),
522 /* If VF PQ, add indication to PQ VF mask */
524 tx_pq_vf_mask[pq_id / QM_PF_QUEUE_GROUP_SIZE] |=
525 (1 << (pq_id % QM_PF_QUEUE_GROUP_SIZE));
526 mem_addr_4kb += vport_pq_mem_4kb;
528 mem_addr_4kb += pq_mem_4kb;
532 /* Store Tx PQ VF mask to size select register */
533 for (i = 0; i < num_tx_pq_vf_masks; i++)
534 if (tx_pq_vf_mask[i])
535 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET +
536 i, tx_pq_vf_mask[i]);
541 /* Prepare Other PQ mapping runtime init values for the specified PF */
542 static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
547 u32 base_mem_addr_4kb)
549 u32 pq_size, pq_mem_4kb, mem_addr_4kb;
550 u16 i, j, pq_id, pq_group;
552 /* A single other PQ group is used in each PF, where PQ group i is used
556 pq_size = num_pf_cids + num_tids;
557 pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
558 mem_addr_4kb = base_mem_addr_4kb;
560 /* Map PQ group to PF */
561 STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group,
565 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET,
566 QM_PQ_SIZE_256B(pq_size));
568 for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE;
569 i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
570 /* Set PQ base address */
571 STORE_RT_REG(p_hwfn, QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id,
574 /* Clear PQ pointer table entry */
576 for (j = 0; j < 2; j++)
578 QM_REG_PTRTBLOTHER_RT_OFFSET +
581 mem_addr_4kb += pq_mem_4kb;
585 /* Prepare PF WFQ runtime init values for the specified PF.
586 * Return -1 on error.
588 static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
591 u8 max_phys_tcs_per_port,
593 struct init_qm_pq_params *pq_params)
595 u32 inc_val, crd_reg_offset;
599 inc_val = QM_WFQ_INC_VAL(pf_wfq);
600 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
601 DP_NOTICE(p_hwfn, true,
602 "Invalid PF WFQ weight configuration\n");
606 for (i = 0; i < num_tx_pqs; i++) {
607 voq = VOQ(pq_params[i].port_id, pq_params[i].tc_id,
608 max_phys_tcs_per_port);
609 crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ?
610 QM_REG_WFQPFCRD_RT_OFFSET :
611 QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
612 voq * MAX_NUM_PFS_BB +
613 (pf_id % MAX_NUM_PFS_BB);
614 OVERWRITE_RT_REG(p_hwfn, crd_reg_offset,
615 (u32)QM_WFQ_CRD_REG_SIGN_BIT);
618 STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET +
619 pf_id, QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
620 STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);
625 /* Prepare PF RL runtime init values for the specified PF.
626 * Return -1 on error.
628 static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
632 inc_val = QM_RL_INC_VAL(pf_rl);
633 if (inc_val > QM_PF_RL_MAX_INC_VAL) {
634 DP_NOTICE(p_hwfn, true,
635 "Invalid PF rate limit configuration\n");
639 STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id,
640 (u32)QM_RL_CRD_REG_SIGN_BIT);
641 STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
642 QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
643 STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
648 /* Prepare VPORT WFQ runtime init values for the specified VPORTs.
649 * Return -1 on error.
651 static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
653 struct init_qm_vport_params *vport_params)
655 u16 vp_pq_id, vport_id;
659 /* Go over all PF VPORTs */
660 for (vport_id = 0; vport_id < num_vports; vport_id++) {
661 if (!vport_params[vport_id].wfq)
664 inc_val = QM_WFQ_INC_VAL(vport_params[vport_id].wfq);
665 if (inc_val > QM_WFQ_MAX_INC_VAL) {
666 DP_NOTICE(p_hwfn, true,
667 "Invalid VPORT WFQ weight configuration\n");
671 /* Each VPORT can have several VPORT PQ IDs for various TCs */
672 for (tc = 0; tc < NUM_OF_TCS; tc++) {
673 vp_pq_id = vport_params[vport_id].first_tx_pq_id[tc];
674 if (vp_pq_id == QM_INVALID_PQ_ID)
677 STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET +
678 vp_pq_id, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
679 STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET +
687 static bool ecore_poll_on_qm_cmd_ready(struct ecore_hwfn *p_hwfn,
688 struct ecore_ptt *p_ptt)
692 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
694 OSAL_UDELAY(QM_STOP_CMD_POLL_PERIOD_US);
695 reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
698 /* Check if timeout while waiting for SDM command ready */
699 if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
700 DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG,
701 "Timeout waiting for QM SDM cmd ready signal\n");
708 static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn,
709 struct ecore_ptt *p_ptt,
714 if (!ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
717 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr);
718 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb);
719 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb);
720 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1);
721 ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0);
723 return ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt);
726 /******************** INTERFACE IMPLEMENTATION *********************/
728 u32 ecore_qm_pf_mem_size(struct ecore_hwfn *p_hwfn,
735 return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
736 QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
737 QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
740 int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
741 u8 max_ports_per_engine,
742 u8 max_phys_tcs_per_port,
747 struct init_qm_port_params
748 port_params[MAX_NUM_PORTS],
749 struct init_qm_global_rl_params
750 global_rl_params[COMMON_MAX_QM_GLOBAL_RLS])
754 /* Init AFullOprtnstcCrdMask */
755 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_LINEVOQ,
756 QM_OPPOR_LINE_VOQ_DEF);
757 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ, QM_BYTE_CRD_EN);
758 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFWFQ, pf_wfq_en);
759 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPWFQ, vport_wfq_en);
760 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFRL, pf_rl_en);
761 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPQCNRL, global_rl_en);
762 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_FWPAUSE, QM_OPPOR_FW_STOP_DEF);
763 SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY,
764 QM_OPPOR_PQ_EMPTY_DEF);
765 STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
767 /* Enable/disable PF RL */
768 ecore_enable_pf_rl(p_hwfn, pf_rl_en);
770 /* Enable/disable PF WFQ */
771 ecore_enable_pf_wfq(p_hwfn, pf_wfq_en);
773 /* Enable/disable global RL */
774 ecore_enable_global_rl(p_hwfn, global_rl_en);
776 /* Enable/disable VPORT WFQ */
777 ecore_enable_vport_wfq(p_hwfn, vport_wfq_en);
779 /* Init PBF CMDQ line credit */
780 ecore_cmdq_lines_rt_init(p_hwfn, max_ports_per_engine,
781 max_phys_tcs_per_port, port_params);
783 /* Init BTB blocks in PBF */
784 ecore_btb_blocks_rt_init(p_hwfn, max_ports_per_engine,
785 max_phys_tcs_per_port, port_params);
787 ecore_global_rl_rt_init(p_hwfn, global_rl_params);
792 int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
793 struct ecore_ptt *p_ptt,
795 u8 max_phys_tcs_per_port,
807 struct init_qm_pq_params *pq_params,
808 struct init_qm_vport_params *vport_params)
810 u32 other_mem_size_4kb;
814 other_mem_size_4kb = QM_PQ_MEM_4KB(num_pf_cids + num_tids) *
817 /* Clear first Tx PQ ID array for each VPORT */
818 for (vport_id = 0; vport_id < num_vports; vport_id++)
819 for (tc = 0; tc < NUM_OF_TCS; tc++)
820 vport_params[vport_id].first_tx_pq_id[tc] =
823 /* Map Other PQs (if any) */
824 #if QM_OTHER_PQS_PER_PF > 0
825 ecore_other_pq_map_rt_init(p_hwfn, pf_id, is_pf_loading, num_pf_cids,
830 if (ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, pf_id, max_phys_tcs_per_port,
831 is_pf_loading, num_pf_cids, num_vf_cids,
832 start_pq, num_pf_pqs, num_vf_pqs,
833 start_vport, other_mem_size_4kb, pq_params,
839 if (ecore_pf_wfq_rt_init(p_hwfn, pf_id, pf_wfq,
840 max_phys_tcs_per_port,
841 num_pf_pqs + num_vf_pqs, pq_params))
845 if (ecore_pf_rl_rt_init(p_hwfn, pf_id, pf_rl))
849 if (ecore_vp_wfq_rt_init(p_hwfn, num_vports, vport_params))
855 int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
856 struct ecore_ptt *p_ptt, u8 pf_id, u16 pf_wfq)
860 inc_val = QM_WFQ_INC_VAL(pf_wfq);
861 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
862 DP_NOTICE(p_hwfn, true,
863 "Invalid PF WFQ weight configuration\n");
867 ecore_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
872 int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
873 struct ecore_ptt *p_ptt, u8 pf_id, u32 pf_rl)
877 inc_val = QM_RL_INC_VAL(pf_rl);
878 if (inc_val > QM_PF_RL_MAX_INC_VAL) {
879 DP_NOTICE(p_hwfn, true,
880 "Invalid PF rate limit configuration\n");
884 ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFCRD + pf_id * 4,
885 (u32)QM_RL_CRD_REG_SIGN_BIT);
886 ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
891 int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
892 struct ecore_ptt *p_ptt,
893 u16 first_tx_pq_id[NUM_OF_TCS],
900 inc_val = QM_WFQ_INC_VAL(wfq);
901 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
902 DP_NOTICE(p_hwfn, true,
903 "Invalid VPORT WFQ weight configuration\n");
907 /* A VPORT can have several VPORT PQ IDs for various TCs */
908 for (tc = 0; tc < NUM_OF_TCS; tc++) {
909 vp_pq_id = first_tx_pq_id[tc];
910 if (vp_pq_id != QM_INVALID_PQ_ID) {
911 ecore_wr(p_hwfn, p_ptt,
912 QM_REG_WFQVPWEIGHT + vp_pq_id * 4, inc_val);
919 int ecore_init_global_rl(struct ecore_hwfn *p_hwfn,
920 struct ecore_ptt *p_ptt,
926 inc_val = QM_RL_INC_VAL(rate_limit);
927 if (inc_val > QM_VP_RL_MAX_INC_VAL(rate_limit)) {
928 DP_NOTICE(p_hwfn, true, "Invalid rate limit configuration.\n");
932 ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLCRD + rl_id * 4,
933 (u32)QM_RL_CRD_REG_SIGN_BIT);
934 ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + rl_id * 4, inc_val);
939 int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
940 struct ecore_ptt *p_ptt, u8 vport_id,
944 u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS;
946 if (vport_id >= max_qm_global_rls) {
947 DP_NOTICE(p_hwfn, true,
948 "Invalid VPORT ID for rate limiter configuration\n");
952 inc_val = QM_RL_INC_VAL(vport_rl ? vport_rl : link_speed);
953 if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) {
954 DP_NOTICE(p_hwfn, true,
955 "Invalid VPORT rate-limit configuration\n");
959 ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLCRD + vport_id * 4,
960 (u32)QM_RL_CRD_REG_SIGN_BIT);
961 ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + vport_id * 4, inc_val);
966 bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,
967 struct ecore_ptt *p_ptt,
969 bool is_tx_pq, u16 start_pq, u16 num_pqs)
971 u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 };
972 u32 pq_mask = 0, last_pq, pq_id;
974 last_pq = start_pq + num_pqs - 1;
976 /* Set command's PQ type */
977 QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
979 /* Go over requested PQs */
980 for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
981 /* Set PQ bit in mask (stop command only) */
983 pq_mask |= (1 << (pq_id % QM_STOP_PQ_MASK_WIDTH));
985 /* If last PQ or end of PQ mask, write command */
986 if ((pq_id == last_pq) ||
987 (pq_id % QM_STOP_PQ_MASK_WIDTH ==
988 (QM_STOP_PQ_MASK_WIDTH - 1))) {
989 QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PAUSE_MASK,
991 QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, GROUP_ID,
992 pq_id / QM_STOP_PQ_MASK_WIDTH);
993 if (!ecore_send_qm_cmd
994 (p_hwfn, p_ptt, QM_STOP_CMD_ADDR, cmd_arr[0],
1004 #ifndef UNUSED_HSI_FUNC
1006 /* NIG: ETS configuration constants */
1007 #define NIG_TX_ETS_CLIENT_OFFSET 4
1008 #define NIG_LB_ETS_CLIENT_OFFSET 1
1009 #define NIG_ETS_MIN_WFQ_BYTES 1600
1011 /* NIG: ETS constants */
1012 #define NIG_ETS_UP_BOUND(weight, mtu) \
1013 (2 * ((weight) > (mtu) ? (weight) : (mtu)))
1015 /* NIG: RL constants */
1017 /* Byte base type value */
1018 #define NIG_RL_BASE_TYPE 1
1021 #define NIG_RL_PERIOD 1
1023 /* Period in 25MHz cycles */
1024 #define NIG_RL_PERIOD_CLK_25M (25 * NIG_RL_PERIOD)
1027 #define NIG_RL_INC_VAL(rate) (((rate) * NIG_RL_PERIOD) / 8)
1029 #define NIG_RL_MAX_VAL(inc_val, mtu) \
1030 (2 * ((inc_val) > (mtu) ? (inc_val) : (mtu)))
1032 /* NIG: packet prioritry configuration constants */
1033 #define NIG_PRIORITY_MAP_TC_BITS 4
1036 void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,
1037 struct ecore_ptt *p_ptt,
1038 struct init_ets_req *req, bool is_lb)
1040 u32 min_weight, tc_weight_base_addr, tc_weight_addr_diff;
1041 u32 tc_bound_base_addr, tc_bound_addr_diff;
1042 u8 sp_tc_map = 0, wfq_tc_map = 0;
1043 u8 tc, num_tc, tc_client_offset;
1045 num_tc = is_lb ? NUM_OF_TCS : NUM_OF_PHYS_TCS;
1046 tc_client_offset = is_lb ? NIG_LB_ETS_CLIENT_OFFSET :
1047 NIG_TX_ETS_CLIENT_OFFSET;
1048 min_weight = 0xffffffff;
1049 tc_weight_base_addr = is_lb ? NIG_REG_LB_ARB_CREDIT_WEIGHT_0 :
1050 NIG_REG_TX_ARB_CREDIT_WEIGHT_0;
1051 tc_weight_addr_diff = is_lb ? NIG_REG_LB_ARB_CREDIT_WEIGHT_1 -
1052 NIG_REG_LB_ARB_CREDIT_WEIGHT_0 :
1053 NIG_REG_TX_ARB_CREDIT_WEIGHT_1 -
1054 NIG_REG_TX_ARB_CREDIT_WEIGHT_0;
1055 tc_bound_base_addr = is_lb ? NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 :
1056 NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0;
1057 tc_bound_addr_diff = is_lb ? NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1 -
1058 NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 :
1059 NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1 -
1060 NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0;
1062 for (tc = 0; tc < num_tc; tc++) {
1063 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
1067 sp_tc_map |= (1 << tc);
1069 if (!tc_req->use_wfq)
1072 /* Update WFQ map */
1073 wfq_tc_map |= (1 << tc);
1075 /* Find minimal weight */
1076 if (tc_req->weight < min_weight)
1077 min_weight = tc_req->weight;
1081 ecore_wr(p_hwfn, p_ptt,
1082 is_lb ? NIG_REG_LB_ARB_CLIENT_IS_STRICT :
1083 NIG_REG_TX_ARB_CLIENT_IS_STRICT,
1084 (sp_tc_map << tc_client_offset));
1087 ecore_wr(p_hwfn, p_ptt,
1088 is_lb ? NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ :
1089 NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
1090 (wfq_tc_map << tc_client_offset));
1091 /* write WFQ weights */
1092 for (tc = 0; tc < num_tc; tc++, tc_client_offset++) {
1093 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
1096 if (!tc_req->use_wfq)
1099 /* Translate weight to bytes */
1100 byte_weight = (NIG_ETS_MIN_WFQ_BYTES * tc_req->weight) /
1103 /* Write WFQ weight */
1104 ecore_wr(p_hwfn, p_ptt, tc_weight_base_addr +
1105 tc_weight_addr_diff * tc_client_offset, byte_weight);
1107 /* Write WFQ upper bound */
1108 ecore_wr(p_hwfn, p_ptt, tc_bound_base_addr +
1109 tc_bound_addr_diff * tc_client_offset,
1110 NIG_ETS_UP_BOUND(byte_weight, req->mtu));
1114 void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,
1115 struct ecore_ptt *p_ptt,
1116 struct init_nig_lb_rl_req *req)
1118 u32 ctrl, inc_val, reg_offset;
1121 /* Disable global MAC+LB RL */
1124 NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT;
1125 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);
1127 /* Configure and enable global MAC+LB RL */
1128 if (req->lb_mac_rate) {
1130 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD,
1131 NIG_RL_PERIOD_CLK_25M);
1132 inc_val = NIG_RL_INC_VAL(req->lb_mac_rate);
1133 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE,
1135 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE,
1136 NIG_RL_MAX_VAL(inc_val, req->mtu));
1141 NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT;
1142 ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);
1145 /* Disable global LB-only RL */
1148 NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT;
1149 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);
1151 /* Configure and enable global LB-only RL */
1154 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_INC_PERIOD,
1155 NIG_RL_PERIOD_CLK_25M);
1156 inc_val = NIG_RL_INC_VAL(req->lb_rate);
1157 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_INC_VALUE,
1159 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_MAX_VALUE,
1160 NIG_RL_MAX_VAL(inc_val, req->mtu));
1164 1 << NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT;
1165 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);
1169 for (tc = 0, reg_offset = 0; tc < NUM_OF_PHYS_TCS;
1170 tc++, reg_offset += 4) {
1174 NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT;
1175 ecore_wr(p_hwfn, p_ptt,
1176 NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);
1178 /* Configure and enable TC RL */
1179 if (!req->tc_rate[tc])
1183 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 +
1184 reg_offset, NIG_RL_PERIOD_CLK_25M);
1185 inc_val = NIG_RL_INC_VAL(req->tc_rate[tc]);
1186 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 +
1187 reg_offset, inc_val);
1188 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 +
1189 reg_offset, NIG_RL_MAX_VAL(inc_val, req->mtu));
1193 NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT;
1194 ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 +
1199 void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,
1200 struct ecore_ptt *p_ptt,
1201 struct init_nig_pri_tc_map_req *req)
1203 u8 tc_pri_mask[NUM_OF_PHYS_TCS] = { 0 };
1204 u32 pri_tc_mask = 0;
1207 for (pri = 0; pri < NUM_OF_VLAN_PRIORITIES; pri++) {
1208 if (!req->pri[pri].valid)
1211 pri_tc_mask |= (req->pri[pri].tc_id <<
1212 (pri * NIG_PRIORITY_MAP_TC_BITS));
1213 tc_pri_mask[req->pri[pri].tc_id] |= (1 << pri);
1216 /* Write priority -> TC mask */
1217 ecore_wr(p_hwfn, p_ptt, NIG_REG_PKT_PRIORITY_TO_TC, pri_tc_mask);
1219 /* Write TC -> priority mask */
1220 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
1221 ecore_wr(p_hwfn, p_ptt, NIG_REG_PRIORITY_FOR_TC_0 + tc * 4,
1223 ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_TC0_PRIORITY_MASK + tc * 4,
1228 #endif /* UNUSED_HSI_FUNC */
1230 #ifndef UNUSED_HSI_FUNC
1232 /* PRS: ETS configuration constants */
1233 #define PRS_ETS_MIN_WFQ_BYTES 1600
1234 #define PRS_ETS_UP_BOUND(weight, mtu) \
1235 (2 * ((weight) > (mtu) ? (weight) : (mtu)))
1238 void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn,
1239 struct ecore_ptt *p_ptt, struct init_ets_req *req)
1241 u32 tc_weight_addr_diff, tc_bound_addr_diff, min_weight = 0xffffffff;
1242 u8 tc, sp_tc_map = 0, wfq_tc_map = 0;
1244 tc_weight_addr_diff = PRS_REG_ETS_ARB_CREDIT_WEIGHT_1 -
1245 PRS_REG_ETS_ARB_CREDIT_WEIGHT_0;
1246 tc_bound_addr_diff = PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1 -
1247 PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0;
1249 for (tc = 0; tc < NUM_OF_TCS; tc++) {
1250 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
1254 sp_tc_map |= (1 << tc);
1256 if (!tc_req->use_wfq)
1259 /* Update WFQ map */
1260 wfq_tc_map |= (1 << tc);
1262 /* Find minimal weight */
1263 if (tc_req->weight < min_weight)
1264 min_weight = tc_req->weight;
1268 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CLIENT_IS_STRICT, sp_tc_map);
1271 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ,
1274 /* write WFQ weights */
1275 for (tc = 0; tc < NUM_OF_TCS; tc++) {
1276 struct init_ets_tc_req *tc_req = &req->tc_req[tc];
1279 if (!tc_req->use_wfq)
1282 /* Translate weight to bytes */
1283 byte_weight = (PRS_ETS_MIN_WFQ_BYTES * tc_req->weight) /
1286 /* Write WFQ weight */
1287 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CREDIT_WEIGHT_0 + tc *
1288 tc_weight_addr_diff, byte_weight);
1290 /* Write WFQ upper bound */
1291 ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0 +
1292 tc * tc_bound_addr_diff, PRS_ETS_UP_BOUND(byte_weight,
1297 #endif /* UNUSED_HSI_FUNC */
1298 #ifndef UNUSED_HSI_FUNC
1300 /* BRB: RAM configuration constants */
1301 #define BRB_TOTAL_RAM_BLOCKS_BB 4800
1302 #define BRB_TOTAL_RAM_BLOCKS_K2 5632
1303 #define BRB_BLOCK_SIZE 128
1304 #define BRB_MIN_BLOCKS_PER_TC 9
1305 #define BRB_HYST_BYTES 10240
1306 #define BRB_HYST_BLOCKS (BRB_HYST_BYTES / BRB_BLOCK_SIZE)
1308 /* Temporary big RAM allocation - should be updated */
1309 void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
1310 struct ecore_ptt *p_ptt, struct init_brb_ram_req *req)
1312 u32 tc_headroom_blocks, min_pkt_size_blocks, total_blocks;
1313 u32 active_port_blocks, reg_offset = 0;
1314 u8 port, active_ports = 0;
1316 tc_headroom_blocks = (u32)DIV_ROUND_UP(req->headroom_per_tc,
1318 min_pkt_size_blocks = (u32)DIV_ROUND_UP(req->min_pkt_size,
1320 total_blocks = ECORE_IS_K2(p_hwfn->p_dev) ? BRB_TOTAL_RAM_BLOCKS_K2 :
1321 BRB_TOTAL_RAM_BLOCKS_BB;
1323 /* Find number of active ports */
1324 for (port = 0; port < MAX_NUM_PORTS; port++)
1325 if (req->num_active_tcs[port])
1328 active_port_blocks = (u32)(total_blocks / active_ports);
1330 for (port = 0; port < req->max_ports_per_engine; port++) {
1331 u32 port_blocks, port_shared_blocks, port_guaranteed_blocks;
1332 u32 full_xoff_th, full_xon_th, pause_xoff_th, pause_xon_th;
1333 u32 tc_guaranteed_blocks;
1336 /* Calculate per-port sizes */
1337 tc_guaranteed_blocks = (u32)DIV_ROUND_UP(req->guranteed_per_tc,
1339 port_blocks = req->num_active_tcs[port] ? active_port_blocks :
1341 port_guaranteed_blocks = req->num_active_tcs[port] *
1342 tc_guaranteed_blocks;
1343 port_shared_blocks = port_blocks - port_guaranteed_blocks;
1344 full_xoff_th = req->num_active_tcs[port] *
1345 BRB_MIN_BLOCKS_PER_TC;
1346 full_xon_th = full_xoff_th + min_pkt_size_blocks;
1347 pause_xoff_th = tc_headroom_blocks;
1348 pause_xon_th = pause_xoff_th + min_pkt_size_blocks;
1350 /* Init total size per port */
1351 ecore_wr(p_hwfn, p_ptt, BRB_REG_TOTAL_MAC_SIZE + port * 4,
1354 /* Init shared size per port */
1355 ecore_wr(p_hwfn, p_ptt, BRB_REG_SHARED_HR_AREA + port * 4,
1356 port_shared_blocks);
1358 for (tc = 0; tc < NUM_OF_TCS; tc++, reg_offset += 4) {
1359 /* Clear init values for non-active TCs */
1360 if (tc == req->num_active_tcs[port]) {
1361 tc_guaranteed_blocks = 0;
1368 /* Init guaranteed size per TC */
1369 ecore_wr(p_hwfn, p_ptt,
1370 BRB_REG_TC_GUARANTIED_0 + reg_offset,
1371 tc_guaranteed_blocks);
1372 ecore_wr(p_hwfn, p_ptt,
1373 BRB_REG_MAIN_TC_GUARANTIED_HYST_0 + reg_offset,
1376 /* Init pause/full thresholds per physical TC - for
1379 ecore_wr(p_hwfn, p_ptt,
1380 BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0 +
1381 reg_offset, full_xoff_th);
1382 ecore_wr(p_hwfn, p_ptt,
1383 BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 +
1384 reg_offset, full_xon_th);
1385 ecore_wr(p_hwfn, p_ptt,
1386 BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0 +
1387 reg_offset, pause_xoff_th);
1388 ecore_wr(p_hwfn, p_ptt,
1389 BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0 +
1390 reg_offset, pause_xon_th);
1392 /* Init pause/full thresholds per physical TC - for
1395 ecore_wr(p_hwfn, p_ptt,
1396 BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0 +
1397 reg_offset, full_xoff_th);
1398 ecore_wr(p_hwfn, p_ptt,
1399 BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0 +
1400 reg_offset, full_xon_th);
1401 ecore_wr(p_hwfn, p_ptt,
1402 BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0 +
1403 reg_offset, pause_xoff_th);
1404 ecore_wr(p_hwfn, p_ptt,
1405 BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0 +
1406 reg_offset, pause_xon_th);
1411 #endif /* UNUSED_HSI_FUNC */
1412 #ifndef UNUSED_HSI_FUNC
1414 #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \
1417 for (i = 0; i < (arr_size); i++) \
1418 ecore_wr(dev, ptt, ((addr) + (4 * i)), \
1419 ((u32 *)&(arr))[i]); \
1422 #ifndef DWORDS_TO_BYTES
1423 #define DWORDS_TO_BYTES(dwords) ((dwords) * REG_SIZE)
1428 * @brief ecore_dmae_to_grc - is an internal function - writes from host to
1429 * wide-bus registers (split registers are not supported yet)
1431 * @param p_hwfn - HW device data
1432 * @param p_ptt - ptt window used for writing the registers.
1433 * @param pData - pointer to source data.
1434 * @param addr - Destination register address.
1435 * @param len_in_dwords - data length in DWARDS (u32)
1437 static int ecore_dmae_to_grc(struct ecore_hwfn *p_hwfn,
1438 struct ecore_ptt *p_ptt,
1443 struct dmae_params params;
1444 bool read_using_dmae = false;
1449 /* Set DMAE params */
1450 OSAL_MEMSET(¶ms, 0, sizeof(params));
1452 SET_FIELD(params.flags, DMAE_PARAMS_COMPLETION_DST, 1);
1454 /* Execute DMAE command */
1455 read_using_dmae = !ecore_dmae_host2grc(p_hwfn, p_ptt,
1456 (u64)(osal_uintptr_t)(pData),
1457 addr, len_in_dwords, ¶ms);
1458 if (!read_using_dmae)
1459 DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG,
1460 "Failed writing to chip using DMAE, using GRC instead\n");
1462 /* If not read using DMAE, read using GRC */
1463 if (!read_using_dmae)
1464 /* write to registers using GRC */
1465 ARR_REG_WR(p_hwfn, p_ptt, addr, pData, len_in_dwords);
1467 return len_in_dwords;
1470 /* In MF, should be called once per port to set EtherType of OuterTag */
1471 void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, u32 ethType)
1473 /* Update DORQ register */
1474 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, ethType);
1477 #endif /* UNUSED_HSI_FUNC */
1479 #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \
1480 (var = ((var) & ~(1 << (offset))) | ((enable) ? (1 << (offset)) : 0))
1481 #define PRS_ETH_TUNN_OUTPUT_FORMAT -188897008
1482 #define PRS_ETH_OUTPUT_FORMAT -46832
1484 void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
1485 struct ecore_ptt *p_ptt, u16 dest_port)
1487 /* Update PRS register */
1488 ecore_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
1490 /* Update NIG register */
1491 ecore_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
1493 /* Update PBF register */
1494 ecore_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
1497 void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
1498 struct ecore_ptt *p_ptt, bool vxlan_enable)
1502 /* Update PRS register */
1503 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1504 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1505 PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT,
1507 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1508 if (reg_val) { /* TODO: handle E5 init */
1509 reg_val = ecore_rd(p_hwfn, p_ptt,
1510 PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
1512 /* Update output only if tunnel blocks not included. */
1513 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1514 ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1515 (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1518 /* Update NIG register */
1519 reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1520 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1521 NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT,
1523 ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1525 /* Update DORQ register */
1526 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN,
1527 vxlan_enable ? 1 : 0);
1530 void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
1531 struct ecore_ptt *p_ptt,
1532 bool eth_gre_enable, bool ip_gre_enable)
1536 /* Update PRS register */
1537 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1538 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1539 PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT,
1541 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1542 PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT,
1544 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1545 if (reg_val) { /* TODO: handle E5 init */
1546 reg_val = ecore_rd(p_hwfn, p_ptt,
1547 PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
1549 /* Update output only if tunnel blocks not included. */
1550 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1551 ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1552 (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1555 /* Update NIG register */
1556 reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1557 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1558 NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT,
1560 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1561 NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT,
1563 ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1565 /* Update DORQ registers */
1566 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN,
1567 eth_gre_enable ? 1 : 0);
1568 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN,
1569 ip_gre_enable ? 1 : 0);
1572 void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
1573 struct ecore_ptt *p_ptt, u16 dest_port)
1575 /* Update PRS register */
1576 ecore_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port);
1578 /* Update NIG register */
1579 ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port);
1581 /* Update PBF register */
1582 ecore_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port);
1585 void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
1586 struct ecore_ptt *p_ptt,
1587 bool eth_geneve_enable, bool ip_geneve_enable)
1591 /* Update PRS register */
1592 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1593 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1594 PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT,
1596 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val,
1597 PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT,
1599 ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1600 if (reg_val) { /* TODO: handle E5 init */
1601 reg_val = ecore_rd(p_hwfn, p_ptt,
1602 PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
1604 /* Update output only if tunnel blocks not included. */
1605 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1606 ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1607 (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1610 /* Update NIG register */
1611 ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
1612 eth_geneve_enable ? 1 : 0);
1613 ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE,
1614 ip_geneve_enable ? 1 : 0);
1616 /* EDPM with geneve tunnel not supported in BB */
1617 if (ECORE_IS_BB_B0(p_hwfn->p_dev))
1620 /* Update DORQ registers */
1621 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2,
1622 eth_geneve_enable ? 1 : 0);
1623 ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2,
1624 ip_geneve_enable ? 1 : 0);
1627 #define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET 3
1628 #define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT -925189872
1630 void ecore_set_vxlan_no_l2_enable(struct ecore_hwfn *p_hwfn,
1631 struct ecore_ptt *p_ptt,
1634 u32 reg_val, cfg_mask;
1636 /* read PRS config register */
1637 reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO);
1639 /* set VXLAN_NO_L2_ENABLE mask */
1640 cfg_mask = (1 << PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET);
1643 /* set VXLAN_NO_L2_ENABLE flag */
1644 reg_val |= cfg_mask;
1646 /* update PRS FIC Format register */
1647 ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1648 (u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT);
1649 /* clear VXLAN_NO_L2_ENABLE flag */
1650 reg_val &= ~cfg_mask;
1653 /* write PRS config register */
1654 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val);
1657 #ifndef UNUSED_HSI_FUNC
1659 #define T_ETH_PACKET_ACTION_GFT_EVENTID 23
1660 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272
1661 #define T_ETH_PACKET_MATCH_RFS_EVENTID 25
1662 #define PARSER_ETH_CONN_CM_HDR 0
1663 #define CAM_LINE_SIZE sizeof(u32)
1664 #define RAM_LINE_SIZE sizeof(u64)
1665 #define REG_SIZE sizeof(u32)
1667 void ecore_gft_disable(struct ecore_hwfn *p_hwfn,
1668 struct ecore_ptt *p_ptt,
1671 struct regpair ram_line;
1672 OSAL_MEMSET(&ram_line, 0, sizeof(ram_line));
1674 /* disable gft search for PF */
1675 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
1677 /* Clean ram & cam for next gft session*/
1680 ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0);
1683 ecore_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line,
1684 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
1685 sizeof(ram_line) / REG_SIZE);
1690 void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
1691 struct ecore_ptt *p_ptt)
1693 u32 rfs_cm_hdr_event_id;
1695 /* Set RFS event ID to be awakened i Tstorm By Prs */
1696 rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
1697 rfs_cm_hdr_event_id |= T_ETH_PACKET_ACTION_GFT_EVENTID <<
1698 PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1699 rfs_cm_hdr_event_id |= PARSER_ETH_CONN_GFT_ACTION_CM_HDR <<
1700 PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1701 ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
1704 void ecore_gft_config(struct ecore_hwfn *p_hwfn,
1705 struct ecore_ptt *p_ptt,
1711 enum gft_profile_type profile_type)
1713 u32 reg_val, cam_line, search_non_ip_as_gft;
1714 struct regpair ram_line = { 0 };
1717 DP_NOTICE(p_hwfn, true, "gft_config: must accept at least on of - ipv4 or ipv6'\n");
1719 DP_NOTICE(p_hwfn, true, "gft_config: must accept at least on of - udp or tcp\n");
1720 if (profile_type >= MAX_GFT_PROFILE_TYPE)
1721 DP_NOTICE(p_hwfn, true, "gft_config: unsupported gft_profile_type\n");
1723 /* Set RFS event ID to be awakened i Tstorm By Prs */
1724 reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<
1725 PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1726 reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1727 ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);
1729 /* Do not load context only cid in PRS on match. */
1730 ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
1732 /* Do not use tenant ID exist bit for gft search*/
1733 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0);
1737 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1);
1739 /* Filters are per PF!! */
1740 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID_MASK,
1741 GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
1742 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
1744 if (!(tcp && udp)) {
1746 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
1747 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
1750 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1751 GFT_PROFILE_TCP_PROTOCOL);
1754 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1755 GFT_PROFILE_UDP_PROTOCOL);
1758 if (!(ipv4 && ipv6)) {
1759 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
1761 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION,
1764 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION,
1768 /* Write characteristics to cam */
1769 ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
1771 cam_line = ecore_rd(p_hwfn, p_ptt,
1772 PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
1774 /* Write line to RAM - compare to filter 4 tuple */
1776 /* Search no IP as GFT */
1777 search_non_ip_as_gft = 0;
1780 SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1);
1781 SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1);
1783 if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) {
1784 SET_FIELD(ram_line.hi, GFT_RAM_LINE_DST_IP, 1);
1785 SET_FIELD(ram_line.hi, GFT_RAM_LINE_SRC_IP, 1);
1786 SET_FIELD(ram_line.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1787 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1788 SET_FIELD(ram_line.lo, GFT_RAM_LINE_SRC_PORT, 1);
1789 SET_FIELD(ram_line.lo, GFT_RAM_LINE_DST_PORT, 1);
1790 } else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) {
1791 SET_FIELD(ram_line.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1792 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1793 SET_FIELD(ram_line.lo, GFT_RAM_LINE_DST_PORT, 1);
1794 } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_ADDR) {
1795 SET_FIELD(ram_line.hi, GFT_RAM_LINE_DST_IP, 1);
1796 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1797 } else if (profile_type == GFT_PROFILE_TYPE_IP_SRC_ADDR) {
1798 SET_FIELD(ram_line.hi, GFT_RAM_LINE_SRC_IP, 1);
1799 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1800 } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) {
1801 SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1);
1803 /* Allow tunneled traffic without inner IP */
1804 search_non_ip_as_gft = 1;
1807 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_NON_IP_AS_GFT,
1808 search_non_ip_as_gft);
1809 ecore_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line,
1810 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
1811 sizeof(ram_line) / REG_SIZE);
1813 /* Set default profile so that no filter match will happen */
1814 ram_line.lo = 0xffffffff;
1815 ram_line.hi = 0x3ff;
1816 ecore_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line,
1817 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
1818 PRS_GFT_CAM_LINES_NO_MATCH,
1819 sizeof(ram_line) / REG_SIZE);
1821 /* Enable gft search */
1822 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
1826 #endif /* UNUSED_HSI_FUNC */
1828 /* Configure VF zone size mode */
1829 void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn,
1830 struct ecore_ptt *p_ptt, u16 mode,
1833 u32 msdm_vf_size_log = MSTORM_VF_ZONE_DEFAULT_SIZE_LOG;
1834 u32 msdm_vf_offset_mask;
1836 if (mode == VF_ZONE_SIZE_MODE_DOUBLE)
1837 msdm_vf_size_log += 1;
1838 else if (mode == VF_ZONE_SIZE_MODE_QUAD)
1839 msdm_vf_size_log += 2;
1841 msdm_vf_offset_mask = (1 << msdm_vf_size_log) - 1;
1844 STORE_RT_REG(p_hwfn,
1845 PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET,
1847 STORE_RT_REG(p_hwfn,
1848 PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET,
1849 msdm_vf_offset_mask);
1851 ecore_wr(p_hwfn, p_ptt,
1852 PGLUE_B_REG_MSDM_VF_SHIFT_B, msdm_vf_size_log);
1853 ecore_wr(p_hwfn, p_ptt,
1854 PGLUE_B_REG_MSDM_OFFSET_MASK_B, msdm_vf_offset_mask);
1858 /* Get mstorm statistics for offset by VF zone size mode */
1859 u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn,
1861 u16 vf_zone_size_mode)
1863 u32 offset = MSTORM_QUEUE_STAT_OFFSET(stat_cnt_id);
1865 if ((vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) &&
1866 (stat_cnt_id > MAX_NUM_PFS)) {
1867 if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
1868 offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1869 (stat_cnt_id - MAX_NUM_PFS);
1870 else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
1871 offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1872 (stat_cnt_id - MAX_NUM_PFS);
1878 /* Get mstorm VF producer offset by VF zone size mode */
1879 u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn,
1882 u16 vf_zone_size_mode)
1884 u32 offset = MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id);
1886 if (vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) {
1887 if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
1888 offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1890 else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
1891 offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
1898 #ifndef LINUX_REMOVE
1899 #define CRC8_INIT_VALUE 0xFF
1901 static u8 cdu_crc8_table[CRC8_TABLE_SIZE];
1903 /* Calculate and return CDU validation byte per connection type / region /
1906 static u8 ecore_calc_cdu_validation_byte(struct ecore_hwfn *p_hwfn,
1907 u8 conn_type, u8 region, u32 cid)
1909 static u8 crc8_table_valid; /*automatically initialized to 0*/
1910 u8 crc, validation_byte = 0;
1911 u32 validation_string = 0;
1914 if (crc8_table_valid == 0) {
1915 OSAL_CRC8_POPULATE(cdu_crc8_table, 0x07);
1916 crc8_table_valid = 1;
1920 * The CRC is calculated on the String-to-compress:
1921 * [31:8] = {CID[31:20],CID[11:0]}
1925 #if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \
1926 CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1)
1927 validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8);
1930 #if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \
1931 CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1)
1932 validation_string |= ((region & 0xF) << 4);
1935 #if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \
1936 CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1)
1937 validation_string |= (conn_type & 0xF);
1939 /* Convert to big-endian and calculate CRC8*/
1940 data_to_crc = OSAL_BE32_TO_CPU(validation_string);
1942 crc = OSAL_CRC8(cdu_crc8_table, (u8 *)&data_to_crc, sizeof(data_to_crc),
1945 /* The validation byte [7:0] is composed:
1946 * for type A validation
1947 * [7] = active configuration bit
1950 * for type B validation
1951 * [7] = active configuration bit
1952 * [6:3] = connection_type[3:0]
1955 validation_byte |= ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >>
1956 CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7;
1958 #if ((CDU_CONTEXT_VALIDATION_DEFAULT_CFG >> \
1959 CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1)
1960 validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7);
1962 validation_byte |= crc & 0x7F;
1964 return validation_byte;
1967 /* Calcualte and set validation bytes for session context */
1968 void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn,
1969 void *p_ctx_mem, u16 ctx_size,
1970 u8 ctx_type, u32 cid)
1972 u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1974 p_ctx = (u8 *)p_ctx_mem;
1976 x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1977 t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1978 u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1980 OSAL_MEMSET(p_ctx, 0, ctx_size);
1982 *x_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 3, cid);
1983 *t_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 4, cid);
1984 *u_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 5, cid);
1987 /* Calcualte and set validation bytes for task context */
1988 void ecore_calc_task_ctx_validation(struct ecore_hwfn *p_hwfn, void *p_ctx_mem,
1989 u16 ctx_size, u8 ctx_type, u32 tid)
1991 u8 *p_ctx, *region1_val_ptr;
1993 p_ctx = (u8 *)p_ctx_mem;
1994 region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1996 OSAL_MEMSET(p_ctx, 0, ctx_size);
1998 *region1_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 1,
2002 /* Memset session context to 0 while preserving validation bytes */
2003 void ecore_memset_session_ctx(struct ecore_hwfn *p_hwfn, void *p_ctx_mem,
2004 u32 ctx_size, u8 ctx_type)
2006 u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
2007 u8 x_val, t_val, u_val;
2009 p_ctx = (u8 *)p_ctx_mem;
2011 x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
2012 t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
2013 u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
2019 OSAL_MEMSET(p_ctx, 0, ctx_size);
2026 /* Memset task context to 0 while preserving validation bytes */
2027 void ecore_memset_task_ctx(struct ecore_hwfn *p_hwfn, void *p_ctx_mem,
2028 u32 ctx_size, u8 ctx_type)
2030 u8 *p_ctx, *region1_val_ptr;
2033 p_ctx = (u8 *)p_ctx_mem;
2034 region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
2036 region1_val = *region1_val_ptr;
2038 OSAL_MEMSET(p_ctx, 0, ctx_size);
2040 *region1_val_ptr = region1_val;
2043 /* Enable and configure context validation */
2044 void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn,
2045 struct ecore_ptt *p_ptt)
2049 /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */
2050 ctx_validation = CDU_CONTEXT_VALIDATION_DEFAULT_CFG << 24;
2051 ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation);
2053 /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */
2054 ctx_validation = CDU_CONTEXT_VALIDATION_DEFAULT_CFG << 8;
2055 ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation);
2057 /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */
2058 ctx_validation = CDU_CONTEXT_VALIDATION_DEFAULT_CFG << 8;
2059 ecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);
2062 #define PHYS_ADDR_DWORDS DIV_ROUND_UP(sizeof(dma_addr_t), 4)
2063 #define OVERLAY_HDR_SIZE_DWORDS (sizeof(struct fw_overlay_buf_hdr) / 4)
2065 static u32 ecore_get_overlay_addr_ram_addr(struct ecore_hwfn *p_hwfn,
2069 case 0: return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
2070 TSTORM_OVERLAY_BUF_ADDR_OFFSET;
2071 case 1: return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
2072 MSTORM_OVERLAY_BUF_ADDR_OFFSET;
2073 case 2: return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
2074 USTORM_OVERLAY_BUF_ADDR_OFFSET;
2075 case 3: return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
2076 XSTORM_OVERLAY_BUF_ADDR_OFFSET;
2077 case 4: return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
2078 YSTORM_OVERLAY_BUF_ADDR_OFFSET;
2079 case 5: return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
2080 PSTORM_OVERLAY_BUF_ADDR_OFFSET;
2086 struct phys_mem_desc *ecore_fw_overlay_mem_alloc(struct ecore_hwfn *p_hwfn,
2087 const u32 *const fw_overlay_in_buf,
2088 u32 buf_size_in_bytes)
2090 u32 buf_size = buf_size_in_bytes / sizeof(u32), buf_offset = 0;
2091 struct phys_mem_desc *allocated_mem;
2096 allocated_mem = (struct phys_mem_desc *)OSAL_ZALLOC(p_hwfn->p_dev,
2099 sizeof(struct phys_mem_desc));
2103 OSAL_MEMSET(allocated_mem, 0, NUM_STORMS *
2104 sizeof(struct phys_mem_desc));
2106 /* For each Storm, set physical address in RAM */
2107 while (buf_offset < buf_size) {
2108 struct phys_mem_desc *storm_mem_desc;
2109 struct fw_overlay_buf_hdr *hdr;
2114 (struct fw_overlay_buf_hdr *)&fw_overlay_in_buf[buf_offset];
2115 storm_buf_size = GET_FIELD(hdr->data,
2116 FW_OVERLAY_BUF_HDR_BUF_SIZE);
2117 storm_id = GET_FIELD(hdr->data, FW_OVERLAY_BUF_HDR_STORM_ID);
2118 storm_mem_desc = allocated_mem + storm_id;
2119 storm_mem_desc->size = storm_buf_size * sizeof(u32);
2121 /* Allocate physical memory for Storm's overlays buffer */
2122 storm_mem_desc->virt_addr =
2123 OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2124 &storm_mem_desc->phys_addr,
2125 storm_mem_desc->size);
2126 if (!storm_mem_desc->virt_addr)
2129 /* Skip overlays buffer header */
2130 buf_offset += OVERLAY_HDR_SIZE_DWORDS;
2132 /* Copy Storm's overlays buffer to allocated memory */
2133 OSAL_MEMCPY(storm_mem_desc->virt_addr,
2134 &fw_overlay_in_buf[buf_offset],
2135 storm_mem_desc->size);
2137 /* Advance to next Storm */
2138 buf_offset += storm_buf_size;
2141 /* If memory allocation has failed, free all allocated memory */
2142 if (buf_offset < buf_size) {
2143 ecore_fw_overlay_mem_free(p_hwfn, allocated_mem);
2147 return allocated_mem;
2150 void ecore_fw_overlay_init_ram(struct ecore_hwfn *p_hwfn,
2151 struct ecore_ptt *p_ptt,
2152 struct phys_mem_desc *fw_overlay_mem)
2156 for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
2157 struct phys_mem_desc *storm_mem_desc =
2158 (struct phys_mem_desc *)fw_overlay_mem + storm_id;
2161 /* Skip Storms with no FW overlays */
2162 if (!storm_mem_desc->virt_addr)
2165 /* Calculate overlay RAM GRC address of current PF */
2166 ram_addr = ecore_get_overlay_addr_ram_addr(p_hwfn, storm_id) +
2167 sizeof(dma_addr_t) * p_hwfn->rel_pf_id;
2169 /* Write Storm's overlay physical address to RAM */
2170 for (i = 0; i < PHYS_ADDR_DWORDS; i++, ram_addr += sizeof(u32))
2171 ecore_wr(p_hwfn, p_ptt, ram_addr,
2172 ((u32 *)&storm_mem_desc->phys_addr)[i]);
2176 void ecore_fw_overlay_mem_free(struct ecore_hwfn *p_hwfn,
2177 struct phys_mem_desc *fw_overlay_mem)
2181 if (!fw_overlay_mem)
2184 for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
2185 struct phys_mem_desc *storm_mem_desc =
2186 (struct phys_mem_desc *)fw_overlay_mem + storm_id;
2188 /* Free Storm's physical memory */
2189 if (storm_mem_desc->virt_addr)
2190 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2191 storm_mem_desc->virt_addr,
2192 storm_mem_desc->phys_addr,
2193 storm_mem_desc->size);
2196 /* Free allocated virtual memory */
2197 OSAL_FREE(p_hwfn->p_dev, fw_overlay_mem);