2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #ifndef __ECORE_INT_API_H__
10 #define __ECORE_INT_API_H__
12 #ifndef __EXTRACT__LINUX__
13 #define ECORE_SB_IDX 0x0002
16 #define TX_PI(tc) (RX_PI + 1 + tc)
18 #ifndef ECORE_INT_MODE
19 #define ECORE_INT_MODE
28 struct ecore_sb_info {
29 struct status_block *sb_virt;
31 u32 sb_ack; /* Last given ack */
33 void OSAL_IOMEM *igu_addr;
35 #define ECORE_SB_INFO_INIT 0x1
36 #define ECORE_SB_INFO_SETUP 0x2
38 #ifdef ECORE_CONFIG_DIRECT_HWFN
39 struct ecore_hwfn *p_hwfn;
41 struct ecore_dev *p_dev;
44 struct ecore_sb_cnt_info {
50 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
55 /* barrier(); status block is written to by the chip */
56 /* FIXME: need some sort of barrier. */
57 prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
58 STATUS_BLOCK_PROD_INDEX_MASK;
59 if (sb_info->sb_ack != prod) {
60 sb_info->sb_ack = prod;
64 OSAL_MMIOWB(sb_info->p_dev);
70 * @brief This function creates an update command for interrupts that is
73 * @param sb_info - This is the structure allocated and
74 * initialized per status block. Assumption is
75 * that it was initialized using ecore_sb_init
76 * @param int_cmd - Enable/Disable/Nop
77 * @param upd_flg - whether igu consumer should be
80 * @return OSAL_INLINE void
82 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
83 enum igu_int_cmd int_cmd, u8 upd_flg)
85 struct igu_prod_cons_update igu_ack = { 0 };
87 igu_ack.sb_id_and_flags =
88 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
89 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
90 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
91 (IGU_SEG_ACCESS_REG << IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
93 #ifdef ECORE_CONFIG_DIRECT_HWFN
94 DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
95 igu_ack.sb_id_and_flags);
97 DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, igu_ack.sb_id_and_flags);
99 /* Both segments (interrupts & acks) are written to same place address;
100 * Need to guarantee all commands will be received (in-order) by HW.
102 OSAL_MMIOWB(sb_info->p_dev);
103 OSAL_BARRIER(sb_info->p_dev);
106 #ifdef ECORE_CONFIG_DIRECT_HWFN
107 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
108 void OSAL_IOMEM *addr,
111 static OSAL_INLINE void __internal_ram_wr(void *p_hwfn,
112 void OSAL_IOMEM *addr,
118 for (i = 0; i < size / sizeof(*data); i++)
119 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
122 #ifdef ECORE_CONFIG_DIRECT_HWFN
123 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
124 void OSAL_IOMEM *addr,
127 __internal_ram_wr(p_hwfn, addr, size, data);
130 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
133 __internal_ram_wr(OSAL_NULL, addr, size, data);
141 enum ecore_coalescing_fsm {
142 ECORE_COAL_RX_STATE_MACHINE,
143 ECORE_COAL_TX_STATE_MACHINE
147 * @brief ecore_int_cau_conf_pi - configure cau for a given
157 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
158 struct ecore_ptt *p_ptt,
161 enum ecore_coalescing_fsm coalescing_fsm,
166 * @brief ecore_int_igu_enable_int - enable device interrupts
170 * @param int_mode - interrupt mode to use
172 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
173 struct ecore_ptt *p_ptt,
174 enum ecore_int_mode int_mode);
178 * @brief ecore_int_igu_disable_int - disable device interrupts
183 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
184 struct ecore_ptt *p_ptt);
188 * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
195 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
197 #define ECORE_SP_SB_ID 0xffff
199 * @brief ecore_int_sb_init - Initializes the sb_info structure.
201 * once the structure is initialized it can be passed to sb related functions.
205 * @param sb_info points to an uninitialized (but
206 * allocated) sb_info structure
207 * @param sb_virt_addr
209 * @param sb_id the sb_id to be used (zero based in driver)
210 * should use ECORE_SP_SB_ID for SP Status block
212 * @return enum _ecore_status_t
214 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
215 struct ecore_ptt *p_ptt,
216 struct ecore_sb_info *sb_info,
218 dma_addr_t sb_phy_addr, u16 sb_id);
220 * @brief ecore_int_sb_setup - Setup the sb.
224 * @param sb_info initialized sb_info structure
226 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
227 struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info);
230 * @brief ecore_int_sb_release - releases the sb_info structure.
232 * once the structure is released, it's memory can be freed
235 * @param sb_info points to an allocated sb_info structure
236 * @param sb_id the sb_id to be used (zero based in driver)
237 * should never be equal to ECORE_SP_SB_ID
240 * @return enum _ecore_status_t
242 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
243 struct ecore_sb_info *sb_info,
247 * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
248 * default status block.
250 * @param p_hwfn - pointer to hwfn
253 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
256 * @brief ecore_int_get_num_sbs - get the number of status
257 * blocks configured for this funciton in the igu.
260 * @param p_sb_cnt_info
264 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
265 struct ecore_sb_cnt_info *p_sb_cnt_info);
268 * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
269 * release. The API need to be called after releasing all slowpath IRQs
275 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
278 * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
279 * preventing attentions from being reasserted, or following the
280 * attributes of the specific attention.
286 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);