1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __IRO_VALUES_H__
8 #define __IRO_VALUES_H__
10 static const struct iro iro_arr[60] = {
11 /* YSTORM_FLOW_CONTROL_MODE_OFFSET */
12 { 0x0, 0x0, 0x0, 0x0, 0x8},
13 /* TSTORM_PORT_STAT_OFFSET(port_id) */
14 { 0x4cb8, 0x88, 0x0, 0x0, 0x88},
15 /* TSTORM_LL2_PORT_STAT_OFFSET(port_id) */
16 { 0x6530, 0x20, 0x0, 0x0, 0x20},
17 /* USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) */
18 { 0xb00, 0x8, 0x0, 0x0, 0x4},
19 /* USTORM_FLR_FINAL_ACK_OFFSET(pf_id) */
20 { 0xa80, 0x8, 0x0, 0x0, 0x4},
21 /* USTORM_EQE_CONS_OFFSET(pf_id) */
22 { 0x0, 0x8, 0x0, 0x0, 0x2},
23 /* USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) */
24 { 0x80, 0x8, 0x0, 0x0, 0x4},
25 /* USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) */
26 { 0x84, 0x8, 0x0, 0x0, 0x2},
27 /* XSTORM_INTEG_TEST_DATA_OFFSET */
28 { 0x4c48, 0x0, 0x0, 0x0, 0x78},
29 /* YSTORM_INTEG_TEST_DATA_OFFSET */
30 { 0x3e38, 0x0, 0x0, 0x0, 0x78},
31 /* PSTORM_INTEG_TEST_DATA_OFFSET */
32 { 0x3ef8, 0x0, 0x0, 0x0, 0x78},
33 /* TSTORM_INTEG_TEST_DATA_OFFSET */
34 { 0x4c40, 0x0, 0x0, 0x0, 0x78},
35 /* MSTORM_INTEG_TEST_DATA_OFFSET */
36 { 0x4998, 0x0, 0x0, 0x0, 0x78},
37 /* USTORM_INTEG_TEST_DATA_OFFSET */
38 { 0x7f50, 0x0, 0x0, 0x0, 0x78},
39 /* TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) */
40 { 0xa28, 0x8, 0x0, 0x0, 0x8},
41 /* CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
42 { 0x6210, 0x10, 0x0, 0x0, 0x10},
43 /* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
44 { 0xb820, 0x30, 0x0, 0x0, 0x30},
45 /* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */
46 { 0xa990, 0x30, 0x0, 0x0, 0x30},
47 /* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
48 { 0x4b68, 0x80, 0x0, 0x0, 0x40},
49 /* MSTORM_ETH_PF_PRODS_OFFSET(queue_id) */
50 { 0x1f8, 0x4, 0x0, 0x0, 0x4},
51 /* MSTORM_ETH_VF_PRODS_OFFSET(vf_id,vf_queue_id) */
52 { 0x53a8, 0x80, 0x4, 0x0, 0x4},
53 /* MSTORM_TPA_TIMEOUT_US_OFFSET */
54 { 0xc7d0, 0x0, 0x0, 0x0, 0x4},
55 /* MSTORM_ETH_PF_STAT_OFFSET(pf_id) */
56 { 0x4ba8, 0x80, 0x0, 0x0, 0x20},
57 /* USTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
58 { 0x8158, 0x40, 0x0, 0x0, 0x30},
59 /* USTORM_ETH_PF_STAT_OFFSET(pf_id) */
60 { 0xe770, 0x60, 0x0, 0x0, 0x60},
61 /* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
62 { 0x4090, 0x80, 0x0, 0x0, 0x38},
63 /* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */
64 { 0xfea8, 0x78, 0x0, 0x0, 0x78},
65 /* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) */
66 { 0x1f8, 0x4, 0x0, 0x0, 0x4},
67 /* TSTORM_ETH_PRS_INPUT_OFFSET */
68 { 0xaf20, 0x0, 0x0, 0x0, 0xf0},
69 /* ETH_RX_RATE_LIMIT_OFFSET(pf_id) */
70 { 0xb010, 0x8, 0x0, 0x0, 0x8},
71 /* TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) */
72 { 0xc00, 0x8, 0x0, 0x0, 0x8},
73 /* XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) */
74 { 0x1f8, 0x8, 0x0, 0x0, 0x8},
75 /* YSTORM_TOE_CQ_PROD_OFFSET(rss_id) */
76 { 0xac0, 0x8, 0x0, 0x0, 0x8},
77 /* USTORM_TOE_CQ_PROD_OFFSET(rss_id) */
78 { 0x2578, 0x8, 0x0, 0x0, 0x8},
79 /* USTORM_TOE_GRQ_PROD_OFFSET(pf_id) */
80 { 0x24f8, 0x8, 0x0, 0x0, 0x8},
81 /* TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) */
82 { 0x0, 0x8, 0x0, 0x0, 0x8},
83 /* TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
84 { 0x400, 0x18, 0x8, 0x0, 0x8},
85 /* MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
86 { 0xb78, 0x18, 0x8, 0x0, 0x2},
87 /* TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
88 { 0xd898, 0x50, 0x0, 0x0, 0x3c},
89 /* MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
90 { 0x12908, 0x18, 0x0, 0x0, 0x10},
91 /* USTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
92 { 0x11aa8, 0x40, 0x0, 0x0, 0x18},
93 /* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
94 { 0xa588, 0x50, 0x0, 0x0, 0x20},
95 /* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
96 { 0x8f00, 0x40, 0x0, 0x0, 0x28},
97 /* PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
98 { 0x10e30, 0x18, 0x0, 0x0, 0x10},
99 /* TSTORM_FCOE_RX_STATS_OFFSET(pf_id) */
100 { 0xde48, 0x48, 0x0, 0x0, 0x38},
101 /* PSTORM_FCOE_TX_STATS_OFFSET(pf_id) */
102 { 0x11298, 0x20, 0x0, 0x0, 0x20},
103 /* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
104 { 0x40c8, 0x80, 0x0, 0x0, 0x10},
105 /* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
106 { 0x5048, 0x10, 0x0, 0x0, 0x10},
107 /* XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */
108 { 0xa928, 0x8, 0x0, 0x0, 0x1},
109 /* YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */
110 { 0xa128, 0x8, 0x0, 0x0, 0x1},
111 /* PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */
112 { 0x11a30, 0x8, 0x0, 0x0, 0x1},
113 /* TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */
114 { 0xf030, 0x8, 0x0, 0x0, 0x1},
115 /* MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */
116 { 0x13028, 0x8, 0x0, 0x0, 0x1},
117 /* USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */
118 { 0x12c58, 0x8, 0x0, 0x0, 0x1},
119 /* XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) */
120 { 0xc9b8, 0x30, 0x0, 0x0, 0x10},
121 /* TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) */
122 { 0xed90, 0x28, 0x0, 0x0, 0x28},
123 /* YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) */
124 { 0xad20, 0x18, 0x0, 0x0, 0x18},
125 /* YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) */
126 { 0xaea0, 0x8, 0x0, 0x0, 0x8},
127 /* PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) */
128 { 0x13c38, 0x8, 0x0, 0x0, 0x8},
129 /* USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) */
130 { 0x13c50, 0x18, 0x0, 0x0, 0x18},
133 #endif /* __IRO_VALUES_H__ */