2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
18 #include "ecore_iov_api.h"
19 #include "ecore_gtt_reg_addr.h"
20 #include "ecore_iro.h"
21 #include "ecore_dcbx.h"
23 #define CHIP_MCP_RESP_ITER_US 10
24 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
26 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
27 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
29 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
30 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
33 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
34 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
36 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
37 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
38 OFFSETOF(struct public_drv_mb, _field), _val)
40 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
41 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
42 OFFSETOF(struct public_drv_mb, _field))
44 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
45 DRV_ID_PDA_COMP_VER_SHIFT)
47 #define MCP_BYTES_PER_MBIT_SHIFT 17
51 static int loaded_port[MAX_NUM_PORTS] = { 0 };
54 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
56 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
61 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
63 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
65 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
67 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
69 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
70 "port_addr = 0x%x, port_id 0x%02x\n",
71 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
74 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
76 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
81 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
85 if (!p_hwfn->mcp_info->public_base)
88 for (i = 0; i < length; i++) {
89 tmp = ecore_rd(p_hwfn, p_ptt,
90 p_hwfn->mcp_info->mfw_mb_addr +
91 (i << 2) + sizeof(u32));
93 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
94 OSAL_BE32_TO_CPU(tmp);
98 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
100 if (p_hwfn->mcp_info) {
101 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
102 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
103 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
105 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
106 p_hwfn->mcp_info = OSAL_NULL;
108 return ECORE_SUCCESS;
111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
112 struct ecore_ptt *p_ptt)
114 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
115 u32 drv_mb_offsize, mfw_mb_offsize;
116 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
119 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
120 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
121 p_info->public_base = 0;
126 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
127 if (!p_info->public_base)
130 p_info->public_base |= GRCBASE_MCP;
132 /* Calculate the driver and MFW mailbox address */
133 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
134 SECTION_OFFSIZE_ADDR(p_info->public_base,
136 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
137 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
138 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
139 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
141 /* Set the MFW MB address */
142 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
143 SECTION_OFFSIZE_ADDR(p_info->public_base,
145 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
146 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
147 p_info->mfw_mb_addr);
149 /* Get the current driver mailbox sequence before sending
152 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
153 DRV_MSG_SEQ_NUMBER_MASK;
155 /* Get current FW pulse sequence */
156 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
159 p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
160 MISCS_REG_GENERIC_POR_0);
162 return ECORE_SUCCESS;
165 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
166 struct ecore_ptt *p_ptt)
168 struct ecore_mcp_info *p_info;
171 /* Allocate mcp_info structure */
172 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
173 sizeof(*p_hwfn->mcp_info));
174 if (!p_hwfn->mcp_info)
176 p_info = p_hwfn->mcp_info;
178 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
179 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
180 /* Do not free mcp_info here, since public_base indicate that
181 * the MCP is not initialized
183 return ECORE_SUCCESS;
186 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
187 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
188 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
189 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
192 /* Initialize the MFW spinlock */
193 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
194 OSAL_SPIN_LOCK_INIT(&p_info->lock);
196 return ECORE_SUCCESS;
199 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
200 ecore_mcp_free(p_hwfn);
204 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
205 struct ecore_ptt *p_ptt)
207 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
208 u32 delay = CHIP_MCP_RESP_ITER_US;
209 u32 org_mcp_reset_seq, cnt = 0;
210 enum _ecore_status_t rc = ECORE_SUCCESS;
213 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
214 delay = EMUL_MCP_RESP_ITER_US;
217 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
219 /* Set drv command along with the updated sequence */
220 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
221 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
224 /* Wait for MFW response */
226 /* Give the FW up to 500 second (50*1000*10usec) */
227 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
228 MISCS_REG_GENERIC_POR_0)) &&
229 (cnt++ < ECORE_MCP_RESET_RETRIES));
231 if (org_mcp_reset_seq !=
232 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
233 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
234 "MCP was reset after %d usec\n", cnt * delay);
236 DP_ERR(p_hwfn, "Failed to reset MCP\n");
240 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
245 /* Should be called while the dedicated spinlock is acquired */
246 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
247 struct ecore_ptt *p_ptt,
252 u32 delay = CHIP_MCP_RESP_ITER_US;
253 u32 seq, cnt = 1, actual_mb_seq;
254 enum _ecore_status_t rc = ECORE_SUCCESS;
257 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
258 delay = EMUL_MCP_RESP_ITER_US;
261 /* Get actual driver mailbox sequence */
262 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
263 DRV_MSG_SEQ_NUMBER_MASK;
265 /* Use MCP history register to check if MCP reset occurred between
268 if (p_hwfn->mcp_info->mcp_hist !=
269 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
270 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
271 ecore_load_mcp_offsets(p_hwfn, p_ptt);
272 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
274 seq = ++p_hwfn->mcp_info->drv_mb_seq;
277 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
279 /* Set drv command along with the updated sequence */
280 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
282 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
283 "wrote command (%x) to MFW MB param 0x%08x\n",
287 /* Wait for MFW response */
289 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
291 /* Give the FW up to 5 second (500*10ms) */
292 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
293 (cnt++ < ECORE_DRV_MB_MAX_RETRIES));
295 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
296 "[after %d ms] read (%x) seq is (%x) from FW MB\n",
297 cnt * delay, *o_mcp_resp, seq);
299 /* Is this a reply to our command? */
300 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
301 *o_mcp_resp &= FW_MSG_CODE_MASK;
302 /* Get the MCP param */
303 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
306 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
310 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
315 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
316 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
317 u32 *o_mcp_resp, u32 *o_mcp_param)
320 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
321 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
323 loaded_port[p_hwfn->port_id]--;
324 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
327 return ECORE_SUCCESS;
331 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, cmd, param, OSAL_NULL,
332 o_mcp_resp, o_mcp_param);
335 enum _ecore_status_t ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
336 struct ecore_ptt *p_ptt,
338 union drv_union_data *p_union_data,
343 enum _ecore_status_t rc;
345 /* MCP not initialized */
346 if (!ecore_mcp_is_init(p_hwfn)) {
347 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
351 /* Acquiring a spinlock is needed to ensure that only a single thread
352 * is accessing the mailbox at a certain time.
354 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
356 if (p_union_data != OSAL_NULL) {
357 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
358 OFFSETOF(struct public_drv_mb, union_data);
359 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, p_union_data,
360 sizeof(*p_union_data));
363 rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, cmd, param, o_mcp_resp,
366 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
371 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
372 struct ecore_ptt *p_ptt,
377 u32 i_txn_size, u32 *i_buf)
379 union drv_union_data union_data;
381 OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
383 return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, cmd, param, &union_data,
384 o_mcp_resp, o_mcp_param);
387 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
388 struct ecore_ptt *p_ptt,
393 u32 *o_txn_size, u32 *o_buf)
395 enum _ecore_status_t rc;
398 /* MCP not initialized */
399 if (!ecore_mcp_is_init(p_hwfn)) {
400 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
404 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
405 rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, cmd, param, o_mcp_resp,
407 if (rc != ECORE_SUCCESS)
410 /* Get payload after operation completes successfully */
411 *o_txn_size = *o_mcp_param;
412 for (i = 0; i < *o_txn_size; i += 4)
413 o_buf[i / sizeof(u32)] = DRV_MB_RD(p_hwfn, p_ptt,
414 union_data.raw_data[i]);
417 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
422 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
425 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
428 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
429 else if (!loaded_port[p_hwfn->port_id])
430 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
432 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
434 /* On CMT, always tell that it's engine */
435 if (p_hwfn->p_dev->num_hwfns > 1)
436 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
438 *p_load_code = load_phase;
440 loaded_port[p_hwfn->port_id]++;
442 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
443 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
444 *p_load_code, loaded, p_hwfn->port_id,
445 loaded_port[p_hwfn->port_id]);
449 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
450 struct ecore_ptt *p_ptt,
453 struct ecore_dev *p_dev = p_hwfn->p_dev;
454 union drv_union_data union_data;
456 enum _ecore_status_t rc;
459 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
460 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
461 return ECORE_SUCCESS;
465 OSAL_MEMCPY(&union_data.ver_str, p_dev->ver_str, MCP_DRV_VER_STR_SIZE);
467 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_REQ,
468 (PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
470 &union_data, p_load_code, ¶m);
472 /* if mcp fails to respond we must abort */
473 if (rc != ECORE_SUCCESS) {
474 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
478 /* If MFW refused (e.g. other port is in diagnostic mode) we
479 * must abort. This can happen in the following cases:
480 * - Other port is in diagnostic mode
481 * - Previously loaded function on the engine is not compliant with
483 * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
486 if (!(*p_load_code) ||
487 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
488 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
489 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
490 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
494 return ECORE_SUCCESS;
497 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
498 struct ecore_ptt *p_ptt)
500 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
502 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
503 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
504 ECORE_PATH_ID(p_hwfn));
505 u32 disabled_vfs[VF_MAX_STATIC / 32];
508 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
509 "Reading Disabled VF information from [offset %08x],"
511 mfw_path_offsize, path_addr);
513 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
514 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
516 OFFSETOF(struct public_path,
519 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
520 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
521 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
524 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
525 OSAL_VF_FLR_UPDATE(p_hwfn);
528 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
529 struct ecore_ptt *p_ptt,
532 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
534 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
535 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
537 union drv_union_data union_data;
539 enum _ecore_status_t rc;
542 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
543 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
544 "Acking VFs [%08x,...,%08x] - %08x\n",
545 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
547 OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
549 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
550 DRV_MSG_CODE_VF_DISABLED_DONE, 0,
551 &union_data, &resp, ¶m);
552 if (rc != ECORE_SUCCESS) {
553 DP_NOTICE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
554 "Failed to pass ACK for VF flr to MFW\n");
555 return ECORE_TIMEOUT;
558 /* TMP - clear the ACK bits; should be done by MFW */
559 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
560 ecore_wr(p_hwfn, p_ptt,
562 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
568 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
569 struct ecore_ptt *p_ptt)
571 u32 transceiver_state;
573 transceiver_state = ecore_rd(p_hwfn, p_ptt,
574 p_hwfn->mcp_info->port_addr +
575 OFFSETOF(struct public_port,
578 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
579 "Received transceiver state update [0x%08x] from mfw"
581 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
582 OFFSETOF(struct public_port,
585 transceiver_state = GET_FIELD(transceiver_state, PMM_TRANSCEIVER_STATE);
587 if (transceiver_state == PMM_TRANSCEIVER_STATE_PRESENT)
588 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
590 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
593 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
594 struct ecore_ptt *p_ptt, bool b_reset)
596 struct ecore_mcp_link_state *p_link;
599 p_link = &p_hwfn->mcp_info->link_output;
600 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
602 status = ecore_rd(p_hwfn, p_ptt,
603 p_hwfn->mcp_info->port_addr +
604 OFFSETOF(struct public_port, link_status));
605 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
606 "Received link update [0x%08x] from mfw"
608 status, (u32)(p_hwfn->mcp_info->port_addr +
609 OFFSETOF(struct public_port,
612 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
613 "Resetting link indications\n");
617 if (p_hwfn->b_drv_link_init)
618 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
620 p_link->link_up = false;
622 p_link->full_duplex = true;
623 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
624 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
625 p_link->speed = 100000;
627 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
628 p_link->speed = 50000;
630 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
631 p_link->speed = 40000;
633 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
634 p_link->speed = 25000;
636 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
637 p_link->speed = 20000;
639 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
640 p_link->speed = 10000;
642 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
643 p_link->full_duplex = false;
645 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
646 p_link->speed = 1000;
652 /* We never store total line speed as p_link->speed is
653 * again changes according to bandwidth allocation.
655 if (p_link->link_up && p_link->speed)
656 p_link->line_speed = p_link->speed;
658 p_link->line_speed = 0;
660 /* Correct speed according to bandwidth allocation */
661 if (p_hwfn->mcp_info->func_info.bandwidth_max && p_link->speed) {
662 u8 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
664 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
668 if (p_hwfn->mcp_info->func_info.bandwidth_min && p_link->speed) {
669 u8 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
671 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
674 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
675 p_link->min_pf_rate);
678 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
679 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
680 p_link->parallel_detection = !!(status &
681 LINK_STATUS_PARALLEL_DETECTION_USED);
682 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
684 p_link->partner_adv_speed |=
685 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
686 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
687 p_link->partner_adv_speed |=
688 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
689 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
690 p_link->partner_adv_speed |=
691 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
692 ECORE_LINK_PARTNER_SPEED_10G : 0;
693 p_link->partner_adv_speed |=
694 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
695 ECORE_LINK_PARTNER_SPEED_20G : 0;
696 p_link->partner_adv_speed |=
697 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
698 ECORE_LINK_PARTNER_SPEED_25G : 0;
699 p_link->partner_adv_speed |=
700 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
701 ECORE_LINK_PARTNER_SPEED_40G : 0;
702 p_link->partner_adv_speed |=
703 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
704 ECORE_LINK_PARTNER_SPEED_50G : 0;
705 p_link->partner_adv_speed |=
706 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
707 ECORE_LINK_PARTNER_SPEED_100G : 0;
709 p_link->partner_tx_flow_ctrl_en =
710 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
711 p_link->partner_rx_flow_ctrl_en =
712 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
714 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
715 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
716 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
718 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
719 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
721 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
722 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
725 p_link->partner_adv_pause = 0;
728 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
731 ecore_dcbx_eagle_workaround(p_hwfn, p_ptt, p_link->pfc_enabled);
733 OSAL_LINK_UPDATE(p_hwfn);
736 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
737 struct ecore_ptt *p_ptt, bool b_up)
739 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
740 union drv_union_data union_data;
741 struct pmm_phy_cfg *p_phy_cfg;
742 u32 param = 0, reply = 0, cmd;
743 enum _ecore_status_t rc = ECORE_SUCCESS;
746 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
747 return ECORE_SUCCESS;
750 /* Set the shmem configuration according to params */
751 p_phy_cfg = &union_data.drv_phy_cfg;
752 OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
753 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
754 if (!params->speed.autoneg)
755 p_phy_cfg->speed = params->speed.forced_speed;
756 p_phy_cfg->pause |= (params->pause.autoneg) ? PMM_PAUSE_AUTONEG : 0;
757 p_phy_cfg->pause |= (params->pause.forced_rx) ? PMM_PAUSE_RX : 0;
758 p_phy_cfg->pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0;
759 p_phy_cfg->adv_speed = params->speed.advertised_speeds;
760 p_phy_cfg->loopback_mode = params->loopback_mode;
763 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
765 "Link on FPGA - Ask for loopback mode '5' at 10G\n");
766 p_phy_cfg->loopback_mode = 5;
767 p_phy_cfg->speed = 10000;
771 p_hwfn->b_drv_link_init = b_up;
774 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
775 "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
776 " adv_speed 0x%08x, loopback 0x%08x,"
777 " features 0x%08x\n",
778 p_phy_cfg->speed, p_phy_cfg->pause,
779 p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode,
780 p_phy_cfg->feature_config_flags);
782 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
784 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, cmd, 0, &union_data, &reply,
787 /* if mcp fails to respond we must abort */
788 if (rc != ECORE_SUCCESS) {
789 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
793 /* Reset the link status if needed */
795 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
800 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
801 struct ecore_ptt *p_ptt)
803 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
805 /* TODO - Add support for VFs */
806 if (IS_VF(p_hwfn->p_dev))
809 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
811 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
812 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
814 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
816 OFFSETOF(struct public_path, process_kill)) &
817 PROCESS_KILL_COUNTER_MASK;
819 return proc_kill_cnt;
822 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
823 struct ecore_ptt *p_ptt)
825 struct ecore_dev *p_dev = p_hwfn->p_dev;
828 /* Prevent possible attentions/interrupts during the recovery handling
829 * and till its load phase, during which they will be re-enabled.
831 ecore_int_igu_disable_int(p_hwfn, p_ptt);
833 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
835 /* The following operations should be done once, and thus in CMT mode
836 * are carried out by only the first HW function.
838 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
841 if (p_dev->recov_in_prog) {
842 DP_NOTICE(p_hwfn, false,
843 "Ignoring the indication since a recovery"
844 " process is already in progress\n");
848 p_dev->recov_in_prog = true;
850 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
851 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
853 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
856 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
857 struct ecore_ptt *p_ptt,
858 enum MFW_DRV_MSG_TYPE type)
860 enum ecore_mcp_protocol_type stats_type;
861 union ecore_mcp_protocol_stats stats;
862 u32 hsi_param, param = 0, reply = 0;
863 union drv_union_data union_data;
866 case MFW_DRV_MSG_GET_LAN_STATS:
867 stats_type = ECORE_MCP_LAN_STATS;
868 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
871 DP_NOTICE(p_hwfn, false, "Invalid protocol type %d\n", type);
875 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
877 OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
879 ecore_mcp_cmd_and_union(p_hwfn, p_ptt, DRV_MSG_CODE_GET_STATS,
880 hsi_param, &union_data, &reply, ¶m);
883 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
884 struct ecore_ptt *p_ptt,
885 struct public_func *p_data, int pfid)
887 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
889 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
890 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
893 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
895 size = OSAL_MIN_T(u32, sizeof(*p_data), SECTION_SIZE(mfw_path_offsize));
896 for (i = 0; i < size / sizeof(u32); i++)
897 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
898 func_addr + (i << 2));
904 ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
905 struct public_func *p_shmem_info)
907 struct ecore_mcp_function_info *p_info;
909 p_info = &p_hwfn->mcp_info->func_info;
911 /* TODO - bandwidth min/max should have valid values of 1-100,
912 * as well as some indication that the feature is disabled.
913 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
914 * limit and correct value to min `1' and max `100' if limit isn't in
917 p_info->bandwidth_min = (p_shmem_info->config &
918 FUNC_MF_CFG_MIN_BW_MASK) >>
919 FUNC_MF_CFG_MIN_BW_SHIFT;
920 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
922 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
923 p_info->bandwidth_min);
924 p_info->bandwidth_min = 1;
927 p_info->bandwidth_max = (p_shmem_info->config &
928 FUNC_MF_CFG_MAX_BW_MASK) >>
929 FUNC_MF_CFG_MAX_BW_SHIFT;
930 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
932 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
933 p_info->bandwidth_max);
934 p_info->bandwidth_max = 100;
939 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
941 struct ecore_mcp_function_info *p_info;
942 struct public_func shmem_info;
943 u32 resp = 0, param = 0;
945 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
947 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
949 p_info = &p_hwfn->mcp_info->func_info;
951 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
953 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
955 /* Acknowledge the MFW */
956 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
960 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
961 struct ecore_ptt *p_ptt)
963 /* A single notification should be sent to upper driver in CMT mode */
964 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
967 DP_NOTICE(p_hwfn, false,
968 "Fan failure was detected on the network interface card"
969 " and it's going to be shut down.\n");
971 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
974 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
975 struct ecore_ptt *p_ptt)
977 struct ecore_mcp_info *info = p_hwfn->mcp_info;
978 enum _ecore_status_t rc = ECORE_SUCCESS;
982 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
984 /* Read Messages from MFW */
985 ecore_mcp_read_mb(p_hwfn, p_ptt);
987 /* Compare current messages to old ones */
988 for (i = 0; i < info->mfw_mb_length; i++) {
989 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
994 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
995 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
996 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
999 case MFW_DRV_MSG_LINK_CHANGE:
1000 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1002 case MFW_DRV_MSG_VF_DISABLED:
1003 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1005 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1006 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1007 ECORE_DCBX_REMOTE_LLDP_MIB);
1009 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1010 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1011 ECORE_DCBX_REMOTE_MIB);
1013 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1014 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1015 ECORE_DCBX_OPERATIONAL_MIB);
1017 case MFW_DRV_MSG_ERROR_RECOVERY:
1018 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1020 case MFW_DRV_MSG_GET_LAN_STATS:
1021 case MFW_DRV_MSG_GET_FCOE_STATS:
1022 case MFW_DRV_MSG_GET_ISCSI_STATS:
1023 case MFW_DRV_MSG_GET_RDMA_STATS:
1024 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1026 case MFW_DRV_MSG_BW_UPDATE:
1027 ecore_mcp_update_bw(p_hwfn, p_ptt);
1029 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1030 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1032 case MFW_DRV_MSG_FAILURE_DETECTED:
1033 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1037 DP_NOTICE(p_hwfn, false,
1038 "Unimplemented MFW message %d\n", i);
1043 /* ACK everything */
1044 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1045 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1047 /* MFW expect answer in BE, so we force write in that format */
1048 ecore_wr(p_hwfn, p_ptt,
1049 info->mfw_mb_addr + sizeof(u32) +
1050 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1051 sizeof(u32) + i * sizeof(u32), val);
1055 DP_NOTICE(p_hwfn, false,
1056 "Received an MFW message indication but no"
1061 /* Copy the new mfw messages into the shadow */
1062 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1067 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev,
1068 struct ecore_ptt *p_ptt,
1070 u32 *p_running_bundle_id)
1072 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1076 if (CHIP_REV_IS_EMUL(p_dev)) {
1077 DP_NOTICE(p_dev, false, "Emulation - can't get MFW version\n");
1078 return ECORE_SUCCESS;
1083 if (p_hwfn->vf_iov_info) {
1084 struct pfvf_acquire_resp_tlv *p_resp;
1086 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1087 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1088 return ECORE_SUCCESS;
1091 DP_VERBOSE(p_dev, ECORE_MSG_IOV,
1092 "VF requested MFW vers prior to ACQUIRE\n");
1096 global_offsize = ecore_rd(p_hwfn, p_ptt,
1097 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1101 ecore_rd(p_hwfn, p_ptt,
1102 SECTION_ADDR(global_offsize,
1103 0) + OFFSETOF(struct public_global, mfw_ver));
1105 if (p_running_bundle_id != OSAL_NULL) {
1106 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1107 SECTION_ADDR(global_offsize,
1109 OFFSETOF(struct public_global,
1110 running_bundle_id));
1113 return ECORE_SUCCESS;
1116 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1119 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1120 struct ecore_ptt *p_ptt;
1122 /* TODO - Add support for VFs */
1126 if (!ecore_mcp_is_init(p_hwfn)) {
1127 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1131 *p_media_type = MEDIA_UNSPECIFIED;
1133 p_ptt = ecore_ptt_acquire(p_hwfn);
1137 *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1138 OFFSETOF(struct public_port, media_type));
1140 ecore_ptt_release(p_hwfn, p_ptt);
1142 return ECORE_SUCCESS;
1145 static enum _ecore_status_t
1146 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1147 struct public_func *p_info,
1148 enum ecore_pci_personality *p_proto)
1150 enum _ecore_status_t rc = ECORE_SUCCESS;
1152 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1153 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1154 *p_proto = ECORE_PCI_ETH;
1163 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1164 struct ecore_ptt *p_ptt)
1166 struct ecore_mcp_function_info *info;
1167 struct public_func shmem_info;
1169 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1170 info = &p_hwfn->mcp_info->func_info;
1172 info->pause_on_host = (shmem_info.config &
1173 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1175 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1176 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1177 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1181 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1183 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1184 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1185 info->mac[1] = (u8)(shmem_info.mac_upper);
1186 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1187 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1188 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1189 info->mac[5] = (u8)(shmem_info.mac_lower);
1191 /* TODO - are there protocols for which there's no MAC? */
1192 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1195 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1197 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1198 "Read configuration from shmem: pause_on_host %02x"
1199 " protocol %02x BW [%02x - %02x]"
1200 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %" PRIx64
1201 " node %" PRIx64 " ovlan %04x\n",
1202 info->pause_on_host, info->protocol,
1203 info->bandwidth_min, info->bandwidth_max,
1204 info->mac[0], info->mac[1], info->mac[2],
1205 info->mac[3], info->mac[4], info->mac[5],
1206 info->wwn_port, info->wwn_node, info->ovlan);
1208 return ECORE_SUCCESS;
1211 struct ecore_mcp_link_params
1212 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1214 if (!p_hwfn || !p_hwfn->mcp_info)
1216 return &p_hwfn->mcp_info->link_input;
1219 struct ecore_mcp_link_state
1220 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1222 if (!p_hwfn || !p_hwfn->mcp_info)
1226 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1227 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1228 p_hwfn->mcp_info->link_output.link_up = true;
1232 return &p_hwfn->mcp_info->link_output;
1235 struct ecore_mcp_link_capabilities
1236 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1238 if (!p_hwfn || !p_hwfn->mcp_info)
1240 return &p_hwfn->mcp_info->link_capabilities;
1243 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1244 struct ecore_ptt *p_ptt)
1246 enum _ecore_status_t rc;
1247 u32 resp = 0, param = 0;
1249 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1250 DRV_MSG_CODE_NIG_DRAIN, 100, &resp, ¶m);
1252 /* Wait for the drain to complete before returning */
1258 const struct ecore_mcp_function_info
1259 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1261 if (!p_hwfn || !p_hwfn->mcp_info)
1263 return &p_hwfn->mcp_info->func_info;
1266 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1267 struct ecore_ptt *p_ptt,
1268 struct ecore_mcp_nvm_params *params)
1270 enum _ecore_status_t rc;
1272 switch (params->type) {
1273 case ECORE_MCP_NVM_RD:
1274 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1275 params->nvm_common.offset,
1276 ¶ms->nvm_common.resp,
1277 ¶ms->nvm_common.param,
1278 params->nvm_rd.buf_size,
1279 params->nvm_rd.buf);
1282 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1283 params->nvm_common.offset,
1284 ¶ms->nvm_common.resp,
1285 ¶ms->nvm_common.param);
1287 case ECORE_MCP_NVM_WR:
1288 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1289 params->nvm_common.offset,
1290 ¶ms->nvm_common.resp,
1291 ¶ms->nvm_common.param,
1292 params->nvm_wr.buf_size,
1293 params->nvm_wr.buf);
1302 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1303 struct ecore_ptt *p_ptt, u32 personalities)
1305 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1306 struct public_func shmem_info;
1307 int i, count = 0, num_pfs;
1309 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1311 for (i = 0; i < num_pfs; i++) {
1312 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1313 MCP_PF_ID_BY_REL(p_hwfn, i));
1314 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1317 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info,
1318 &protocol) != ECORE_SUCCESS)
1321 if ((1 << ((u32)protocol)) & personalities)
1328 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1329 struct ecore_ptt *p_ptt,
1335 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1336 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1341 if (IS_VF(p_hwfn->p_dev))
1344 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1345 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1346 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1347 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1349 *p_flash_size = flash_size;
1351 return ECORE_SUCCESS;
1354 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1355 struct ecore_ptt *p_ptt)
1357 struct ecore_dev *p_dev = p_hwfn->p_dev;
1359 if (p_dev->recov_in_prog) {
1360 DP_NOTICE(p_hwfn, false,
1361 "Avoid triggering a recovery since such a process"
1362 " is already in progress\n");
1366 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1367 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1369 return ECORE_SUCCESS;
1372 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1373 struct ecore_ptt *p_ptt,
1376 u32 resp = 0, param = 0, rc_param = 0;
1377 enum _ecore_status_t rc;
1379 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1380 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1381 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1382 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1384 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1387 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1388 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1396 enum _ecore_status_t
1397 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1398 struct ecore_mcp_drv_version *p_ver)
1400 u32 param = 0, reply = 0, num_words, i;
1401 struct drv_version_stc *p_drv_version;
1402 union drv_union_data union_data;
1405 enum _ecore_status_t rc;
1408 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1409 return ECORE_SUCCESS;
1412 p_drv_version = &union_data.drv_version;
1413 p_drv_version->version = p_ver->version;
1414 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1415 for (i = 0; i < num_words; i++) {
1416 p_name = &p_ver->name[i * sizeof(u32)];
1417 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1418 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1421 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, DRV_MSG_CODE_SET_VERSION, 0,
1422 &union_data, &reply, ¶m);
1423 if (rc != ECORE_SUCCESS)
1424 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1429 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1430 struct ecore_ptt *p_ptt)
1432 enum _ecore_status_t rc;
1433 u32 resp = 0, param = 0;
1435 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1437 if (rc != ECORE_SUCCESS)
1438 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1443 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1444 struct ecore_ptt *p_ptt)
1446 u32 value, cpu_mode;
1448 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1450 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1451 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1452 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1453 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1455 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1458 enum _ecore_status_t
1459 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1460 struct ecore_ptt *p_ptt,
1461 enum ecore_ov_config_method config,
1462 enum ecore_ov_client client)
1464 enum _ecore_status_t rc;
1465 u32 resp = 0, param = 0;
1469 case ECORE_OV_CLIENT_DRV:
1470 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1472 case ECORE_OV_CLIENT_USER:
1473 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1476 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", config);
1480 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1481 drv_mb_param, &resp, ¶m);
1482 if (rc != ECORE_SUCCESS)
1483 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1488 enum _ecore_status_t
1489 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1490 struct ecore_ptt *p_ptt,
1491 enum ecore_ov_driver_state drv_state)
1493 enum _ecore_status_t rc;
1494 u32 resp = 0, param = 0;
1497 switch (drv_state) {
1498 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1499 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1501 case ECORE_OV_DRIVER_STATE_DISABLED:
1502 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1504 case ECORE_OV_DRIVER_STATE_ACTIVE:
1505 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1508 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1512 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1513 drv_state, &resp, ¶m);
1514 if (rc != ECORE_SUCCESS)
1515 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1520 enum _ecore_status_t
1521 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1522 struct ecore_fc_npiv_tbl *p_table)
1527 enum _ecore_status_t
1528 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1529 struct ecore_ptt *p_ptt, u16 mtu)
1534 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1535 struct ecore_ptt *p_ptt,
1536 enum ecore_led_mode mode)
1538 u32 resp = 0, param = 0, drv_mb_param;
1539 enum _ecore_status_t rc;
1542 case ECORE_LED_MODE_ON:
1543 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1545 case ECORE_LED_MODE_OFF:
1546 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1548 case ECORE_LED_MODE_RESTORE:
1549 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1552 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1556 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1557 drv_mb_param, &resp, ¶m);
1558 if (rc != ECORE_SUCCESS)
1559 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1564 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1565 struct ecore_ptt *p_ptt,
1568 enum _ecore_status_t rc;
1569 u32 resp = 0, param = 0;
1571 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1572 mask_parities, &resp, ¶m);
1574 if (rc != ECORE_SUCCESS) {
1576 "MCP response failure for mask parities, aborting\n");
1577 } else if (resp != FW_MSG_CODE_OK) {
1579 "MCP did not ack mask parity request. Old MFW?\n");
1586 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1589 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1590 u32 bytes_left, offset, bytes_to_copy, buf_size;
1591 struct ecore_mcp_nvm_params params;
1592 struct ecore_ptt *p_ptt;
1593 enum _ecore_status_t rc = ECORE_SUCCESS;
1595 p_ptt = ecore_ptt_acquire(p_hwfn);
1599 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1602 params.type = ECORE_MCP_NVM_RD;
1603 params.nvm_rd.buf_size = &buf_size;
1604 params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1605 while (bytes_left > 0) {
1606 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1607 MCP_DRV_NVM_BUF_LEN);
1608 params.nvm_common.offset = (addr + offset) |
1609 (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1610 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1611 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1612 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1613 FW_MSG_CODE_NVM_OK)) {
1614 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1617 offset += *params.nvm_rd.buf_size;
1618 bytes_left -= *params.nvm_rd.buf_size;
1621 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1622 ecore_ptt_release(p_hwfn, p_ptt);
1627 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1628 u32 addr, u8 *p_buf, u32 len)
1630 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1631 struct ecore_mcp_nvm_params params;
1632 struct ecore_ptt *p_ptt;
1633 enum _ecore_status_t rc;
1635 p_ptt = ecore_ptt_acquire(p_hwfn);
1639 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1640 params.type = ECORE_MCP_NVM_RD;
1641 params.nvm_rd.buf_size = &len;
1642 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1643 DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1644 params.nvm_common.offset = addr;
1645 params.nvm_rd.buf = (u32 *)p_buf;
1646 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1647 if (rc != ECORE_SUCCESS)
1648 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1650 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1651 ecore_ptt_release(p_hwfn, p_ptt);
1656 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1658 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1659 struct ecore_mcp_nvm_params params;
1660 struct ecore_ptt *p_ptt;
1662 p_ptt = ecore_ptt_acquire(p_hwfn);
1666 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1667 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1668 ecore_ptt_release(p_hwfn, p_ptt);
1670 return ECORE_SUCCESS;
1673 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1675 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1676 struct ecore_mcp_nvm_params params;
1677 struct ecore_ptt *p_ptt;
1678 enum _ecore_status_t rc;
1680 p_ptt = ecore_ptt_acquire(p_hwfn);
1683 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1684 params.type = ECORE_MCP_CMD;
1685 params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1686 params.nvm_common.offset = addr;
1687 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1688 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1689 ecore_ptt_release(p_hwfn, p_ptt);
1694 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1697 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1698 struct ecore_mcp_nvm_params params;
1699 struct ecore_ptt *p_ptt;
1700 enum _ecore_status_t rc;
1702 p_ptt = ecore_ptt_acquire(p_hwfn);
1705 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1706 params.type = ECORE_MCP_CMD;
1707 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
1708 params.nvm_common.offset = addr;
1709 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1710 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1711 ecore_ptt_release(p_hwfn, p_ptt);
1716 /* rc receives ECORE_INVAL as default parameter because
1717 * it might not enter the while loop if the len is 0
1719 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
1720 u32 addr, u8 *p_buf, u32 len)
1722 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1723 enum _ecore_status_t rc = ECORE_INVAL;
1724 struct ecore_mcp_nvm_params params;
1725 struct ecore_ptt *p_ptt;
1726 u32 buf_idx, buf_size;
1728 p_ptt = ecore_ptt_acquire(p_hwfn);
1732 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1733 params.type = ECORE_MCP_NVM_WR;
1734 if (cmd == ECORE_PUT_FILE_DATA)
1735 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
1737 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
1739 while (buf_idx < len) {
1740 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
1741 MCP_DRV_NVM_BUF_LEN);
1742 params.nvm_common.offset = ((buf_size <<
1743 DRV_MB_PARAM_NVM_LEN_SHIFT)
1745 params.nvm_wr.buf_size = buf_size;
1746 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
1747 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1748 if (rc != ECORE_SUCCESS ||
1749 ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
1750 (params.nvm_common.resp !=
1751 FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
1752 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1754 buf_idx += buf_size;
1757 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1758 ecore_ptt_release(p_hwfn, p_ptt);
1763 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
1764 u32 addr, u8 *p_buf, u32 len)
1766 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1767 struct ecore_mcp_nvm_params params;
1768 struct ecore_ptt *p_ptt;
1769 enum _ecore_status_t rc;
1771 p_ptt = ecore_ptt_acquire(p_hwfn);
1775 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1776 params.type = ECORE_MCP_NVM_WR;
1777 params.nvm_wr.buf_size = len;
1778 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
1779 DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
1780 params.nvm_common.offset = addr;
1781 params.nvm_wr.buf = (u32 *)p_buf;
1782 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1783 if (rc != ECORE_SUCCESS)
1784 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1785 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1786 ecore_ptt_release(p_hwfn, p_ptt);
1791 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
1794 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1795 struct ecore_mcp_nvm_params params;
1796 struct ecore_ptt *p_ptt;
1797 enum _ecore_status_t rc;
1799 p_ptt = ecore_ptt_acquire(p_hwfn);
1803 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1804 params.type = ECORE_MCP_CMD;
1805 params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
1806 params.nvm_common.offset = addr;
1807 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1808 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1809 ecore_ptt_release(p_hwfn, p_ptt);
1814 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
1815 struct ecore_ptt *p_ptt,
1816 u32 port, u32 addr, u32 offset,
1819 struct ecore_mcp_nvm_params params;
1820 enum _ecore_status_t rc;
1821 u32 bytes_left, bytes_to_copy, buf_size;
1823 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1824 SET_FIELD(params.nvm_common.offset,
1825 DRV_MB_PARAM_TRANSCEIVER_PORT, port);
1826 SET_FIELD(params.nvm_common.offset,
1827 DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS, addr);
1831 params.type = ECORE_MCP_NVM_RD;
1832 params.nvm_rd.buf_size = &buf_size;
1833 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
1834 while (bytes_left > 0) {
1835 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1836 MAX_I2C_TRANSACTION_SIZE);
1837 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1838 SET_FIELD(params.nvm_common.offset,
1839 DRV_MB_PARAM_TRANSCEIVER_OFFSET, addr + offset);
1840 SET_FIELD(params.nvm_common.offset,
1841 DRV_MB_PARAM_TRANSCEIVER_SIZE, bytes_to_copy);
1842 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1843 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
1844 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
1846 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
1847 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
1848 return ECORE_UNKNOWN_ERROR;
1850 offset += *params.nvm_rd.buf_size;
1851 bytes_left -= *params.nvm_rd.buf_size;
1854 return ECORE_SUCCESS;
1857 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
1858 struct ecore_ptt *p_ptt,
1859 u32 port, u32 addr, u32 offset,
1862 struct ecore_mcp_nvm_params params;
1863 enum _ecore_status_t rc;
1864 u32 buf_idx, buf_size;
1866 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1867 SET_FIELD(params.nvm_common.offset,
1868 DRV_MB_PARAM_TRANSCEIVER_PORT, port);
1869 SET_FIELD(params.nvm_common.offset,
1870 DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS, addr);
1871 params.type = ECORE_MCP_NVM_WR;
1872 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
1874 while (buf_idx < len) {
1875 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
1876 MAX_I2C_TRANSACTION_SIZE);
1877 SET_FIELD(params.nvm_common.offset,
1878 DRV_MB_PARAM_TRANSCEIVER_OFFSET, offset + buf_idx);
1879 SET_FIELD(params.nvm_common.offset,
1880 DRV_MB_PARAM_TRANSCEIVER_SIZE, buf_size);
1881 params.nvm_wr.buf_size = buf_size;
1882 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
1883 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1884 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
1885 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
1887 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
1888 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
1889 return ECORE_UNKNOWN_ERROR;
1891 buf_idx += buf_size;
1894 return ECORE_SUCCESS;
1897 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
1898 struct ecore_ptt *p_ptt,
1899 u16 gpio, u32 *gpio_val)
1901 enum _ecore_status_t rc = ECORE_SUCCESS;
1902 u32 drv_mb_param = 0, rsp;
1904 SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_NUMBER, gpio);
1906 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
1907 drv_mb_param, &rsp, gpio_val);
1909 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
1910 return ECORE_UNKNOWN_ERROR;
1912 return ECORE_SUCCESS;
1915 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
1916 struct ecore_ptt *p_ptt,
1917 u16 gpio, u16 gpio_val)
1919 enum _ecore_status_t rc = ECORE_SUCCESS;
1920 u32 drv_mb_param = 0, param, rsp;
1922 SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_NUMBER, gpio);
1923 SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_VALUE, gpio_val);
1925 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
1926 drv_mb_param, &rsp, ¶m);
1928 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
1929 return ECORE_UNKNOWN_ERROR;
1931 return ECORE_SUCCESS;