2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 #include "ecore_status.h"
12 #include "ecore_mcp.h"
13 #include "mcp_public.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_sriov.h"
19 #include "ecore_iov_api.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
22 #include "ecore_dcbx.h"
24 #define CHIP_MCP_RESP_ITER_US 10
25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
28 #define ECORE_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
31 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
35 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
38 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
39 OFFSETOF(struct public_drv_mb, _field), _val)
41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
42 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
43 OFFSETOF(struct public_drv_mb, _field))
45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
46 DRV_ID_PDA_COMP_VER_SHIFT)
48 #define MCP_BYTES_PER_MBIT_SHIFT 17
52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
57 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
64 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
66 u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
68 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
70 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
71 "port_addr = 0x%x, port_id 0x%02x\n",
72 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
77 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
82 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
86 if (!p_hwfn->mcp_info->public_base)
89 for (i = 0; i < length; i++) {
90 tmp = ecore_rd(p_hwfn, p_ptt,
91 p_hwfn->mcp_info->mfw_mb_addr +
92 (i << 2) + sizeof(u32));
94 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
95 OSAL_BE32_TO_CPU(tmp);
99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
101 if (p_hwfn->mcp_info) {
102 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
103 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
104 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
106 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
108 return ECORE_SUCCESS;
111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
112 struct ecore_ptt *p_ptt)
114 struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
115 u32 drv_mb_offsize, mfw_mb_offsize;
116 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
119 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
120 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
121 p_info->public_base = 0;
126 p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
127 if (!p_info->public_base)
130 p_info->public_base |= GRCBASE_MCP;
132 /* Calculate the driver and MFW mailbox address */
133 drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
134 SECTION_OFFSIZE_ADDR(p_info->public_base,
136 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
137 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
138 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
139 " mcp_pf_id = 0x%x\n",
140 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
142 /* Set the MFW MB address */
143 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
144 SECTION_OFFSIZE_ADDR(p_info->public_base,
146 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
147 p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
148 p_info->mfw_mb_addr);
150 /* Get the current driver mailbox sequence before sending
153 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
154 DRV_MSG_SEQ_NUMBER_MASK;
156 /* Get current FW pulse sequence */
157 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
160 p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
161 MISCS_REG_GENERIC_POR_0);
163 return ECORE_SUCCESS;
166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
167 struct ecore_ptt *p_ptt)
169 struct ecore_mcp_info *p_info;
172 /* Allocate mcp_info structure */
173 p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
174 sizeof(*p_hwfn->mcp_info));
175 if (!p_hwfn->mcp_info)
177 p_info = p_hwfn->mcp_info;
179 if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
180 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
181 /* Do not free mcp_info here, since public_base indicate that
182 * the MCP is not initialized
184 return ECORE_SUCCESS;
187 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
188 p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
189 p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
190 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
193 /* Initialize the MFW spinlock */
194 OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
195 OSAL_SPIN_LOCK_INIT(&p_info->lock);
197 return ECORE_SUCCESS;
200 DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
201 ecore_mcp_free(p_hwfn);
205 /* Locks the MFW mailbox of a PF to ensure a single access.
206 * The lock is achieved in most cases by holding a spinlock, causing other
207 * threads to wait till a previous access is done.
208 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
209 * access is achieved by setting a blocking flag, which will fail other
210 * competing contexts to send their mailboxes.
212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
215 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
217 /* The spinlock shouldn't be acquired when the mailbox command is
218 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
219 * pending [UN]LOAD_REQ command of another PF together with a spinlock
220 * (i.e. interrupts are disabled) - can lead to a deadlock.
221 * It is assumed that for a single PF, no other mailbox commands can be
222 * sent from another context while sending LOAD_REQ, and that any
223 * parallel commands to UNLOAD_REQ can be cancelled.
225 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
226 p_hwfn->mcp_info->block_mb_sending = false;
228 if (p_hwfn->mcp_info->block_mb_sending) {
229 DP_NOTICE(p_hwfn, false,
230 "Trying to send a MFW mailbox command [0x%x]"
231 " in parallel to [UN]LOAD_REQ. Aborting.\n",
233 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
237 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
238 p_hwfn->mcp_info->block_mb_sending = true;
239 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
242 return ECORE_SUCCESS;
245 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
247 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
248 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
251 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
252 struct ecore_ptt *p_ptt)
254 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
255 u32 delay = CHIP_MCP_RESP_ITER_US;
256 u32 org_mcp_reset_seq, cnt = 0;
257 enum _ecore_status_t rc = ECORE_SUCCESS;
260 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
261 delay = EMUL_MCP_RESP_ITER_US;
264 /* Ensure that only a single thread is accessing the mailbox at a
267 rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
268 if (rc != ECORE_SUCCESS)
271 /* Set drv command along with the updated sequence */
272 org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
273 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
276 /* Wait for MFW response */
278 /* Give the FW up to 500 second (50*1000*10usec) */
279 } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
280 MISCS_REG_GENERIC_POR_0)) &&
281 (cnt++ < ECORE_MCP_RESET_RETRIES));
283 if (org_mcp_reset_seq !=
284 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
285 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
286 "MCP was reset after %d usec\n", cnt * delay);
288 DP_ERR(p_hwfn, "Failed to reset MCP\n");
292 ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
297 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
298 struct ecore_ptt *p_ptt,
303 u32 delay = CHIP_MCP_RESP_ITER_US;
304 u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
305 u32 seq, cnt = 1, actual_mb_seq;
306 enum _ecore_status_t rc = ECORE_SUCCESS;
309 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
310 delay = EMUL_MCP_RESP_ITER_US;
311 /* There is a built-in delay of 100usec in each MFW response read */
312 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
316 /* Get actual driver mailbox sequence */
317 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
318 DRV_MSG_SEQ_NUMBER_MASK;
320 /* Use MCP history register to check if MCP reset occurred between
323 if (p_hwfn->mcp_info->mcp_hist !=
324 ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
325 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
326 ecore_load_mcp_offsets(p_hwfn, p_ptt);
327 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
329 seq = ++p_hwfn->mcp_info->drv_mb_seq;
332 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
334 /* Set drv command along with the updated sequence */
335 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
338 /* Wait for MFW response */
340 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
342 /* Give the FW up to 5 second (500*10ms) */
343 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
344 (cnt++ < max_retries));
346 /* Is this a reply to our command? */
347 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
348 *o_mcp_resp &= FW_MSG_CODE_MASK;
349 /* Get the MCP param */
350 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
353 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
357 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
362 static enum _ecore_status_t
363 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
364 struct ecore_ptt *p_ptt,
365 struct ecore_mcp_mb_params *p_mb_params)
368 enum _ecore_status_t rc;
370 /* MCP not initialized */
371 if (!ecore_mcp_is_init(p_hwfn)) {
372 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
376 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
377 OFFSETOF(struct public_drv_mb, union_data);
379 /* Ensure that only a single thread is accessing the mailbox at a
382 rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
383 if (rc != ECORE_SUCCESS)
386 if (p_mb_params->p_data_src != OSAL_NULL)
387 ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr,
388 p_mb_params->p_data_src,
389 sizeof(*p_mb_params->p_data_src));
391 rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
392 p_mb_params->param, &p_mb_params->mcp_resp,
393 &p_mb_params->mcp_param);
395 if (p_mb_params->p_data_dst != OSAL_NULL)
396 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
398 sizeof(*p_mb_params->p_data_dst));
400 ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
405 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
406 struct ecore_ptt *p_ptt, u32 cmd, u32 param,
407 u32 *o_mcp_resp, u32 *o_mcp_param)
409 struct ecore_mcp_mb_params mb_params;
410 enum _ecore_status_t rc;
413 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
414 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
416 loaded_port[p_hwfn->port_id]--;
417 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
420 return ECORE_SUCCESS;
424 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
426 mb_params.param = param;
427 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
428 if (rc != ECORE_SUCCESS)
431 *o_mcp_resp = mb_params.mcp_resp;
432 *o_mcp_param = mb_params.mcp_param;
434 return ECORE_SUCCESS;
437 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
438 struct ecore_ptt *p_ptt,
443 u32 i_txn_size, u32 *i_buf)
445 struct ecore_mcp_mb_params mb_params;
446 union drv_union_data union_data;
447 enum _ecore_status_t rc;
449 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
451 mb_params.param = param;
452 OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
453 mb_params.p_data_src = &union_data;
454 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
455 if (rc != ECORE_SUCCESS)
458 *o_mcp_resp = mb_params.mcp_resp;
459 *o_mcp_param = mb_params.mcp_param;
461 return ECORE_SUCCESS;
464 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
465 struct ecore_ptt *p_ptt,
470 u32 *o_txn_size, u32 *o_buf)
472 struct ecore_mcp_mb_params mb_params;
473 union drv_union_data union_data;
474 enum _ecore_status_t rc;
476 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
478 mb_params.param = param;
479 mb_params.p_data_dst = &union_data;
480 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
481 if (rc != ECORE_SUCCESS)
484 *o_mcp_resp = mb_params.mcp_resp;
485 *o_mcp_param = mb_params.mcp_param;
487 *o_txn_size = *o_mcp_param;
488 OSAL_MEMCPY(o_buf, (u32 *)&union_data.raw_data, *o_txn_size);
490 return ECORE_SUCCESS;
494 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
497 static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
500 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
501 else if (!loaded_port[p_hwfn->port_id])
502 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
504 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
506 /* On CMT, always tell that it's engine */
507 if (p_hwfn->p_dev->num_hwfns > 1)
508 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
510 *p_load_code = load_phase;
512 loaded_port[p_hwfn->port_id]++;
514 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
515 "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
516 *p_load_code, loaded, p_hwfn->port_id,
517 loaded_port[p_hwfn->port_id]);
521 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
522 struct ecore_ptt *p_ptt,
525 struct ecore_dev *p_dev = p_hwfn->p_dev;
526 struct ecore_mcp_mb_params mb_params;
527 union drv_union_data union_data;
528 enum _ecore_status_t rc;
531 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
532 ecore_mcp_mf_workaround(p_hwfn, p_load_code);
533 return ECORE_SUCCESS;
537 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
538 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
539 mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
541 OSAL_MEMCPY(&union_data.ver_str, p_dev->ver_str, MCP_DRV_VER_STR_SIZE);
542 mb_params.p_data_src = &union_data;
543 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
545 /* if mcp fails to respond we must abort */
546 if (rc != ECORE_SUCCESS) {
547 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
551 *p_load_code = mb_params.mcp_resp;
553 /* If MFW refused (e.g. other port is in diagnostic mode) we
554 * must abort. This can happen in the following cases:
555 * - Other port is in diagnostic mode
556 * - Previously loaded function on the engine is not compliant with
558 * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
561 if (!(*p_load_code) ||
562 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
563 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
564 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
565 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
569 return ECORE_SUCCESS;
572 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
573 struct ecore_ptt *p_ptt)
575 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
577 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
578 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
579 ECORE_PATH_ID(p_hwfn));
580 u32 disabled_vfs[VF_MAX_STATIC / 32];
583 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
584 "Reading Disabled VF information from [offset %08x],"
586 mfw_path_offsize, path_addr);
588 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
589 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
591 OFFSETOF(struct public_path,
594 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
595 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
596 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
599 if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
600 OSAL_VF_FLR_UPDATE(p_hwfn);
603 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
604 struct ecore_ptt *p_ptt,
607 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
609 u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
610 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
612 struct ecore_mcp_mb_params mb_params;
613 union drv_union_data union_data;
614 enum _ecore_status_t rc;
617 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
618 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
619 "Acking VFs [%08x,...,%08x] - %08x\n",
620 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
622 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
623 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
624 OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
625 mb_params.p_data_src = &union_data;
626 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
628 if (rc != ECORE_SUCCESS) {
629 DP_NOTICE(p_hwfn, false,
630 "Failed to pass ACK for VF flr to MFW\n");
631 return ECORE_TIMEOUT;
634 /* TMP - clear the ACK bits; should be done by MFW */
635 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
636 ecore_wr(p_hwfn, p_ptt,
638 OFFSETOF(struct public_func, drv_ack_vf_disabled) +
644 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
645 struct ecore_ptt *p_ptt)
647 u32 transceiver_state;
649 transceiver_state = ecore_rd(p_hwfn, p_ptt,
650 p_hwfn->mcp_info->port_addr +
651 OFFSETOF(struct public_port,
654 DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
655 "Received transceiver state update [0x%08x] from mfw"
657 transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
658 OFFSETOF(struct public_port,
661 transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
663 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
664 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
666 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
669 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
670 struct ecore_ptt *p_ptt,
673 struct ecore_mcp_link_state *p_link;
677 p_link = &p_hwfn->mcp_info->link_output;
678 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
680 status = ecore_rd(p_hwfn, p_ptt,
681 p_hwfn->mcp_info->port_addr +
682 OFFSETOF(struct public_port, link_status));
683 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
684 "Received link update [0x%08x] from mfw"
686 status, (u32)(p_hwfn->mcp_info->port_addr +
687 OFFSETOF(struct public_port,
690 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
691 "Resetting link indications\n");
695 if (p_hwfn->b_drv_link_init)
696 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
698 p_link->link_up = false;
700 p_link->full_duplex = true;
701 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
702 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
703 p_link->speed = 100000;
705 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
706 p_link->speed = 50000;
708 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
709 p_link->speed = 40000;
711 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
712 p_link->speed = 25000;
714 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
715 p_link->speed = 20000;
717 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
718 p_link->speed = 10000;
720 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
721 p_link->full_duplex = false;
723 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
724 p_link->speed = 1000;
730 /* We never store total line speed as p_link->speed is
731 * again changes according to bandwidth allocation.
733 if (p_link->link_up && p_link->speed)
734 p_link->line_speed = p_link->speed;
736 p_link->line_speed = 0;
738 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
739 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
741 /* Max bandwidth configuration */
742 __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
745 /* Mintz bandwidth configuration */
746 __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
748 ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
749 p_link->min_pf_rate);
751 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
752 p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
753 p_link->parallel_detection = !!(status &
754 LINK_STATUS_PARALLEL_DETECTION_USED);
755 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
757 p_link->partner_adv_speed |=
758 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
759 ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
760 p_link->partner_adv_speed |=
761 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
762 ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
763 p_link->partner_adv_speed |=
764 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
765 ECORE_LINK_PARTNER_SPEED_10G : 0;
766 p_link->partner_adv_speed |=
767 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
768 ECORE_LINK_PARTNER_SPEED_20G : 0;
769 p_link->partner_adv_speed |=
770 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
771 ECORE_LINK_PARTNER_SPEED_25G : 0;
772 p_link->partner_adv_speed |=
773 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
774 ECORE_LINK_PARTNER_SPEED_40G : 0;
775 p_link->partner_adv_speed |=
776 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
777 ECORE_LINK_PARTNER_SPEED_50G : 0;
778 p_link->partner_adv_speed |=
779 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
780 ECORE_LINK_PARTNER_SPEED_100G : 0;
782 p_link->partner_tx_flow_ctrl_en =
783 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
784 p_link->partner_rx_flow_ctrl_en =
785 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
787 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
788 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
789 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
791 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
792 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
794 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
795 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
798 p_link->partner_adv_pause = 0;
801 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
803 OSAL_LINK_UPDATE(p_hwfn);
806 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
807 struct ecore_ptt *p_ptt, bool b_up)
809 struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
810 struct ecore_mcp_mb_params mb_params;
811 union drv_union_data union_data;
812 struct eth_phy_cfg *p_phy_cfg;
813 enum _ecore_status_t rc = ECORE_SUCCESS;
817 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
818 return ECORE_SUCCESS;
821 /* Set the shmem configuration according to params */
822 p_phy_cfg = &union_data.drv_phy_cfg;
823 OSAL_MEMSET(p_phy_cfg, 0, sizeof(*p_phy_cfg));
824 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
825 if (!params->speed.autoneg)
826 p_phy_cfg->speed = params->speed.forced_speed;
827 p_phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
828 p_phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
829 p_phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
830 p_phy_cfg->adv_speed = params->speed.advertised_speeds;
831 p_phy_cfg->loopback_mode = params->loopback_mode;
832 p_hwfn->b_drv_link_init = b_up;
835 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
836 "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
837 " adv_speed 0x%08x, loopback 0x%08x\n",
838 p_phy_cfg->speed, p_phy_cfg->pause,
839 p_phy_cfg->adv_speed, p_phy_cfg->loopback_mode);
841 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
843 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
845 mb_params.p_data_src = &union_data;
846 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
848 /* if mcp fails to respond we must abort */
849 if (rc != ECORE_SUCCESS) {
850 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
854 /* Reset the link status if needed */
856 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
861 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
862 struct ecore_ptt *p_ptt)
864 u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
866 /* TODO - Add support for VFs */
867 if (IS_VF(p_hwfn->p_dev))
870 path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
872 path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
873 path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
875 proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
877 OFFSETOF(struct public_path, process_kill)) &
878 PROCESS_KILL_COUNTER_MASK;
880 return proc_kill_cnt;
883 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
884 struct ecore_ptt *p_ptt)
886 struct ecore_dev *p_dev = p_hwfn->p_dev;
889 /* Prevent possible attentions/interrupts during the recovery handling
890 * and till its load phase, during which they will be re-enabled.
892 ecore_int_igu_disable_int(p_hwfn, p_ptt);
894 DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
896 /* The following operations should be done once, and thus in CMT mode
897 * are carried out by only the first HW function.
899 if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
902 if (p_dev->recov_in_prog) {
903 DP_NOTICE(p_hwfn, false,
904 "Ignoring the indication since a recovery"
905 " process is already in progress\n");
909 p_dev->recov_in_prog = true;
911 proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
912 DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
914 OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
917 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
918 struct ecore_ptt *p_ptt,
919 enum MFW_DRV_MSG_TYPE type)
921 enum ecore_mcp_protocol_type stats_type;
922 union ecore_mcp_protocol_stats stats;
923 struct ecore_mcp_mb_params mb_params;
924 union drv_union_data union_data;
928 case MFW_DRV_MSG_GET_LAN_STATS:
929 stats_type = ECORE_MCP_LAN_STATS;
930 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
933 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
937 OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
939 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
940 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
941 mb_params.param = hsi_param;
942 OSAL_MEMCPY(&union_data, &stats, sizeof(stats));
943 mb_params.p_data_src = &union_data;
944 ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
947 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
948 struct public_func *p_shmem_info)
950 struct ecore_mcp_function_info *p_info;
952 p_info = &p_hwfn->mcp_info->func_info;
954 /* TODO - bandwidth min/max should have valid values of 1-100,
955 * as well as some indication that the feature is disabled.
956 * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
957 * limit and correct value to min `1' and max `100' if limit isn't in
960 p_info->bandwidth_min = (p_shmem_info->config &
961 FUNC_MF_CFG_MIN_BW_MASK) >>
962 FUNC_MF_CFG_MIN_BW_SHIFT;
963 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
965 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
966 p_info->bandwidth_min);
967 p_info->bandwidth_min = 1;
970 p_info->bandwidth_max = (p_shmem_info->config &
971 FUNC_MF_CFG_MAX_BW_MASK) >>
972 FUNC_MF_CFG_MAX_BW_SHIFT;
973 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
975 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
976 p_info->bandwidth_max);
977 p_info->bandwidth_max = 100;
981 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
982 struct ecore_ptt *p_ptt,
983 struct public_func *p_data,
986 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
988 u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
989 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
992 OSAL_MEM_ZERO(p_data, sizeof(*p_data));
994 size = OSAL_MIN_T(u32, sizeof(*p_data),
995 SECTION_SIZE(mfw_path_offsize));
996 for (i = 0; i < size / sizeof(u32); i++)
997 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
998 func_addr + (i << 2));
1004 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1006 struct ecore_mcp_function_info *p_info;
1007 struct public_func shmem_info;
1008 u32 resp = 0, param = 0;
1010 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1012 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1014 p_info = &p_hwfn->mcp_info->func_info;
1016 ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1018 ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1020 /* Acknowledge the MFW */
1021 ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1025 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1026 struct ecore_ptt *p_ptt)
1028 /* A single notification should be sent to upper driver in CMT mode */
1029 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1032 DP_NOTICE(p_hwfn, false,
1033 "Fan failure was detected on the network interface card"
1034 " and it's going to be shut down.\n");
1036 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1039 static enum _ecore_status_t
1040 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1041 u32 mdump_cmd, union drv_union_data *p_data_src,
1042 union drv_union_data *p_data_dst, u32 *p_mcp_resp)
1044 struct ecore_mcp_mb_params mb_params;
1045 enum _ecore_status_t rc;
1047 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1048 mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1049 mb_params.param = mdump_cmd;
1050 mb_params.p_data_src = p_data_src;
1051 mb_params.p_data_dst = p_data_dst;
1052 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1053 if (rc != ECORE_SUCCESS)
1056 *p_mcp_resp = mb_params.mcp_resp;
1057 if (*p_mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1058 DP_NOTICE(p_hwfn, false,
1059 "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1067 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1068 struct ecore_ptt *p_ptt)
1072 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_ACK,
1073 OSAL_NULL, OSAL_NULL, &mcp_resp);
1076 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1077 struct ecore_ptt *p_ptt,
1080 union drv_union_data union_data;
1083 OSAL_MEMCPY(&union_data.raw_data, &epoch, sizeof(epoch));
1085 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_SET_VALUES,
1086 &union_data, OSAL_NULL, &mcp_resp);
1089 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1090 struct ecore_ptt *p_ptt)
1094 p_hwfn->p_dev->mdump_en = true;
1096 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_TRIGGER,
1097 OSAL_NULL, OSAL_NULL, &mcp_resp);
1100 static enum _ecore_status_t
1101 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1102 struct mdump_config_stc *p_mdump_config)
1104 union drv_union_data union_data;
1106 enum _ecore_status_t rc;
1108 rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_GET_CONFIG,
1109 OSAL_NULL, &union_data, &mcp_resp);
1110 if (rc != ECORE_SUCCESS)
1113 /* A zero response implies that the mdump command is not supported */
1115 return ECORE_NOTIMPL;
1117 if (mcp_resp != FW_MSG_CODE_OK) {
1118 DP_NOTICE(p_hwfn, false,
1119 "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1121 rc = ECORE_UNKNOWN_ERROR;
1124 OSAL_MEMCPY(p_mdump_config, &union_data.mdump_config,
1125 sizeof(*p_mdump_config));
1130 enum _ecore_status_t
1131 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1132 struct ecore_mdump_info *p_mdump_info)
1134 u32 addr, global_offsize, global_addr;
1135 struct mdump_config_stc mdump_config;
1136 enum _ecore_status_t rc;
1138 OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1140 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1142 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1143 global_addr = SECTION_ADDR(global_offsize, 0);
1144 p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1146 OFFSETOF(struct public_global,
1149 if (p_mdump_info->reason) {
1150 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1151 if (rc != ECORE_SUCCESS)
1154 p_mdump_info->version = mdump_config.version;
1155 p_mdump_info->config = mdump_config.config;
1156 p_mdump_info->epoch = mdump_config.epoc;
1157 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1158 p_mdump_info->valid_logs = mdump_config.valid_logs;
1160 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1161 "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1162 p_mdump_info->reason, p_mdump_info->version,
1163 p_mdump_info->config, p_mdump_info->epoch,
1164 p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1166 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1167 "MFW mdump info: reason %d\n", p_mdump_info->reason);
1170 return ECORE_SUCCESS;
1173 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1174 struct ecore_ptt *p_ptt)
1178 return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MDUMP_CLEAR_LOGS,
1179 OSAL_NULL, OSAL_NULL, &mcp_resp);
1182 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1183 struct ecore_ptt *p_ptt)
1185 /* In CMT mode - no need for more than a single acknowledgment to the
1186 * MFW, and no more than a single notification to the upper driver.
1188 if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1191 DP_NOTICE(p_hwfn, false,
1192 "Received a critical error notification from the MFW!\n");
1194 if (p_hwfn->p_dev->mdump_en) {
1195 DP_NOTICE(p_hwfn, false,
1196 "Not acknowledging the notification to allow the MFW crash dump\n");
1197 p_hwfn->p_dev->mdump_en = false;
1201 ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1202 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1205 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1206 struct ecore_ptt *p_ptt)
1208 struct ecore_mcp_info *info = p_hwfn->mcp_info;
1209 enum _ecore_status_t rc = ECORE_SUCCESS;
1213 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1215 /* Read Messages from MFW */
1216 ecore_mcp_read_mb(p_hwfn, p_ptt);
1218 /* Compare current messages to old ones */
1219 for (i = 0; i < info->mfw_mb_length; i++) {
1220 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1225 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1226 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1227 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1230 case MFW_DRV_MSG_LINK_CHANGE:
1231 ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1233 case MFW_DRV_MSG_VF_DISABLED:
1234 ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1236 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1237 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1238 ECORE_DCBX_REMOTE_LLDP_MIB);
1240 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1241 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1242 ECORE_DCBX_REMOTE_MIB);
1244 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1245 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1246 ECORE_DCBX_OPERATIONAL_MIB);
1248 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1249 ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1251 case MFW_DRV_MSG_ERROR_RECOVERY:
1252 ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1254 case MFW_DRV_MSG_GET_LAN_STATS:
1255 case MFW_DRV_MSG_GET_FCOE_STATS:
1256 case MFW_DRV_MSG_GET_ISCSI_STATS:
1257 case MFW_DRV_MSG_GET_RDMA_STATS:
1258 ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1260 case MFW_DRV_MSG_BW_UPDATE:
1261 ecore_mcp_update_bw(p_hwfn, p_ptt);
1263 case MFW_DRV_MSG_FAILURE_DETECTED:
1264 ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1266 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1267 ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1270 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1275 /* ACK everything */
1276 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1277 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1279 /* MFW expect answer in BE, so we force write in that format */
1280 ecore_wr(p_hwfn, p_ptt,
1281 info->mfw_mb_addr + sizeof(u32) +
1282 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1283 sizeof(u32) + i * sizeof(u32), val);
1287 DP_NOTICE(p_hwfn, false,
1288 "Received an MFW message indication but no"
1293 /* Copy the new mfw messages into the shadow */
1294 OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1299 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1300 struct ecore_ptt *p_ptt,
1302 u32 *p_running_bundle_id)
1307 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1308 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1309 return ECORE_SUCCESS;
1313 if (IS_VF(p_hwfn->p_dev)) {
1314 if (p_hwfn->vf_iov_info) {
1315 struct pfvf_acquire_resp_tlv *p_resp;
1317 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1318 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1319 return ECORE_SUCCESS;
1321 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1322 "VF requested MFW version prior to ACQUIRE\n");
1327 global_offsize = ecore_rd(p_hwfn, p_ptt,
1328 SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1332 ecore_rd(p_hwfn, p_ptt,
1333 SECTION_ADDR(global_offsize,
1334 0) + OFFSETOF(struct public_global, mfw_ver));
1336 if (p_running_bundle_id != OSAL_NULL) {
1337 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1338 SECTION_ADDR(global_offsize,
1340 OFFSETOF(struct public_global,
1341 running_bundle_id));
1344 return ECORE_SUCCESS;
1347 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1350 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1351 struct ecore_ptt *p_ptt;
1353 /* TODO - Add support for VFs */
1357 if (!ecore_mcp_is_init(p_hwfn)) {
1358 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1362 *p_media_type = MEDIA_UNSPECIFIED;
1364 p_ptt = ecore_ptt_acquire(p_hwfn);
1368 *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1369 OFFSETOF(struct public_port, media_type));
1371 ecore_ptt_release(p_hwfn, p_ptt);
1373 return ECORE_SUCCESS;
1376 static enum _ecore_status_t
1377 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1378 struct public_func *p_info,
1379 enum ecore_pci_personality *p_proto)
1381 enum _ecore_status_t rc = ECORE_SUCCESS;
1383 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1384 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1385 *p_proto = ECORE_PCI_ETH;
1394 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1395 struct ecore_ptt *p_ptt)
1397 struct ecore_mcp_function_info *info;
1398 struct public_func shmem_info;
1400 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1401 info = &p_hwfn->mcp_info->func_info;
1403 info->pause_on_host = (shmem_info.config &
1404 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1406 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, &info->protocol)) {
1407 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1408 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1412 ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1414 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1415 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1416 info->mac[1] = (u8)(shmem_info.mac_upper);
1417 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1418 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1419 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1420 info->mac[5] = (u8)(shmem_info.mac_lower);
1422 /* TODO - are there protocols for which there's no MAC? */
1423 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1426 /* TODO - are these calculations true for BE machine? */
1427 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1428 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1429 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1430 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1432 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1434 info->mtu = (u16)shmem_info.mtu_size;
1439 info->mtu = (u16)shmem_info.mtu_size;
1441 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1442 "Read configuration from shmem: pause_on_host %02x"
1443 " protocol %02x BW [%02x - %02x]"
1444 " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1445 " node %lx ovlan %04x\n",
1446 info->pause_on_host, info->protocol,
1447 info->bandwidth_min, info->bandwidth_max,
1448 info->mac[0], info->mac[1], info->mac[2],
1449 info->mac[3], info->mac[4], info->mac[5],
1450 (unsigned long)info->wwn_port,
1451 (unsigned long)info->wwn_node, info->ovlan);
1453 return ECORE_SUCCESS;
1456 struct ecore_mcp_link_params
1457 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1459 if (!p_hwfn || !p_hwfn->mcp_info)
1461 return &p_hwfn->mcp_info->link_input;
1464 struct ecore_mcp_link_state
1465 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1467 if (!p_hwfn || !p_hwfn->mcp_info)
1471 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1472 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1473 p_hwfn->mcp_info->link_output.link_up = true;
1477 return &p_hwfn->mcp_info->link_output;
1480 struct ecore_mcp_link_capabilities
1481 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1483 if (!p_hwfn || !p_hwfn->mcp_info)
1485 return &p_hwfn->mcp_info->link_capabilities;
1488 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1489 struct ecore_ptt *p_ptt)
1491 u32 resp = 0, param = 0;
1492 enum _ecore_status_t rc;
1494 rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1495 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
1497 /* Wait for the drain to complete before returning */
1503 const struct ecore_mcp_function_info
1504 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1506 if (!p_hwfn || !p_hwfn->mcp_info)
1508 return &p_hwfn->mcp_info->func_info;
1511 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1512 struct ecore_ptt *p_ptt,
1513 struct ecore_mcp_nvm_params *params)
1515 enum _ecore_status_t rc;
1517 switch (params->type) {
1518 case ECORE_MCP_NVM_RD:
1519 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1520 params->nvm_common.offset,
1521 ¶ms->nvm_common.resp,
1522 ¶ms->nvm_common.param,
1523 params->nvm_rd.buf_size,
1524 params->nvm_rd.buf);
1527 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1528 params->nvm_common.offset,
1529 ¶ms->nvm_common.resp,
1530 ¶ms->nvm_common.param);
1532 case ECORE_MCP_NVM_WR:
1533 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1534 params->nvm_common.offset,
1535 ¶ms->nvm_common.resp,
1536 ¶ms->nvm_common.param,
1537 params->nvm_wr.buf_size,
1538 params->nvm_wr.buf);
1547 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1548 struct ecore_ptt *p_ptt, u32 personalities)
1550 enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1551 struct public_func shmem_info;
1552 int i, count = 0, num_pfs;
1554 num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1556 for (i = 0; i < num_pfs; i++) {
1557 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1558 MCP_PF_ID_BY_REL(p_hwfn, i));
1559 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1562 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info,
1563 &protocol) != ECORE_SUCCESS)
1566 if ((1 << ((u32)protocol)) & personalities)
1573 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1574 struct ecore_ptt *p_ptt,
1580 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1581 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
1586 if (IS_VF(p_hwfn->p_dev))
1589 flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1590 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1591 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1592 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1594 *p_flash_size = flash_size;
1596 return ECORE_SUCCESS;
1599 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
1600 struct ecore_ptt *p_ptt)
1602 struct ecore_dev *p_dev = p_hwfn->p_dev;
1604 if (p_dev->recov_in_prog) {
1605 DP_NOTICE(p_hwfn, false,
1606 "Avoid triggering a recovery since such a process"
1607 " is already in progress\n");
1611 DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
1612 ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
1614 return ECORE_SUCCESS;
1617 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
1618 struct ecore_ptt *p_ptt,
1621 u32 resp = 0, param = 0, rc_param = 0;
1622 enum _ecore_status_t rc;
1624 /* Only Leader can configure MSIX, and need to take CMT into account */
1626 if (!IS_LEAD_HWFN(p_hwfn))
1627 return ECORE_SUCCESS;
1628 num *= p_hwfn->p_dev->num_hwfns;
1630 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1631 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1632 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1633 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1635 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1638 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1639 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
1643 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1644 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1651 enum _ecore_status_t
1652 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1653 struct ecore_mcp_drv_version *p_ver)
1655 struct drv_version_stc *p_drv_version;
1656 struct ecore_mcp_mb_params mb_params;
1657 union drv_union_data union_data;
1661 enum _ecore_status_t rc;
1664 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
1665 return ECORE_SUCCESS;
1668 p_drv_version = &union_data.drv_version;
1669 p_drv_version->version = p_ver->version;
1670 num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
1671 for (i = 0; i < num_words; i++) {
1672 /* The driver name is expected to be in a big-endian format */
1673 p_name = &p_ver->name[i * sizeof(u32)];
1674 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
1675 *(u32 *)&p_drv_version->name[i * sizeof(u32)] = val;
1678 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1679 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1680 mb_params.p_data_src = &union_data;
1681 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1682 if (rc != ECORE_SUCCESS)
1683 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1688 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
1689 struct ecore_ptt *p_ptt)
1691 enum _ecore_status_t rc;
1692 u32 resp = 0, param = 0;
1694 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1696 if (rc != ECORE_SUCCESS)
1697 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1702 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
1703 struct ecore_ptt *p_ptt)
1705 u32 value, cpu_mode;
1707 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1709 value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1710 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1711 ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1712 cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1714 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
1717 enum _ecore_status_t
1718 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
1719 struct ecore_ptt *p_ptt,
1720 enum ecore_ov_client client)
1722 enum _ecore_status_t rc;
1723 u32 resp = 0, param = 0;
1727 case ECORE_OV_CLIENT_DRV:
1728 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1730 case ECORE_OV_CLIENT_USER:
1731 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1733 case ECORE_OV_CLIENT_VENDOR_SPEC:
1734 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
1737 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
1741 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1742 drv_mb_param, &resp, ¶m);
1743 if (rc != ECORE_SUCCESS)
1744 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1749 enum _ecore_status_t
1750 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
1751 struct ecore_ptt *p_ptt,
1752 enum ecore_ov_driver_state drv_state)
1754 enum _ecore_status_t rc;
1755 u32 resp = 0, param = 0;
1758 switch (drv_state) {
1759 case ECORE_OV_DRIVER_STATE_NOT_LOADED:
1760 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1762 case ECORE_OV_DRIVER_STATE_DISABLED:
1763 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1765 case ECORE_OV_DRIVER_STATE_ACTIVE:
1766 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1769 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
1773 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1774 drv_mb_param, &resp, ¶m);
1775 if (rc != ECORE_SUCCESS)
1776 DP_ERR(p_hwfn, "Failed to send driver state\n");
1781 enum _ecore_status_t
1782 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1783 struct ecore_fc_npiv_tbl *p_table)
1788 enum _ecore_status_t
1789 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
1790 struct ecore_ptt *p_ptt, u16 mtu)
1795 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
1796 struct ecore_ptt *p_ptt,
1797 enum ecore_led_mode mode)
1799 u32 resp = 0, param = 0, drv_mb_param;
1800 enum _ecore_status_t rc;
1803 case ECORE_LED_MODE_ON:
1804 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1806 case ECORE_LED_MODE_OFF:
1807 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1809 case ECORE_LED_MODE_RESTORE:
1810 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1813 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
1817 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1818 drv_mb_param, &resp, ¶m);
1819 if (rc != ECORE_SUCCESS)
1820 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1825 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
1826 struct ecore_ptt *p_ptt,
1829 enum _ecore_status_t rc;
1830 u32 resp = 0, param = 0;
1832 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1833 mask_parities, &resp, ¶m);
1835 if (rc != ECORE_SUCCESS) {
1837 "MCP response failure for mask parities, aborting\n");
1838 } else if (resp != FW_MSG_CODE_OK) {
1840 "MCP did not ack mask parity request. Old MFW?\n");
1847 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
1850 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1851 u32 bytes_left, offset, bytes_to_copy, buf_size;
1852 struct ecore_mcp_nvm_params params;
1853 struct ecore_ptt *p_ptt;
1854 enum _ecore_status_t rc = ECORE_SUCCESS;
1856 p_ptt = ecore_ptt_acquire(p_hwfn);
1860 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1863 params.type = ECORE_MCP_NVM_RD;
1864 params.nvm_rd.buf_size = &buf_size;
1865 params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
1866 while (bytes_left > 0) {
1867 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
1868 MCP_DRV_NVM_BUF_LEN);
1869 params.nvm_common.offset = (addr + offset) |
1870 (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
1871 params.nvm_rd.buf = (u32 *)(p_buf + offset);
1872 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1873 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
1874 FW_MSG_CODE_NVM_OK)) {
1875 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1879 /* This can be a lengthy process, and it's possible scheduler
1880 * isn't preemptible. Sleep a bit to prevent CPU hogging.
1882 if (bytes_left % 0x1000 <
1883 (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
1886 offset += *params.nvm_rd.buf_size;
1887 bytes_left -= *params.nvm_rd.buf_size;
1890 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1891 ecore_ptt_release(p_hwfn, p_ptt);
1896 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
1897 u32 addr, u8 *p_buf, u32 len)
1899 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1900 struct ecore_mcp_nvm_params params;
1901 struct ecore_ptt *p_ptt;
1902 enum _ecore_status_t rc;
1904 p_ptt = ecore_ptt_acquire(p_hwfn);
1908 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1909 params.type = ECORE_MCP_NVM_RD;
1910 params.nvm_rd.buf_size = &len;
1911 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
1912 DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
1913 params.nvm_common.offset = addr;
1914 params.nvm_rd.buf = (u32 *)p_buf;
1915 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1916 if (rc != ECORE_SUCCESS)
1917 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
1919 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1920 ecore_ptt_release(p_hwfn, p_ptt);
1925 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
1927 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1928 struct ecore_mcp_nvm_params params;
1929 struct ecore_ptt *p_ptt;
1931 p_ptt = ecore_ptt_acquire(p_hwfn);
1935 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1936 OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
1937 ecore_ptt_release(p_hwfn, p_ptt);
1939 return ECORE_SUCCESS;
1942 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
1944 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1945 struct ecore_mcp_nvm_params params;
1946 struct ecore_ptt *p_ptt;
1947 enum _ecore_status_t rc;
1949 p_ptt = ecore_ptt_acquire(p_hwfn);
1952 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1953 params.type = ECORE_MCP_CMD;
1954 params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
1955 params.nvm_common.offset = addr;
1956 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1957 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1958 ecore_ptt_release(p_hwfn, p_ptt);
1963 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
1966 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1967 struct ecore_mcp_nvm_params params;
1968 struct ecore_ptt *p_ptt;
1969 enum _ecore_status_t rc;
1971 p_ptt = ecore_ptt_acquire(p_hwfn);
1974 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
1975 params.type = ECORE_MCP_CMD;
1976 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
1977 params.nvm_common.offset = addr;
1978 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
1979 p_dev->mcp_nvm_resp = params.nvm_common.resp;
1980 ecore_ptt_release(p_hwfn, p_ptt);
1985 /* rc receives ECORE_INVAL as default parameter because
1986 * it might not enter the while loop if the len is 0
1988 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
1989 u32 addr, u8 *p_buf, u32 len)
1991 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1992 enum _ecore_status_t rc = ECORE_INVAL;
1993 struct ecore_mcp_nvm_params params;
1994 struct ecore_ptt *p_ptt;
1995 u32 buf_idx, buf_size;
1997 p_ptt = ecore_ptt_acquire(p_hwfn);
2001 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2002 params.type = ECORE_MCP_NVM_WR;
2003 if (cmd == ECORE_PUT_FILE_DATA)
2004 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2006 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2008 while (buf_idx < len) {
2009 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2010 MCP_DRV_NVM_BUF_LEN);
2011 params.nvm_common.offset = ((buf_size <<
2012 DRV_MB_PARAM_NVM_LEN_SHIFT)
2014 params.nvm_wr.buf_size = buf_size;
2015 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2016 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2017 if (rc != ECORE_SUCCESS ||
2018 ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2019 (params.nvm_common.resp !=
2020 FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2021 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2023 /* This can be a lengthy process, and it's possible scheduler
2024 * isn't preemptible. Sleep a bit to prevent CPU hogging.
2026 if (buf_idx % 0x1000 >
2027 (buf_idx + buf_size) % 0x1000)
2030 buf_idx += buf_size;
2033 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2034 ecore_ptt_release(p_hwfn, p_ptt);
2039 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2040 u32 addr, u8 *p_buf, u32 len)
2042 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2043 struct ecore_mcp_nvm_params params;
2044 struct ecore_ptt *p_ptt;
2045 enum _ecore_status_t rc;
2047 p_ptt = ecore_ptt_acquire(p_hwfn);
2051 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2052 params.type = ECORE_MCP_NVM_WR;
2053 params.nvm_wr.buf_size = len;
2054 params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2055 DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2056 params.nvm_common.offset = addr;
2057 params.nvm_wr.buf = (u32 *)p_buf;
2058 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2059 if (rc != ECORE_SUCCESS)
2060 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2061 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2062 ecore_ptt_release(p_hwfn, p_ptt);
2067 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2070 struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2071 struct ecore_mcp_nvm_params params;
2072 struct ecore_ptt *p_ptt;
2073 enum _ecore_status_t rc;
2075 p_ptt = ecore_ptt_acquire(p_hwfn);
2079 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2080 params.type = ECORE_MCP_CMD;
2081 params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2082 params.nvm_common.offset = addr;
2083 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2084 p_dev->mcp_nvm_resp = params.nvm_common.resp;
2085 ecore_ptt_release(p_hwfn, p_ptt);
2090 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2091 struct ecore_ptt *p_ptt,
2092 u32 port, u32 addr, u32 offset,
2095 struct ecore_mcp_nvm_params params;
2096 enum _ecore_status_t rc;
2097 u32 bytes_left, bytes_to_copy, buf_size;
2099 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2100 params.nvm_common.offset =
2101 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2102 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2106 params.type = ECORE_MCP_NVM_RD;
2107 params.nvm_rd.buf_size = &buf_size;
2108 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2109 while (bytes_left > 0) {
2110 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2111 MAX_I2C_TRANSACTION_SIZE);
2112 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2113 params.nvm_common.offset &=
2114 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2115 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2116 params.nvm_common.offset |=
2118 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2119 params.nvm_common.offset |=
2120 (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2121 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2122 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2123 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2125 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2126 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2127 return ECORE_UNKNOWN_ERROR;
2129 offset += *params.nvm_rd.buf_size;
2130 bytes_left -= *params.nvm_rd.buf_size;
2133 return ECORE_SUCCESS;
2136 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2137 struct ecore_ptt *p_ptt,
2138 u32 port, u32 addr, u32 offset,
2141 struct ecore_mcp_nvm_params params;
2142 enum _ecore_status_t rc;
2143 u32 buf_idx, buf_size;
2145 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2146 params.nvm_common.offset =
2147 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2148 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2149 params.type = ECORE_MCP_NVM_WR;
2150 params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2152 while (buf_idx < len) {
2153 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2154 MAX_I2C_TRANSACTION_SIZE);
2155 params.nvm_common.offset &=
2156 (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2157 DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2158 params.nvm_common.offset |=
2159 ((offset + buf_idx) <<
2160 DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2161 params.nvm_common.offset |=
2162 (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2163 params.nvm_wr.buf_size = buf_size;
2164 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2165 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2166 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2167 FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2169 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2170 FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2171 return ECORE_UNKNOWN_ERROR;
2173 buf_idx += buf_size;
2176 return ECORE_SUCCESS;
2179 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2180 struct ecore_ptt *p_ptt,
2181 u16 gpio, u32 *gpio_val)
2183 enum _ecore_status_t rc = ECORE_SUCCESS;
2184 u32 drv_mb_param = 0, rsp;
2186 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2188 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2189 drv_mb_param, &rsp, gpio_val);
2191 if (rc != ECORE_SUCCESS)
2194 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2195 return ECORE_UNKNOWN_ERROR;
2197 return ECORE_SUCCESS;
2200 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2201 struct ecore_ptt *p_ptt,
2202 u16 gpio, u16 gpio_val)
2204 enum _ecore_status_t rc = ECORE_SUCCESS;
2205 u32 drv_mb_param = 0, param, rsp;
2207 drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2208 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2210 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2211 drv_mb_param, &rsp, ¶m);
2213 if (rc != ECORE_SUCCESS)
2216 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2217 return ECORE_UNKNOWN_ERROR;
2219 return ECORE_SUCCESS;
2222 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2223 struct ecore_ptt *p_ptt,
2224 u16 gpio, u32 *gpio_direction,
2227 u32 drv_mb_param = 0, rsp, val = 0;
2228 enum _ecore_status_t rc = ECORE_SUCCESS;
2230 drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2232 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2233 drv_mb_param, &rsp, &val);
2234 if (rc != ECORE_SUCCESS)
2237 *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2238 DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2239 *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2240 DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2242 if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2243 return ECORE_UNKNOWN_ERROR;
2245 return ECORE_SUCCESS;
2248 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2249 struct ecore_ptt *p_ptt)
2251 u32 drv_mb_param = 0, rsp, param;
2252 enum _ecore_status_t rc = ECORE_SUCCESS;
2254 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2255 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2257 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2258 drv_mb_param, &rsp, ¶m);
2260 if (rc != ECORE_SUCCESS)
2263 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2264 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2265 rc = ECORE_UNKNOWN_ERROR;
2270 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2271 struct ecore_ptt *p_ptt)
2273 u32 drv_mb_param, rsp, param;
2274 enum _ecore_status_t rc = ECORE_SUCCESS;
2276 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2277 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2279 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2280 drv_mb_param, &rsp, ¶m);
2282 if (rc != ECORE_SUCCESS)
2285 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2286 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2287 rc = ECORE_UNKNOWN_ERROR;
2292 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2293 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2295 u32 drv_mb_param = 0, rsp;
2296 enum _ecore_status_t rc = ECORE_SUCCESS;
2298 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2299 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2301 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2302 drv_mb_param, &rsp, num_images);
2304 if (rc != ECORE_SUCCESS)
2307 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2308 rc = ECORE_UNKNOWN_ERROR;
2313 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2314 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2315 struct bist_nvm_image_att *p_image_att, u32 image_index)
2317 struct ecore_mcp_nvm_params params;
2318 enum _ecore_status_t rc;
2321 OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_mcp_nvm_params));
2322 params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2323 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2324 params.nvm_common.offset |= (image_index <<
2325 DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2327 params.type = ECORE_MCP_NVM_RD;
2328 params.nvm_rd.buf_size = &buf_size;
2329 params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2330 params.nvm_rd.buf = (u32 *)p_image_att;
2332 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2333 if (rc != ECORE_SUCCESS)
2336 if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2337 (p_image_att->return_code != 1))
2338 rc = ECORE_UNKNOWN_ERROR;
2343 enum _ecore_status_t
2344 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2345 struct ecore_ptt *p_ptt,
2346 struct ecore_temperature_info *p_temp_info)
2348 struct ecore_temperature_sensor *p_temp_sensor;
2349 struct temperature_status_stc *p_mfw_temp_info;
2350 struct ecore_mcp_mb_params mb_params;
2351 union drv_union_data union_data;
2353 enum _ecore_status_t rc;
2356 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2357 mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2358 mb_params.p_data_dst = &union_data;
2359 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2360 if (rc != ECORE_SUCCESS)
2363 p_mfw_temp_info = &union_data.temp_info;
2365 OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2366 p_temp_info->num_sensors = OSAL_MIN_T(u32,
2367 p_mfw_temp_info->num_of_sensors,
2368 ECORE_MAX_NUM_OF_SENSORS);
2369 for (i = 0; i < p_temp_info->num_sensors; i++) {
2370 val = p_mfw_temp_info->sensor[i];
2371 p_temp_sensor = &p_temp_info->sensors[i];
2372 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2373 SENSOR_LOCATION_SHIFT;
2374 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2375 THRESHOLD_HIGH_SHIFT;
2376 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2377 CRITICAL_TEMPERATURE_SHIFT;
2378 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2382 return ECORE_SUCCESS;
2385 enum _ecore_status_t ecore_mcp_get_mba_versions(
2386 struct ecore_hwfn *p_hwfn,
2387 struct ecore_ptt *p_ptt,
2388 struct ecore_mba_vers *p_mba_vers)
2390 struct ecore_mcp_nvm_params params;
2391 enum _ecore_status_t rc;
2394 OSAL_MEM_ZERO(¶ms, sizeof(params));
2395 params.type = ECORE_MCP_NVM_RD;
2396 params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2397 params.nvm_common.offset = 0;
2398 params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2399 params.nvm_rd.buf_size = &buf_size;
2400 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, ¶ms);
2402 if (rc != ECORE_SUCCESS)
2405 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2407 rc = ECORE_UNKNOWN_ERROR;
2409 if (buf_size != MCP_DRV_NVM_BUF_LEN)
2410 rc = ECORE_UNKNOWN_ERROR;
2415 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2416 struct ecore_ptt *p_ptt,
2421 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2422 0, &rsp, (u32 *)num_events);
2425 #define ECORE_RESC_ALLOC_VERSION_MAJOR 1
2426 #define ECORE_RESC_ALLOC_VERSION_MINOR 0
2427 #define ECORE_RESC_ALLOC_VERSION \
2428 ((ECORE_RESC_ALLOC_VERSION_MAJOR << \
2429 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2430 (ECORE_RESC_ALLOC_VERSION_MINOR << \
2431 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2433 enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
2434 struct ecore_ptt *p_ptt,
2435 struct resource_info *p_resc_info,
2436 u32 *p_mcp_resp, u32 *p_mcp_param)
2438 struct ecore_mcp_mb_params mb_params;
2439 union drv_union_data union_data;
2440 enum _ecore_status_t rc;
2442 OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2443 mb_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2444 mb_params.param = ECORE_RESC_ALLOC_VERSION;
2445 OSAL_MEMCPY(&union_data.resource, p_resc_info, sizeof(*p_resc_info));
2446 mb_params.p_data_src = &union_data;
2447 mb_params.p_data_dst = &union_data;
2448 rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2449 if (rc != ECORE_SUCCESS)
2452 *p_mcp_resp = mb_params.mcp_resp;
2453 *p_mcp_param = mb_params.mcp_param;
2455 OSAL_MEMCPY(p_resc_info, &union_data.resource, sizeof(*p_resc_info));
2457 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2458 "MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x,"
2459 " offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
2460 *p_mcp_param, p_resc_info->res_id, p_resc_info->size,
2461 p_resc_info->offset, p_resc_info->vf_size,
2462 p_resc_info->vf_offset, p_resc_info->flags);
2464 return ECORE_SUCCESS;
2467 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
2468 struct ecore_ptt *p_ptt)
2470 u32 mcp_resp, mcp_param;
2472 return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2473 &mcp_resp, &mcp_param);