2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
11 static bool gro_disable = 1; /* mod_param */
13 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
15 struct rte_mbuf *new_mb = NULL;
16 struct eth_rx_bd *rx_bd;
18 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
20 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
21 if (unlikely(!new_mb)) {
23 "Failed to allocate rx buffer "
24 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
25 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
26 rte_mempool_avail_count(rxq->mb_pool),
27 rte_mempool_in_use_count(rxq->mb_pool));
30 rxq->sw_rx_ring[idx].mbuf = new_mb;
31 rxq->sw_rx_ring[idx].page_offset = 0;
32 mapping = rte_mbuf_data_dma_addr_default(new_mb);
33 /* Advance PROD and get BD pointer */
34 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
35 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
36 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
41 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
45 if (rxq->sw_rx_ring != NULL) {
46 for (i = 0; i < rxq->nb_rx_desc; i++) {
47 if (rxq->sw_rx_ring[i].mbuf != NULL) {
48 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
49 rxq->sw_rx_ring[i].mbuf = NULL;
55 void qede_rx_queue_release(void *rx_queue)
57 struct qede_rx_queue *rxq = rx_queue;
60 qede_rx_queue_release_mbufs(rxq);
61 rte_free(rxq->sw_rx_ring);
62 rxq->sw_rx_ring = NULL;
68 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
72 PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs\n", txq->nb_tx_desc);
74 if (txq->sw_tx_ring) {
75 for (i = 0; i < txq->nb_tx_desc; i++) {
76 if (txq->sw_tx_ring[i].mbuf) {
77 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
78 txq->sw_tx_ring[i].mbuf = NULL;
85 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
86 uint16_t nb_desc, unsigned int socket_id,
87 const struct rte_eth_rxconf *rx_conf,
88 struct rte_mempool *mp)
90 struct qede_dev *qdev = dev->data->dev_private;
91 struct ecore_dev *edev = &qdev->edev;
92 struct rte_eth_dev_data *eth_data = dev->data;
93 struct qede_rx_queue *rxq;
94 uint16_t pkt_len = (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len;
100 PMD_INIT_FUNC_TRACE(edev);
102 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
103 if (!rte_is_power_of_2(nb_desc)) {
104 DP_ERR(edev, "Ring size %u is not power of 2\n",
109 /* Free memory prior to re-allocation if needed... */
110 if (dev->data->rx_queues[queue_idx] != NULL) {
111 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
112 dev->data->rx_queues[queue_idx] = NULL;
115 /* First allocate the rx queue data structure */
116 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
117 RTE_CACHE_LINE_SIZE, socket_id);
120 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
127 rxq->nb_rx_desc = nb_desc;
128 rxq->queue_id = queue_idx;
129 rxq->port_id = dev->data->port_id;
132 data_size = (uint16_t)rte_pktmbuf_data_room_size(mp) -
133 RTE_PKTMBUF_HEADROOM;
135 if (pkt_len > data_size && !dev->data->scattered_rx) {
136 DP_ERR(edev, "MTU %u should not exceed dataroom %u\n",
142 if (dev->data->scattered_rx)
143 rxq->rx_buf_size = data_size;
145 rxq->rx_buf_size = pkt_len + QEDE_ETH_OVERHEAD;
149 DP_INFO(edev, "MTU = %u ; RX buffer = %u\n",
150 qdev->mtu, rxq->rx_buf_size);
152 if (pkt_len > ETHER_MAX_LEN) {
153 dev->data->dev_conf.rxmode.jumbo_frame = 1;
154 DP_NOTICE(edev, false, "jumbo frame enabled\n");
156 dev->data->dev_conf.rxmode.jumbo_frame = 0;
159 /* Allocate the parallel driver ring for Rx buffers */
160 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
161 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
162 RTE_CACHE_LINE_SIZE, socket_id);
163 if (!rxq->sw_rx_ring) {
164 DP_NOTICE(edev, false,
165 "Unable to alloc memory for sw_rx_ring on socket %u\n",
172 /* Allocate FW Rx ring */
173 rc = qdev->ops->common->chain_alloc(edev,
174 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
175 ECORE_CHAIN_MODE_NEXT_PTR,
176 ECORE_CHAIN_CNT_TYPE_U16,
178 sizeof(struct eth_rx_bd),
181 if (rc != ECORE_SUCCESS) {
182 DP_NOTICE(edev, false,
183 "Unable to alloc memory for rxbd ring on socket %u\n",
185 rte_free(rxq->sw_rx_ring);
186 rxq->sw_rx_ring = NULL;
192 /* Allocate FW completion ring */
193 rc = qdev->ops->common->chain_alloc(edev,
194 ECORE_CHAIN_USE_TO_CONSUME,
195 ECORE_CHAIN_MODE_PBL,
196 ECORE_CHAIN_CNT_TYPE_U16,
198 sizeof(union eth_rx_cqe),
201 if (rc != ECORE_SUCCESS) {
202 DP_NOTICE(edev, false,
203 "Unable to alloc memory for cqe ring on socket %u\n",
205 /* TBD: Freeing RX BD ring */
206 rte_free(rxq->sw_rx_ring);
207 rxq->sw_rx_ring = NULL;
212 /* Allocate buffers for the Rx ring */
213 for (i = 0; i < rxq->nb_rx_desc; i++) {
214 rc = qede_alloc_rx_buffer(rxq);
216 DP_NOTICE(edev, false,
217 "RX buffer allocation failed at idx=%d\n", i);
222 dev->data->rx_queues[queue_idx] = rxq;
224 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
225 queue_idx, nb_desc, qdev->mtu, socket_id);
229 qede_rx_queue_release(rxq);
233 void qede_tx_queue_release(void *tx_queue)
235 struct qede_tx_queue *txq = tx_queue;
238 qede_tx_queue_release_mbufs(txq);
239 if (txq->sw_tx_ring) {
240 rte_free(txq->sw_tx_ring);
241 txq->sw_tx_ring = NULL;
249 qede_tx_queue_setup(struct rte_eth_dev *dev,
252 unsigned int socket_id,
253 const struct rte_eth_txconf *tx_conf)
255 struct qede_dev *qdev = dev->data->dev_private;
256 struct ecore_dev *edev = &qdev->edev;
257 struct qede_tx_queue *txq;
260 PMD_INIT_FUNC_TRACE(edev);
262 if (!rte_is_power_of_2(nb_desc)) {
263 DP_ERR(edev, "Ring size %u is not power of 2\n",
268 /* Free memory prior to re-allocation if needed... */
269 if (dev->data->tx_queues[queue_idx] != NULL) {
270 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
271 dev->data->tx_queues[queue_idx] = NULL;
274 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
275 RTE_CACHE_LINE_SIZE, socket_id);
279 "Unable to allocate memory for txq on socket %u",
284 txq->nb_tx_desc = nb_desc;
286 txq->port_id = dev->data->port_id;
288 rc = qdev->ops->common->chain_alloc(edev,
289 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
290 ECORE_CHAIN_MODE_PBL,
291 ECORE_CHAIN_CNT_TYPE_U16,
293 sizeof(union eth_tx_bd_types),
295 if (rc != ECORE_SUCCESS) {
297 "Unable to allocate memory for txbd ring on socket %u",
299 qede_tx_queue_release(txq);
303 /* Allocate software ring */
304 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
305 (sizeof(struct qede_tx_entry) *
307 RTE_CACHE_LINE_SIZE, socket_id);
309 if (!txq->sw_tx_ring) {
311 "Unable to allocate memory for txbd ring on socket %u",
313 qede_tx_queue_release(txq);
317 txq->queue_id = queue_idx;
319 txq->nb_tx_avail = txq->nb_tx_desc;
321 txq->tx_free_thresh =
322 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
323 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
325 dev->data->tx_queues[queue_idx] = txq;
328 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
329 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
334 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
335 static void qede_init_fp(struct qede_dev *qdev)
337 struct qede_fastpath *fp;
338 uint8_t i, rss_id, tc;
339 int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
341 memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
342 sizeof(*qdev->fp_array)));
343 memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
344 sizeof(*qdev->sb_array)));
346 fp = &qdev->fp_array[i];
348 fp->type = QEDE_FASTPATH_RX;
351 fp->type = QEDE_FASTPATH_TX;
355 fp->sb_info = &qdev->sb_array[i];
356 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
359 qdev->gro_disable = gro_disable;
362 void qede_free_fp_arrays(struct qede_dev *qdev)
364 /* It asseumes qede_free_mem_load() is called before */
365 if (qdev->fp_array != NULL) {
366 rte_free(qdev->fp_array);
367 qdev->fp_array = NULL;
370 if (qdev->sb_array != NULL) {
371 rte_free(qdev->sb_array);
372 qdev->sb_array = NULL;
376 int qede_alloc_fp_array(struct qede_dev *qdev)
378 struct qede_fastpath *fp;
379 struct ecore_dev *edev = &qdev->edev;
382 qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
383 sizeof(*qdev->fp_array),
384 RTE_CACHE_LINE_SIZE);
386 if (!qdev->fp_array) {
387 DP_ERR(edev, "fp array allocation failed\n");
391 qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
392 sizeof(*qdev->sb_array),
393 RTE_CACHE_LINE_SIZE);
395 if (!qdev->sb_array) {
396 DP_ERR(edev, "sb array allocation failed\n");
397 rte_free(qdev->fp_array);
404 /* This function allocates fast-path status block memory */
406 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
409 struct ecore_dev *edev = &qdev->edev;
410 struct status_block *sb_virt;
414 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
417 DP_ERR(edev, "Status block allocation failed\n");
421 rc = qdev->ops->common->sb_init(edev, sb_info,
422 sb_virt, sb_phys, sb_id,
423 QED_SB_TYPE_L2_QUEUE);
425 DP_ERR(edev, "Status block initialization failed\n");
426 /* TBD: No dma_free_coherent possible */
433 int qede_alloc_fp_resc(struct qede_dev *qdev)
435 struct ecore_dev *edev = &qdev->edev;
436 struct qede_fastpath *fp;
441 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
443 num_sbs = (ecore_cxt_get_proto_cid_count
444 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL)) / 2;
447 DP_ERR(edev, "No status blocks available\n");
452 qede_free_fp_arrays(qdev);
454 rc = qede_alloc_fp_array(qdev);
460 for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
461 fp = &qdev->fp_array[i];
462 if (qede_alloc_mem_sb(qdev, fp->sb_info, i % num_sbs)) {
463 qede_free_fp_arrays(qdev);
471 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
473 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
475 qede_free_mem_load(eth_dev);
476 qede_free_fp_arrays(qdev);
480 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
482 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
483 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
484 struct eth_rx_prod_data rx_prods = { 0 };
486 /* Update producers */
487 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
488 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
490 /* Make sure that the BD and SGE data is updated before updating the
491 * producers since FW might read the BD/SGE right after the producer
496 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
497 (uint32_t *)&rx_prods);
499 /* mmiowb is needed to synchronize doorbell writes from more than one
500 * processor. It guarantees that the write arrives to the device before
501 * the napi lock is released and another qede_poll is called (possibly
502 * on another CPU). Without this barrier, the next doorbell can bypass
503 * this doorbell. This is applicable to IA64/Altix systems.
507 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u\n", bd_prod, cqe_prod);
510 static inline uint32_t
511 qede_rxfh_indir_default(uint32_t index, uint32_t n_rx_rings)
513 return index % n_rx_rings;
516 static void qede_prandom_bytes(uint32_t *buff, size_t bytes)
520 srand((unsigned int)time(NULL));
522 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
527 qede_check_vport_rss_enable(struct rte_eth_dev *eth_dev,
528 struct qed_update_vport_rss_params *rss_params)
530 struct rte_eth_rss_conf rss_conf;
531 enum rte_eth_rx_mq_mode mode = eth_dev->data->dev_conf.rxmode.mq_mode;
532 struct qede_dev *qdev = eth_dev->data->dev_private;
533 struct ecore_dev *edev = &qdev->edev;
539 PMD_INIT_FUNC_TRACE(edev);
541 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
542 key = (uint32_t *)rss_conf.rss_key;
543 hf = rss_conf.rss_hf;
545 /* Check if RSS conditions are met.
546 * Note: Even though its meaningless to enable RSS with one queue, it
547 * could be used to produce RSS Hash, so skipping that check.
549 if (!(mode & ETH_MQ_RX_RSS)) {
550 DP_INFO(edev, "RSS flag is not set\n");
555 DP_INFO(edev, "Request to disable RSS\n");
559 memset(rss_params, 0, sizeof(*rss_params));
561 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
562 rss_params->rss_ind_table[i] = qede_rxfh_indir_default(i,
563 QEDE_RSS_COUNT(qdev));
566 qede_prandom_bytes(rss_params->rss_key,
567 sizeof(rss_params->rss_key));
569 memcpy(rss_params->rss_key, rss_conf.rss_key,
570 rss_conf.rss_key_len);
572 qede_init_rss_caps(&rss_caps, hf);
574 rss_params->rss_caps = rss_caps;
576 DP_INFO(edev, "RSS conditions are met\n");
581 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
583 struct qede_dev *qdev = eth_dev->data->dev_private;
584 struct ecore_dev *edev = &qdev->edev;
585 struct ecore_queue_start_common_params q_params;
586 struct qed_update_vport_rss_params *rss_params = &qdev->rss_params;
587 struct qed_dev_info *qed_info = &qdev->dev_info.common;
588 struct qed_update_vport_params vport_update_params;
589 struct qede_tx_queue *txq;
590 struct qede_fastpath *fp;
591 dma_addr_t p_phys_table;
594 int vlan_removal_en = 1;
598 fp = &qdev->fp_array[i];
599 if (fp->type & QEDE_FASTPATH_RX) {
600 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
602 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
605 memset(&q_params, 0, sizeof(q_params));
606 q_params.queue_id = i;
607 q_params.vport_id = 0;
608 q_params.sb = fp->sb_info->igu_sb_id;
609 q_params.sb_idx = RX_PI;
611 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
613 rc = qdev->ops->q_rx_start(edev, i, &q_params,
614 fp->rxq->rx_buf_size,
615 fp->rxq->rx_bd_ring.p_phys_addr,
618 &fp->rxq->hw_rxq_prod_addr);
620 DP_ERR(edev, "Start rxq #%d failed %d\n",
621 fp->rxq->queue_id, rc);
625 fp->rxq->hw_cons_ptr =
626 &fp->sb_info->sb_virt->pi_array[RX_PI];
628 qede_update_rx_prod(qdev, fp->rxq);
631 if (!(fp->type & QEDE_FASTPATH_TX))
633 for (tc = 0; tc < qdev->num_tc; tc++) {
635 txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
637 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
638 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
640 memset(&q_params, 0, sizeof(q_params));
641 q_params.queue_id = txq->queue_id;
642 q_params.vport_id = 0;
643 q_params.sb = fp->sb_info->igu_sb_id;
644 q_params.sb_idx = TX_PI(tc);
646 rc = qdev->ops->q_tx_start(edev, i, &q_params,
648 page_cnt, /* **pp_doorbell */
649 &txq->doorbell_addr);
651 DP_ERR(edev, "Start txq %u failed %d\n",
657 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
658 SET_FIELD(txq->tx_db.data.params,
659 ETH_DB_DATA_DEST, DB_DEST_XCM);
660 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
662 SET_FIELD(txq->tx_db.data.params,
663 ETH_DB_DATA_AGG_VAL_SEL,
664 DQ_XCM_ETH_TX_BD_PROD_CMD);
666 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
670 /* Prepare and send the vport enable */
671 memset(&vport_update_params, 0, sizeof(vport_update_params));
672 /* Update MTU via vport update */
673 vport_update_params.mtu = qdev->mtu;
674 vport_update_params.vport_id = 0;
675 vport_update_params.update_vport_active_flg = 1;
676 vport_update_params.vport_active_flg = 1;
679 if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
680 /* TBD: Check SRIOV enabled for VF */
681 vport_update_params.update_tx_switching_flg = 1;
682 vport_update_params.tx_switching_flg = 1;
685 if (qede_check_vport_rss_enable(eth_dev, rss_params)) {
686 vport_update_params.update_rss_flg = 1;
687 qdev->rss_enabled = 1;
689 qdev->rss_enabled = 0;
692 rte_memcpy(&vport_update_params.rss_params, rss_params,
693 sizeof(*rss_params));
695 rc = qdev->ops->vport_update(edev, &vport_update_params);
697 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
704 static bool qede_tunn_exist(uint16_t flag)
706 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
707 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
711 * qede_check_tunn_csum_l4:
713 * 1 : If L4 csum is enabled AND if the validation has failed.
716 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
718 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
719 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
720 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
721 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
726 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
728 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
729 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
730 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
731 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
736 static inline uint8_t
737 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
744 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
745 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
748 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
749 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
750 ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
751 sizeof(struct ether_hdr));
752 pkt_csum = ip->hdr_checksum;
753 ip->hdr_checksum = 0;
754 calc_csum = rte_ipv4_cksum(ip);
755 ip->hdr_checksum = pkt_csum;
756 return (calc_csum != pkt_csum);
757 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
764 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
766 ecore_chain_consume(&rxq->rx_bd_ring);
771 qede_reuse_page(struct qede_dev *qdev,
772 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
774 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
775 uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
776 struct qede_rx_entry *curr_prod;
777 dma_addr_t new_mapping;
779 curr_prod = &rxq->sw_rx_ring[idx];
780 *curr_prod = *curr_cons;
782 new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
783 curr_prod->page_offset;
785 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
786 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
792 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
793 struct qede_dev *qdev, uint8_t count)
795 struct qede_rx_entry *curr_cons;
797 for (; count > 0; count--) {
798 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
799 qede_reuse_page(qdev, rxq, curr_cons);
800 qede_rx_bd_ring_consume(rxq);
804 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
809 static const uint32_t
810 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
811 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
812 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
813 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
814 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
815 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
816 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
819 /* Bits (0..3) provides L3/L4 protocol type */
820 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
821 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
822 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
823 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
825 if (val < QEDE_PKT_TYPE_MAX)
826 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
828 return RTE_PTYPE_UNKNOWN;
831 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
836 static const uint32_t
837 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
838 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
839 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
840 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
841 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
842 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
843 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
844 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
845 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
846 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
847 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
848 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
849 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
850 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
851 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
852 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
853 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
854 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
855 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
856 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
857 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
858 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
859 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
860 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
861 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
862 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
863 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
864 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
865 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
866 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
867 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
868 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
869 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
870 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
871 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
872 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
873 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
874 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
875 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
876 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
877 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
880 /* Cover bits[4-0] to include tunn_type and next protocol */
881 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
882 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
883 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
884 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
886 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
887 return ptype_tunn_lkup_tbl[val];
889 return RTE_PTYPE_UNKNOWN;
893 int qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb,
894 int num_segs, uint16_t pkt_len)
896 struct qede_rx_queue *rxq = p_rxq;
897 struct qede_dev *qdev = rxq->qdev;
898 struct ecore_dev *edev = &qdev->edev;
899 uint16_t sw_rx_index, cur_size;
901 register struct rte_mbuf *seg1 = NULL;
902 register struct rte_mbuf *seg2 = NULL;
906 cur_size = pkt_len > rxq->rx_buf_size ?
907 rxq->rx_buf_size : pkt_len;
909 PMD_RX_LOG(DEBUG, rxq,
910 "SG packet, len and num BD mismatch\n");
911 qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
915 if (qede_alloc_rx_buffer(rxq)) {
918 PMD_RX_LOG(DEBUG, rxq, "Buffer allocation failed\n");
919 index = rxq->port_id;
920 rte_eth_devices[index].data->rx_mbuf_alloc_failed++;
921 rxq->rx_alloc_errors++;
925 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
926 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
927 qede_rx_bd_ring_consume(rxq);
929 seg2->data_len = cur_size;
939 PMD_RX_LOG(DEBUG, rxq,
940 "Mapped all BDs of jumbo, but still have %d bytes\n",
943 return ECORE_SUCCESS;
947 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
949 struct qede_rx_queue *rxq = p_rxq;
950 struct qede_dev *qdev = rxq->qdev;
951 struct ecore_dev *edev = &qdev->edev;
952 struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
953 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
955 union eth_rx_cqe *cqe;
956 struct eth_fast_path_rx_reg_cqe *fp_cqe;
957 register struct rte_mbuf *rx_mb = NULL;
958 register struct rte_mbuf *seg1 = NULL;
959 enum eth_rx_cqe_type cqe_type;
960 uint16_t len, pad, preload_idx, pkt_len, parse_flag;
961 uint8_t csum_flag, num_segs;
962 enum rss_hash_type htype;
963 uint8_t tunn_parse_flag;
966 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
967 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
971 if (hw_comp_cons == sw_comp_cons)
974 while (sw_comp_cons != hw_comp_cons) {
975 /* Get the CQE from the completion ring */
977 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
978 cqe_type = cqe->fast_path_regular.type;
980 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
981 PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE\n");
983 qdev->ops->eth_cqe_completion(edev, fp->id,
984 (struct eth_slow_path_rx_cqe *)cqe);
988 /* Get the data from the SW ring */
989 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
990 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
991 assert(rx_mb != NULL);
994 fp_cqe = &cqe->fast_path_regular;
996 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
997 pad = fp_cqe->placement_offset;
998 assert((len + pad) <= rx_mb->buf_len);
1000 PMD_RX_LOG(DEBUG, rxq,
1001 "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
1002 " len = %u, parsing_flags = %d\n",
1003 cqe_type, fp_cqe->bitfields,
1004 rte_le_to_cpu_16(fp_cqe->vlan_tag),
1005 len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
1007 /* If this is an error packet then drop it */
1009 rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
1011 rx_mb->ol_flags = 0;
1013 if (qede_tunn_exist(parse_flag)) {
1014 PMD_RX_LOG(DEBUG, rxq, "Rx tunneled packet\n");
1015 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1016 PMD_RX_LOG(ERR, rxq,
1017 "L4 csum failed, flags = 0x%x\n",
1019 rxq->rx_hw_errors++;
1020 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1023 fp_cqe->tunnel_pars_flags.flags;
1024 rx_mb->packet_type =
1025 qede_rx_cqe_to_tunn_pkt_type(
1029 PMD_RX_LOG(DEBUG, rxq, "Rx non-tunneled packet\n");
1030 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1031 PMD_RX_LOG(ERR, rxq,
1032 "L4 csum failed, flags = 0x%x\n",
1034 rxq->rx_hw_errors++;
1035 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1036 } else if (unlikely(qede_check_notunn_csum_l3(rx_mb,
1038 PMD_RX_LOG(ERR, rxq,
1039 "IP csum failed, flags = 0x%x\n",
1041 rxq->rx_hw_errors++;
1042 rx_mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1044 rx_mb->packet_type =
1045 qede_rx_cqe_to_pkt_type(parse_flag);
1049 PMD_RX_LOG(INFO, rxq, "packet_type 0x%x\n", rx_mb->packet_type);
1051 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1052 PMD_RX_LOG(ERR, rxq,
1053 "New buffer allocation failed,"
1054 "dropping incoming packet\n");
1055 qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1056 rte_eth_devices[rxq->port_id].
1057 data->rx_mbuf_alloc_failed++;
1058 rxq->rx_alloc_errors++;
1062 qede_rx_bd_ring_consume(rxq);
1064 if (fp_cqe->bd_num > 1) {
1065 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1066 num_segs = fp_cqe->bd_num - 1;
1072 ret = qede_process_sg_pkts(p_rxq, seg1, num_segs,
1074 if (ret != ECORE_SUCCESS) {
1075 qede_recycle_rx_bd_ring(rxq, qdev,
1081 /* Prefetch next mbuf while processing current one. */
1082 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1083 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1085 /* Update rest of the MBUF fields */
1086 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
1087 rx_mb->nb_segs = fp_cqe->bd_num;
1088 rx_mb->data_len = len;
1089 rx_mb->pkt_len = fp_cqe->pkt_len;
1090 rx_mb->port = rxq->port_id;
1092 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
1093 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1094 if (qdev->rss_enabled && htype) {
1095 rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1096 rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1097 PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x\n",
1101 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1103 if (CQE_HAS_VLAN(parse_flag)) {
1104 rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1105 rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1108 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1109 /* FW does not provide indication of Outer VLAN tag,
1110 * which is always stripped, so vlan_tci_outer is set
1111 * to 0. Here vlan_tag represents inner VLAN tag.
1113 rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1114 rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1115 rx_mb->vlan_tci_outer = 0;
1118 rx_pkts[rx_pkt] = rx_mb;
1121 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1122 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1123 if (rx_pkt == nb_pkts) {
1124 PMD_RX_LOG(DEBUG, rxq,
1125 "Budget reached nb_pkts=%u received=%u\n",
1131 qede_update_rx_prod(qdev, rxq);
1133 rxq->rcv_pkts += rx_pkt;
1135 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d\n", rx_pkt, rte_lcore_id());
1141 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1143 uint16_t nb_segs, idx = TX_CONS(txq);
1144 struct eth_tx_bd *tx_data_bd;
1145 struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1147 if (unlikely(!mbuf)) {
1148 PMD_TX_LOG(ERR, txq, "null mbuf\n");
1149 PMD_TX_LOG(ERR, txq,
1150 "tx_desc %u tx_avail %u tx_cons %u tx_prod %u\n",
1151 txq->nb_tx_desc, txq->nb_tx_avail, idx,
1156 nb_segs = mbuf->nb_segs;
1158 /* It's like consuming rxbuf in recv() */
1159 ecore_chain_consume(&txq->tx_pbl);
1163 rte_pktmbuf_free(mbuf);
1164 txq->sw_tx_ring[idx].mbuf = NULL;
1169 static inline uint16_t
1170 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1172 uint16_t tx_compl = 0;
1173 uint16_t hw_bd_cons;
1175 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1176 rte_compiler_barrier();
1178 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1179 if (qede_free_tx_pkt(edev, txq)) {
1180 PMD_TX_LOG(ERR, txq,
1181 "hw_bd_cons = %u, chain_cons = %u\n",
1183 ecore_chain_get_cons_idx(&txq->tx_pbl));
1186 txq->sw_tx_cons++; /* Making TXD available */
1190 PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u\n",
1191 tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1195 /* Populate scatter gather buffer descriptor fields */
1196 static inline uint16_t qede_encode_sg_bd(struct qede_tx_queue *p_txq,
1197 struct rte_mbuf *m_seg,
1199 struct eth_tx_1st_bd *bd1)
1201 struct qede_tx_queue *txq = p_txq;
1202 struct eth_tx_2nd_bd *bd2 = NULL;
1203 struct eth_tx_3rd_bd *bd3 = NULL;
1204 struct eth_tx_bd *tx_bd = NULL;
1205 uint16_t nb_segs = count;
1208 /* Check for scattered buffers */
1211 bd2 = (struct eth_tx_2nd_bd *)
1212 ecore_chain_produce(&txq->tx_pbl);
1213 memset(bd2, 0, sizeof(*bd2));
1214 mapping = rte_mbuf_data_dma_addr(m_seg);
1215 bd2->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1216 bd2->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1217 bd2->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1218 } else if (nb_segs == 2) {
1219 bd3 = (struct eth_tx_3rd_bd *)
1220 ecore_chain_produce(&txq->tx_pbl);
1221 memset(bd3, 0, sizeof(*bd3));
1222 mapping = rte_mbuf_data_dma_addr(m_seg);
1223 bd3->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1224 bd3->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1225 bd3->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1227 tx_bd = (struct eth_tx_bd *)
1228 ecore_chain_produce(&txq->tx_pbl);
1229 memset(tx_bd, 0, sizeof(*tx_bd));
1230 mapping = rte_mbuf_data_dma_addr(m_seg);
1231 tx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1232 tx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1233 tx_bd->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1236 bd1->data.nbds = nb_segs;
1237 m_seg = m_seg->next;
1240 /* Return total scattered buffers */
1245 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1247 struct qede_tx_queue *txq = p_txq;
1248 struct qede_dev *qdev = txq->qdev;
1249 struct ecore_dev *edev = &qdev->edev;
1250 struct qede_fastpath *fp;
1251 struct eth_tx_1st_bd *bd1;
1252 struct rte_mbuf *m_seg = NULL;
1253 uint16_t nb_tx_pkts;
1254 uint16_t nb_pkt_sent = 0;
1258 uint16_t nb_segs = 0;
1260 fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1262 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1263 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u\n",
1264 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1265 (void)qede_process_tx_compl(edev, txq);
1268 nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1269 ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1270 if (unlikely(nb_tx_pkts == 0)) {
1271 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u\n",
1272 nb_pkts, txq->nb_tx_avail);
1276 tx_count = nb_tx_pkts;
1277 while (nb_tx_pkts--) {
1278 /* Fill the entry in the SW ring and the BDs in the FW ring */
1280 struct rte_mbuf *mbuf = *tx_pkts++;
1282 txq->sw_tx_ring[idx].mbuf = mbuf;
1283 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1284 /* Zero init struct fields */
1285 bd1->data.bd_flags.bitfields = 0;
1286 bd1->data.bitfields = 0;
1288 bd1->data.bd_flags.bitfields =
1289 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1290 /* Map MBUF linear data for DMA and set in the first BD */
1291 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1294 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type)) {
1295 PMD_TX_LOG(INFO, txq, "Tx tunnel packet\n");
1296 /* First indicate its a tunnel pkt */
1297 bd1->data.bd_flags.bitfields |=
1298 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1299 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1301 /* Legacy FW had flipped behavior in regard to this bit
1302 * i.e. it needed to set to prevent FW from touching
1303 * encapsulated packets when it didn't need to.
1305 if (unlikely(txq->is_legacy))
1306 bd1->data.bitfields ^=
1307 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1309 /* Outer IP checksum offload */
1310 if (mbuf->ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1311 PMD_TX_LOG(INFO, txq, "OuterIP csum offload\n");
1312 bd1->data.bd_flags.bitfields |=
1313 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1314 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1317 /* Outer UDP checksum offload */
1318 bd1->data.bd_flags.bitfields |=
1319 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1320 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1323 /* Descriptor based VLAN insertion */
1324 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1325 PMD_TX_LOG(INFO, txq, "Insert VLAN 0x%x\n",
1327 bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1328 bd1->data.bd_flags.bitfields |=
1329 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1332 /* Offload the IP checksum in the hardware */
1333 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1334 PMD_TX_LOG(INFO, txq, "IP csum offload\n");
1335 bd1->data.bd_flags.bitfields |=
1336 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1339 /* L4 checksum offload (tcp or udp) */
1340 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1341 PMD_TX_LOG(INFO, txq, "L4 csum offload\n");
1342 bd1->data.bd_flags.bitfields |=
1343 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1344 /* IPv6 + extn. -> later */
1347 /* Handle fragmented MBUF */
1350 bd1->data.nbds = nb_segs;
1351 /* Encode scatter gather buffer descriptors if required */
1352 nb_segs = qede_encode_sg_bd(txq, m_seg, nb_segs, bd1);
1353 txq->nb_tx_avail = txq->nb_tx_avail - nb_segs;
1356 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1358 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1363 /* Write value of prod idx into bd_prod */
1364 txq->tx_db.data.bd_prod = bd_prod;
1366 rte_compiler_barrier();
1367 DIRECT_REG_WR(edev, txq->doorbell_addr, txq->tx_db.raw);
1370 /* Check again for Tx completions */
1371 (void)qede_process_tx_compl(edev, txq);
1373 PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d\n",
1374 nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1379 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1381 struct qede_dev *qdev = eth_dev->data->dev_private;
1382 struct qede_fastpath *fp;
1383 uint8_t i, rss_id, txq_index, tc;
1384 int rxq = 0, txq = 0;
1387 fp = &qdev->fp_array[i];
1388 if (fp->type & QEDE_FASTPATH_RX) {
1389 fp->rxq = eth_dev->data->rx_queues[i];
1390 fp->rxq->queue_id = rxq++;
1393 if (fp->type & QEDE_FASTPATH_TX) {
1394 for (tc = 0; tc < qdev->num_tc; tc++) {
1395 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1397 eth_dev->data->tx_queues[txq_index];
1398 fp->txqs[tc]->queue_id = txq_index;
1399 if (qdev->dev_info.is_legacy)
1400 fp->txqs[tc]->is_legacy = true;
1407 int qede_dev_start(struct rte_eth_dev *eth_dev)
1409 struct qede_dev *qdev = eth_dev->data->dev_private;
1410 struct ecore_dev *edev = &qdev->edev;
1411 struct qed_link_output link_output;
1412 struct qede_fastpath *fp;
1415 DP_INFO(edev, "Device state is %d\n", qdev->state);
1417 if (qdev->state == QEDE_DEV_START) {
1418 DP_INFO(edev, "Port is already started\n");
1422 if (qdev->state == QEDE_DEV_CONFIG)
1423 qede_init_fp_queue(eth_dev);
1425 rc = qede_start_queues(eth_dev, true);
1427 DP_ERR(edev, "Failed to start queues\n");
1432 /* Bring-up the link */
1433 qede_dev_set_link_state(eth_dev, true);
1436 if (qede_reset_fp_rings(qdev))
1439 /* Start/resume traffic */
1440 qdev->ops->fastpath_start(edev);
1442 qdev->state = QEDE_DEV_START;
1444 DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1449 static int qede_drain_txq(struct qede_dev *qdev,
1450 struct qede_tx_queue *txq, bool allow_drain)
1452 struct ecore_dev *edev = &qdev->edev;
1455 while (txq->sw_tx_cons != txq->sw_tx_prod) {
1456 qede_process_tx_compl(edev, txq);
1459 DP_NOTICE(edev, false,
1460 "Tx queue[%u] is stuck,"
1461 "requesting MCP to drain\n",
1463 rc = qdev->ops->common->drain(edev);
1466 return qede_drain_txq(qdev, txq, false);
1469 DP_NOTICE(edev, false,
1470 "Timeout waiting for tx queue[%d]:"
1471 "PROD=%d, CONS=%d\n",
1472 txq->queue_id, txq->sw_tx_prod,
1478 rte_compiler_barrier();
1481 /* FW finished processing, wait for HW to transmit all tx packets */
1487 static int qede_stop_queues(struct qede_dev *qdev)
1489 struct qed_update_vport_params vport_update_params;
1490 struct ecore_dev *edev = &qdev->edev;
1493 /* Disable the vport */
1494 memset(&vport_update_params, 0, sizeof(vport_update_params));
1495 vport_update_params.vport_id = 0;
1496 vport_update_params.update_vport_active_flg = 1;
1497 vport_update_params.vport_active_flg = 0;
1498 vport_update_params.update_rss_flg = 0;
1500 DP_INFO(edev, "Deactivate vport\n");
1502 rc = qdev->ops->vport_update(edev, &vport_update_params);
1504 DP_ERR(edev, "Failed to update vport\n");
1508 DP_INFO(edev, "Flushing tx queues\n");
1510 /* Flush Tx queues. If needed, request drain from MCP */
1512 struct qede_fastpath *fp = &qdev->fp_array[i];
1514 if (fp->type & QEDE_FASTPATH_TX) {
1515 for (tc = 0; tc < qdev->num_tc; tc++) {
1516 struct qede_tx_queue *txq = fp->txqs[tc];
1518 rc = qede_drain_txq(qdev, txq, true);
1525 /* Stop all Queues in reverse order */
1526 for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1527 struct qed_stop_rxq_params rx_params;
1529 /* Stop the Tx Queue(s) */
1530 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1531 for (tc = 0; tc < qdev->num_tc; tc++) {
1532 struct qed_stop_txq_params tx_params;
1535 tx_params.rss_id = i;
1536 val = qdev->fp_array[i].txqs[tc]->queue_id;
1537 tx_params.tx_queue_id = val;
1539 DP_INFO(edev, "Stopping tx queues\n");
1540 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1542 DP_ERR(edev, "Failed to stop TXQ #%d\n",
1543 tx_params.tx_queue_id);
1549 /* Stop the Rx Queue */
1550 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1551 memset(&rx_params, 0, sizeof(rx_params));
1552 rx_params.rss_id = i;
1553 rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1554 rx_params.eq_completion_only = 1;
1556 DP_INFO(edev, "Stopping rx queues\n");
1558 rc = qdev->ops->q_rx_stop(edev, &rx_params);
1560 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1569 int qede_reset_fp_rings(struct qede_dev *qdev)
1571 struct qede_fastpath *fp;
1572 struct qede_tx_queue *txq;
1576 for_each_queue(id) {
1577 fp = &qdev->fp_array[id];
1579 if (fp->type & QEDE_FASTPATH_RX) {
1580 DP_INFO(&qdev->edev,
1581 "Reset FP chain for RSS %u\n", id);
1582 qede_rx_queue_release_mbufs(fp->rxq);
1583 ecore_chain_reset(&fp->rxq->rx_bd_ring);
1584 ecore_chain_reset(&fp->rxq->rx_comp_ring);
1585 fp->rxq->sw_rx_prod = 0;
1586 fp->rxq->sw_rx_cons = 0;
1587 *fp->rxq->hw_cons_ptr = 0;
1588 for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1589 if (qede_alloc_rx_buffer(fp->rxq)) {
1591 "RX buffer allocation failed\n");
1596 if (fp->type & QEDE_FASTPATH_TX) {
1597 for (tc = 0; tc < qdev->num_tc; tc++) {
1599 qede_tx_queue_release_mbufs(txq);
1600 ecore_chain_reset(&txq->tx_pbl);
1601 txq->sw_tx_cons = 0;
1602 txq->sw_tx_prod = 0;
1603 *txq->hw_cons_ptr = 0;
1611 /* This function frees all memory of a single fp */
1612 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1614 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1615 struct qede_fastpath *fp;
1620 for_each_queue(id) {
1621 fp = &qdev->fp_array[id];
1622 if (fp->type & QEDE_FASTPATH_RX) {
1623 qede_rx_queue_release(fp->rxq);
1624 eth_dev->data->rx_queues[id] = NULL;
1626 for (tc = 0; tc < qdev->num_tc; tc++) {
1627 txq_idx = fp->txqs[tc]->queue_id;
1628 qede_tx_queue_release(fp->txqs[tc]);
1629 eth_dev->data->tx_queues[txq_idx] = NULL;
1635 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1637 struct qede_dev *qdev = eth_dev->data->dev_private;
1638 struct ecore_dev *edev = &qdev->edev;
1640 DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1642 if (qdev->state != QEDE_DEV_START) {
1643 DP_INFO(edev, "Device not yet started\n");
1647 if (qede_stop_queues(qdev))
1648 DP_ERR(edev, "Didn't succeed to close queues\n");
1650 DP_INFO(edev, "Stopped queues\n");
1652 qdev->ops->fastpath_stop(edev);
1654 /* Bring the link down */
1655 qede_dev_set_link_state(eth_dev, false);
1657 qdev->state = QEDE_DEV_STOP;
1659 DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");