1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
10 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
12 struct rte_mbuf *new_mb = NULL;
13 struct eth_rx_bd *rx_bd;
15 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
17 new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
18 if (unlikely(!new_mb)) {
20 "Failed to allocate rx buffer "
21 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
22 idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
23 rte_mempool_avail_count(rxq->mb_pool),
24 rte_mempool_in_use_count(rxq->mb_pool));
27 rxq->sw_rx_ring[idx].mbuf = new_mb;
28 rxq->sw_rx_ring[idx].page_offset = 0;
29 mapping = rte_mbuf_data_iova_default(new_mb);
30 /* Advance PROD and get BD pointer */
31 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
32 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
33 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
38 #define QEDE_MAX_BULK_ALLOC_COUNT 512
40 static inline int qede_alloc_rx_bulk_mbufs(struct qede_rx_queue *rxq, int count)
42 void *obj_p[QEDE_MAX_BULK_ALLOC_COUNT] __rte_cache_aligned;
43 struct rte_mbuf *mbuf = NULL;
44 struct eth_rx_bd *rx_bd;
49 if (count > QEDE_MAX_BULK_ALLOC_COUNT)
50 count = QEDE_MAX_BULK_ALLOC_COUNT;
52 ret = rte_mempool_get_bulk(rxq->mb_pool, obj_p, count);
55 "Failed to allocate %d rx buffers "
56 "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
58 rxq->sw_rx_prod & NUM_RX_BDS(rxq),
59 rxq->sw_rx_cons & NUM_RX_BDS(rxq),
60 rte_mempool_avail_count(rxq->mb_pool),
61 rte_mempool_in_use_count(rxq->mb_pool));
65 for (i = 0; i < count; i++) {
67 if (likely(i < count - 1))
68 rte_prefetch0(obj_p[i + 1]);
70 idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
71 rxq->sw_rx_ring[idx].mbuf = mbuf;
72 rxq->sw_rx_ring[idx].page_offset = 0;
73 mapping = rte_mbuf_data_iova_default(mbuf);
74 rx_bd = (struct eth_rx_bd *)
75 ecore_chain_produce(&rxq->rx_bd_ring);
76 rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
77 rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
84 /* Criterias for calculating Rx buffer size -
85 * 1) rx_buf_size should not exceed the size of mbuf
86 * 2) In scattered_rx mode - minimum rx_buf_size should be
87 * (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT
88 * 3) In regular mode - minimum rx_buf_size should be
89 * (MTU + Maximum L2 Header Size + 2)
90 * In above cases +2 corrosponds to 2 bytes padding in front of L2
92 * 4) rx_buf_size should be cacheline-size aligned. So considering
93 * criteria 1, we need to adjust the size to floor instead of ceil,
94 * so that we don't exceed mbuf size while ceiling rx_buf_size.
97 qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
98 uint16_t max_frame_size)
100 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
101 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
104 if (dev->data->scattered_rx) {
105 /* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of
106 * bufferes can be used for single packet. So need to make sure
107 * mbuf size is sufficient enough for this.
109 if ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <
110 (max_frame_size + QEDE_ETH_OVERHEAD)) {
111 DP_ERR(edev, "mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\n",
112 mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);
116 rx_buf_size = RTE_MAX(mbufsz,
117 (max_frame_size + QEDE_ETH_OVERHEAD) /
118 ETH_RX_MAX_BUFF_PER_PKT);
120 rx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;
123 /* Align to cache-line size if needed */
124 return QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);
127 static struct qede_rx_queue *
128 qede_alloc_rx_queue_mem(struct rte_eth_dev *dev,
131 unsigned int socket_id,
132 struct rte_mempool *mp,
135 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
136 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
137 struct qede_rx_queue *rxq;
141 /* First allocate the rx queue data structure */
142 rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
143 RTE_CACHE_LINE_SIZE, socket_id);
146 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
153 rxq->nb_rx_desc = nb_desc;
154 rxq->queue_id = queue_idx;
155 rxq->port_id = dev->data->port_id;
158 rxq->rx_buf_size = bufsz;
160 DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
161 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
163 /* Allocate the parallel driver ring for Rx buffers */
164 size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
165 rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
166 RTE_CACHE_LINE_SIZE, socket_id);
167 if (!rxq->sw_rx_ring) {
168 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
169 " socket %u\n", socket_id);
174 /* Allocate FW Rx ring */
175 rc = qdev->ops->common->chain_alloc(edev,
176 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
177 ECORE_CHAIN_MODE_NEXT_PTR,
178 ECORE_CHAIN_CNT_TYPE_U16,
180 sizeof(struct eth_rx_bd),
184 if (rc != ECORE_SUCCESS) {
185 DP_ERR(edev, "Memory allocation fails for RX BD ring"
186 " on socket %u\n", socket_id);
187 rte_free(rxq->sw_rx_ring);
192 /* Allocate FW completion ring */
193 rc = qdev->ops->common->chain_alloc(edev,
194 ECORE_CHAIN_USE_TO_CONSUME,
195 ECORE_CHAIN_MODE_PBL,
196 ECORE_CHAIN_CNT_TYPE_U16,
198 sizeof(union eth_rx_cqe),
202 if (rc != ECORE_SUCCESS) {
203 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
204 " on socket %u\n", socket_id);
205 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
206 rte_free(rxq->sw_rx_ring);
215 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qid,
216 uint16_t nb_desc, unsigned int socket_id,
217 __rte_unused const struct rte_eth_rxconf *rx_conf,
218 struct rte_mempool *mp)
220 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
221 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
222 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
223 struct qede_rx_queue *rxq;
224 uint16_t max_rx_pkt_len;
228 PMD_INIT_FUNC_TRACE(edev);
230 /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
231 if (!rte_is_power_of_2(nb_desc)) {
232 DP_ERR(edev, "Ring size %u is not power of 2\n",
237 /* Free memory prior to re-allocation if needed... */
238 if (dev->data->rx_queues[qid] != NULL) {
239 qede_rx_queue_release(dev->data->rx_queues[qid]);
240 dev->data->rx_queues[qid] = NULL;
243 max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
245 /* Fix up RX buffer size */
246 bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
247 /* cache align the mbuf size to simplfy rx_buf_size calculation */
248 bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
249 if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
250 (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
251 if (!dev->data->scattered_rx) {
252 DP_INFO(edev, "Forcing scatter-gather mode\n");
253 dev->data->scattered_rx = 1;
257 rc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);
263 if (ECORE_IS_CMT(edev)) {
264 rxq = qede_alloc_rx_queue_mem(dev, qid * 2, nb_desc,
265 socket_id, mp, bufsz);
269 qdev->fp_array[qid * 2].rxq = rxq;
270 rxq = qede_alloc_rx_queue_mem(dev, qid * 2 + 1, nb_desc,
271 socket_id, mp, bufsz);
275 qdev->fp_array[qid * 2 + 1].rxq = rxq;
276 /* provide per engine fp struct as rx queue */
277 dev->data->rx_queues[qid] = &qdev->fp_array_cmt[qid];
279 rxq = qede_alloc_rx_queue_mem(dev, qid, nb_desc,
280 socket_id, mp, bufsz);
284 dev->data->rx_queues[qid] = rxq;
285 qdev->fp_array[qid].rxq = rxq;
288 DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
289 qid, nb_desc, rxq->rx_buf_size, socket_id);
295 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
296 struct qede_rx_queue *rxq)
298 DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
299 ecore_chain_reset(&rxq->rx_bd_ring);
300 ecore_chain_reset(&rxq->rx_comp_ring);
303 *rxq->hw_cons_ptr = 0;
306 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
310 if (rxq->sw_rx_ring) {
311 for (i = 0; i < rxq->nb_rx_desc; i++) {
312 if (rxq->sw_rx_ring[i].mbuf) {
313 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
314 rxq->sw_rx_ring[i].mbuf = NULL;
320 static void _qede_rx_queue_release(struct qede_dev *qdev,
321 struct ecore_dev *edev,
322 struct qede_rx_queue *rxq)
324 qede_rx_queue_release_mbufs(rxq);
325 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
326 qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
327 rte_free(rxq->sw_rx_ring);
331 void qede_rx_queue_release(void *rx_queue)
333 struct qede_rx_queue *rxq = rx_queue;
334 struct qede_fastpath_cmt *fp_cmt;
335 struct qede_dev *qdev;
336 struct ecore_dev *edev;
340 edev = QEDE_INIT_EDEV(qdev);
341 PMD_INIT_FUNC_TRACE(edev);
342 if (ECORE_IS_CMT(edev)) {
344 _qede_rx_queue_release(qdev, edev, fp_cmt->fp0->rxq);
345 _qede_rx_queue_release(qdev, edev, fp_cmt->fp1->rxq);
347 _qede_rx_queue_release(qdev, edev, rxq);
352 /* Stops a given RX queue in the HW */
353 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
355 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
356 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
357 struct ecore_hwfn *p_hwfn;
358 struct qede_rx_queue *rxq;
362 if (rx_queue_id < qdev->num_rx_queues) {
363 rxq = qdev->fp_array[rx_queue_id].rxq;
364 hwfn_index = rx_queue_id % edev->num_hwfns;
365 p_hwfn = &edev->hwfns[hwfn_index];
366 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
368 if (rc != ECORE_SUCCESS) {
369 DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
372 qede_rx_queue_release_mbufs(rxq);
373 qede_rx_queue_reset(qdev, rxq);
374 eth_dev->data->rx_queue_state[rx_queue_id] =
375 RTE_ETH_QUEUE_STATE_STOPPED;
376 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
378 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
385 static struct qede_tx_queue *
386 qede_alloc_tx_queue_mem(struct rte_eth_dev *dev,
389 unsigned int socket_id,
390 const struct rte_eth_txconf *tx_conf)
392 struct qede_dev *qdev = dev->data->dev_private;
393 struct ecore_dev *edev = &qdev->edev;
394 struct qede_tx_queue *txq;
397 txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
398 RTE_CACHE_LINE_SIZE, socket_id);
402 "Unable to allocate memory for txq on socket %u",
407 txq->nb_tx_desc = nb_desc;
409 txq->port_id = dev->data->port_id;
411 rc = qdev->ops->common->chain_alloc(edev,
412 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
413 ECORE_CHAIN_MODE_PBL,
414 ECORE_CHAIN_CNT_TYPE_U16,
416 sizeof(union eth_tx_bd_types),
419 if (rc != ECORE_SUCCESS) {
421 "Unable to allocate memory for txbd ring on socket %u",
423 qede_tx_queue_release(txq);
427 /* Allocate software ring */
428 txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
429 (sizeof(struct qede_tx_entry) *
431 RTE_CACHE_LINE_SIZE, socket_id);
433 if (!txq->sw_tx_ring) {
435 "Unable to allocate memory for txbd ring on socket %u",
437 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
438 qede_tx_queue_release(txq);
442 txq->queue_id = queue_idx;
444 txq->nb_tx_avail = txq->nb_tx_desc;
446 txq->tx_free_thresh =
447 tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
448 (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
451 "txq %u num_desc %u tx_free_thresh %u socket %u\n",
452 queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
457 qede_tx_queue_setup(struct rte_eth_dev *dev,
460 unsigned int socket_id,
461 const struct rte_eth_txconf *tx_conf)
463 struct qede_dev *qdev = dev->data->dev_private;
464 struct ecore_dev *edev = &qdev->edev;
465 struct qede_tx_queue *txq;
467 PMD_INIT_FUNC_TRACE(edev);
469 if (!rte_is_power_of_2(nb_desc)) {
470 DP_ERR(edev, "Ring size %u is not power of 2\n",
475 /* Free memory prior to re-allocation if needed... */
476 if (dev->data->tx_queues[queue_idx] != NULL) {
477 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
478 dev->data->tx_queues[queue_idx] = NULL;
481 if (ECORE_IS_CMT(edev)) {
482 txq = qede_alloc_tx_queue_mem(dev, queue_idx * 2, nb_desc,
487 qdev->fp_array[queue_idx * 2].txq = txq;
488 txq = qede_alloc_tx_queue_mem(dev, (queue_idx * 2) + 1, nb_desc,
493 qdev->fp_array[(queue_idx * 2) + 1].txq = txq;
494 dev->data->tx_queues[queue_idx] =
495 &qdev->fp_array_cmt[queue_idx];
497 txq = qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc,
502 dev->data->tx_queues[queue_idx] = txq;
503 qdev->fp_array[queue_idx].txq = txq;
510 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
511 struct qede_tx_queue *txq)
513 DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
514 ecore_chain_reset(&txq->tx_pbl);
517 *txq->hw_cons_ptr = 0;
520 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
524 if (txq->sw_tx_ring) {
525 for (i = 0; i < txq->nb_tx_desc; i++) {
526 if (txq->sw_tx_ring[i].mbuf) {
527 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
528 txq->sw_tx_ring[i].mbuf = NULL;
534 static void _qede_tx_queue_release(struct qede_dev *qdev,
535 struct ecore_dev *edev,
536 struct qede_tx_queue *txq)
538 qede_tx_queue_release_mbufs(txq);
539 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
540 rte_free(txq->sw_tx_ring);
544 void qede_tx_queue_release(void *tx_queue)
546 struct qede_tx_queue *txq = tx_queue;
547 struct qede_fastpath_cmt *fp_cmt;
548 struct qede_dev *qdev;
549 struct ecore_dev *edev;
553 edev = QEDE_INIT_EDEV(qdev);
554 PMD_INIT_FUNC_TRACE(edev);
556 if (ECORE_IS_CMT(edev)) {
558 _qede_tx_queue_release(qdev, edev, fp_cmt->fp0->txq);
559 _qede_tx_queue_release(qdev, edev, fp_cmt->fp1->txq);
561 _qede_tx_queue_release(qdev, edev, txq);
566 /* This function allocates fast-path status block memory */
568 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
571 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
572 struct status_block *sb_virt;
576 sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
577 sizeof(struct status_block));
579 DP_ERR(edev, "Status block allocation failed\n");
582 rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
585 DP_ERR(edev, "Status block initialization failed\n");
586 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
587 sizeof(struct status_block));
594 int qede_alloc_fp_resc(struct qede_dev *qdev)
596 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
597 struct qede_fastpath *fp;
602 PMD_INIT_FUNC_TRACE(edev);
605 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
607 num_sbs = ecore_cxt_get_proto_cid_count
608 (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
611 DP_ERR(edev, "No status blocks available\n");
615 qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
616 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
618 if (!qdev->fp_array) {
619 DP_ERR(edev, "fp array allocation failed\n");
623 memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
624 sizeof(*qdev->fp_array));
626 if (ECORE_IS_CMT(edev)) {
627 qdev->fp_array_cmt = rte_calloc("fp_cmt",
628 QEDE_RXTX_MAX(qdev) / 2,
629 sizeof(*qdev->fp_array_cmt),
630 RTE_CACHE_LINE_SIZE);
632 if (!qdev->fp_array_cmt) {
633 DP_ERR(edev, "fp array for CMT allocation failed\n");
637 memset((void *)qdev->fp_array_cmt, 0,
638 (QEDE_RXTX_MAX(qdev) / 2) * sizeof(*qdev->fp_array_cmt));
640 /* Establish the mapping of fp_array with fp_array_cmt */
641 for (i = 0; i < QEDE_RXTX_MAX(qdev) / 2; i++) {
642 qdev->fp_array_cmt[i].qdev = qdev;
643 qdev->fp_array_cmt[i].fp0 = &qdev->fp_array[i * 2];
644 qdev->fp_array_cmt[i].fp1 = &qdev->fp_array[i * 2 + 1];
648 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
649 fp = &qdev->fp_array[sb_idx];
652 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
653 RTE_CACHE_LINE_SIZE);
655 DP_ERR(edev, "FP sb_info allocation fails\n");
658 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
659 DP_ERR(edev, "FP status block allocation fails\n");
662 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
663 fp->sb_info->igu_sb_id);
669 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
671 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
672 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
673 struct qede_fastpath *fp;
677 PMD_INIT_FUNC_TRACE(edev);
679 for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
680 fp = &qdev->fp_array[sb_idx];
683 DP_INFO(edev, "Free sb_info index 0x%x\n",
684 fp->sb_info->igu_sb_id);
686 OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
687 fp->sb_info->sb_phys,
688 sizeof(struct status_block));
689 rte_free(fp->sb_info);
694 /* Free packet buffers and ring memories */
695 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
696 if (eth_dev->data->rx_queues[i]) {
697 qede_rx_queue_release(eth_dev->data->rx_queues[i]);
698 eth_dev->data->rx_queues[i] = NULL;
702 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
703 if (eth_dev->data->tx_queues[i]) {
704 qede_tx_queue_release(eth_dev->data->tx_queues[i]);
705 eth_dev->data->tx_queues[i] = NULL;
710 rte_free(qdev->fp_array);
711 qdev->fp_array = NULL;
713 if (qdev->fp_array_cmt)
714 rte_free(qdev->fp_array_cmt);
715 qdev->fp_array_cmt = NULL;
719 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
720 struct qede_rx_queue *rxq)
722 uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
723 uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
724 struct eth_rx_prod_data rx_prods = { 0 };
726 /* Update producers */
727 rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
728 rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
730 /* Make sure that the BD and SGE data is updated before updating the
731 * producers since FW might read the BD/SGE right after the producer
736 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
737 (uint32_t *)&rx_prods);
739 /* mmiowb is needed to synchronize doorbell writes from more than one
740 * processor. It guarantees that the write arrives to the device before
741 * the napi lock is released and another qede_poll is called (possibly
742 * on another CPU). Without this barrier, the next doorbell can bypass
743 * this doorbell. This is applicable to IA64/Altix systems.
747 PMD_RX_LOG(DEBUG, rxq, "bd_prod %u cqe_prod %u", bd_prod, cqe_prod);
750 /* Starts a given RX queue in HW */
752 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
754 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
755 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
756 struct ecore_queue_start_common_params params;
757 struct ecore_rxq_start_ret_params ret_params;
758 struct qede_rx_queue *rxq;
759 struct qede_fastpath *fp;
760 struct ecore_hwfn *p_hwfn;
761 dma_addr_t p_phys_table;
767 if (rx_queue_id < qdev->num_rx_queues) {
768 fp = &qdev->fp_array[rx_queue_id];
770 /* Allocate buffers for the Rx ring */
771 for (j = 0; j < rxq->nb_rx_desc; j++) {
772 rc = qede_alloc_rx_buffer(rxq);
774 DP_ERR(edev, "RX buffer allocation failed"
775 " for rxq = %u\n", rx_queue_id);
779 /* disable interrupts */
780 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
782 memset(¶ms, 0, sizeof(params));
783 params.queue_id = rx_queue_id / edev->num_hwfns;
785 params.stats_id = params.vport_id;
786 params.p_sb = fp->sb_info;
787 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
788 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
789 params.sb_idx = RX_PI;
790 hwfn_index = rx_queue_id % edev->num_hwfns;
791 p_hwfn = &edev->hwfns[hwfn_index];
792 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
793 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
794 memset(&ret_params, 0, sizeof(ret_params));
795 rc = ecore_eth_rx_queue_start(p_hwfn,
796 p_hwfn->hw_info.opaque_fid,
797 ¶ms, fp->rxq->rx_buf_size,
798 fp->rxq->rx_bd_ring.p_phys_addr,
799 p_phys_table, page_cnt,
802 DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
806 /* Update with the returned parameters */
807 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
808 fp->rxq->handle = ret_params.p_handle;
810 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_pi_array[RX_PI];
811 qede_update_rx_prod(qdev, fp->rxq);
812 eth_dev->data->rx_queue_state[rx_queue_id] =
813 RTE_ETH_QUEUE_STATE_STARTED;
814 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
816 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
824 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
826 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
827 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
828 struct ecore_queue_start_common_params params;
829 struct ecore_txq_start_ret_params ret_params;
830 struct ecore_hwfn *p_hwfn;
831 dma_addr_t p_phys_table;
832 struct qede_tx_queue *txq;
833 struct qede_fastpath *fp;
838 if (tx_queue_id < qdev->num_tx_queues) {
839 fp = &qdev->fp_array[tx_queue_id];
841 memset(¶ms, 0, sizeof(params));
842 params.queue_id = tx_queue_id / edev->num_hwfns;
844 params.stats_id = params.vport_id;
845 params.p_sb = fp->sb_info;
846 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
847 fp->txq->queue_id, fp->sb_info->igu_sb_id);
848 params.sb_idx = TX_PI(0); /* tc = 0 */
849 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
850 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
851 hwfn_index = tx_queue_id % edev->num_hwfns;
852 p_hwfn = &edev->hwfns[hwfn_index];
853 if (qdev->dev_info.is_legacy)
854 fp->txq->is_legacy = true;
855 rc = ecore_eth_tx_queue_start(p_hwfn,
856 p_hwfn->hw_info.opaque_fid,
858 p_phys_table, page_cnt,
860 if (rc != ECORE_SUCCESS) {
861 DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
865 txq->doorbell_addr = ret_params.p_doorbell;
866 txq->handle = ret_params.p_handle;
868 txq->hw_cons_ptr = &fp->sb_info->sb_pi_array[TX_PI(0)];
869 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
871 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
873 SET_FIELD(txq->tx_db.data.params,
874 ETH_DB_DATA_AGG_VAL_SEL,
875 DQ_XCM_ETH_TX_BD_PROD_CMD);
876 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
877 eth_dev->data->tx_queue_state[tx_queue_id] =
878 RTE_ETH_QUEUE_STATE_STARTED;
879 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
881 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
889 qede_free_tx_pkt(struct qede_tx_queue *txq)
891 struct rte_mbuf *mbuf;
896 mbuf = txq->sw_tx_ring[idx].mbuf;
898 nb_segs = mbuf->nb_segs;
899 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
901 /* It's like consuming rxbuf in recv() */
902 ecore_chain_consume(&txq->tx_pbl);
906 rte_pktmbuf_free(mbuf);
907 txq->sw_tx_ring[idx].mbuf = NULL;
909 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
911 ecore_chain_consume(&txq->tx_pbl);
917 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
918 struct qede_tx_queue *txq)
921 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
925 rte_compiler_barrier();
926 hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
927 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
928 sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
929 PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
930 abs(hw_bd_cons - sw_tx_cons));
932 while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl))
933 qede_free_tx_pkt(txq);
936 static int qede_drain_txq(struct qede_dev *qdev,
937 struct qede_tx_queue *txq, bool allow_drain)
939 struct ecore_dev *edev = &qdev->edev;
942 while (txq->sw_tx_cons != txq->sw_tx_prod) {
943 qede_process_tx_compl(edev, txq);
946 DP_ERR(edev, "Tx queue[%u] is stuck,"
947 "requesting MCP to drain\n",
949 rc = qdev->ops->common->drain(edev);
952 return qede_drain_txq(qdev, txq, false);
954 DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
955 "PROD=%d, CONS=%d\n",
956 txq->queue_id, txq->sw_tx_prod,
962 rte_compiler_barrier();
965 /* FW finished processing, wait for HW to transmit all tx packets */
971 /* Stops a given TX queue in the HW */
972 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
974 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
975 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
976 struct ecore_hwfn *p_hwfn;
977 struct qede_tx_queue *txq;
981 if (tx_queue_id < qdev->num_tx_queues) {
982 txq = qdev->fp_array[tx_queue_id].txq;
984 if (qede_drain_txq(qdev, txq, true))
985 return -1; /* For the lack of retcodes */
987 hwfn_index = tx_queue_id % edev->num_hwfns;
988 p_hwfn = &edev->hwfns[hwfn_index];
989 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
990 if (rc != ECORE_SUCCESS) {
991 DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
994 qede_tx_queue_release_mbufs(txq);
995 qede_tx_queue_reset(qdev, txq);
996 eth_dev->data->tx_queue_state[tx_queue_id] =
997 RTE_ETH_QUEUE_STATE_STOPPED;
998 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
1000 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
1007 int qede_start_queues(struct rte_eth_dev *eth_dev)
1009 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1013 for (id = 0; id < qdev->num_rx_queues; id++) {
1014 rc = qede_rx_queue_start(eth_dev, id);
1015 if (rc != ECORE_SUCCESS)
1019 for (id = 0; id < qdev->num_tx_queues; id++) {
1020 rc = qede_tx_queue_start(eth_dev, id);
1021 if (rc != ECORE_SUCCESS)
1028 void qede_stop_queues(struct rte_eth_dev *eth_dev)
1030 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1033 /* Stopping RX/TX queues */
1034 for (id = 0; id < qdev->num_tx_queues; id++)
1035 qede_tx_queue_stop(eth_dev, id);
1037 for (id = 0; id < qdev->num_rx_queues; id++)
1038 qede_rx_queue_stop(eth_dev, id);
1041 static inline bool qede_tunn_exist(uint16_t flag)
1043 return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1044 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
1047 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
1049 return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1050 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
1054 * qede_check_tunn_csum_l4:
1056 * 1 : If L4 csum is enabled AND if the validation has failed.
1059 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
1061 if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1062 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
1063 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1064 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
1069 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
1071 if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1072 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
1073 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1074 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
1079 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
1080 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
1082 uint32_t packet_type = RTE_PTYPE_UNKNOWN;
1083 struct rte_ether_hdr *eth_hdr;
1084 struct rte_ipv4_hdr *ipv4_hdr;
1085 struct rte_ipv6_hdr *ipv6_hdr;
1086 struct rte_vlan_hdr *vlan_hdr;
1088 bool vlan_tagged = 0;
1091 eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
1092 len = sizeof(struct rte_ether_hdr);
1093 ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
1095 /* Note: Valid only if VLAN stripping is disabled */
1096 if (ethertype == RTE_ETHER_TYPE_VLAN) {
1098 vlan_hdr = (struct rte_vlan_hdr *)(eth_hdr + 1);
1099 len += sizeof(struct rte_vlan_hdr);
1100 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
1103 if (ethertype == RTE_ETHER_TYPE_IPV4) {
1104 packet_type |= RTE_PTYPE_L3_IPV4;
1105 ipv4_hdr = rte_pktmbuf_mtod_offset(m,
1106 struct rte_ipv4_hdr *, len);
1107 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
1108 packet_type |= RTE_PTYPE_L4_TCP;
1109 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
1110 packet_type |= RTE_PTYPE_L4_UDP;
1111 } else if (ethertype == RTE_ETHER_TYPE_IPV6) {
1112 packet_type |= RTE_PTYPE_L3_IPV6;
1113 ipv6_hdr = rte_pktmbuf_mtod_offset(m,
1114 struct rte_ipv6_hdr *, len);
1115 if (ipv6_hdr->proto == IPPROTO_TCP)
1116 packet_type |= RTE_PTYPE_L4_TCP;
1117 else if (ipv6_hdr->proto == IPPROTO_UDP)
1118 packet_type |= RTE_PTYPE_L4_UDP;
1122 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
1124 packet_type |= RTE_PTYPE_L2_ETHER;
1129 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
1134 static const uint32_t
1135 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1136 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4 |
1137 RTE_PTYPE_INNER_L2_ETHER,
1138 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6 |
1139 RTE_PTYPE_INNER_L2_ETHER,
1140 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4 |
1141 RTE_PTYPE_INNER_L4_TCP |
1142 RTE_PTYPE_INNER_L2_ETHER,
1143 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6 |
1144 RTE_PTYPE_INNER_L4_TCP |
1145 RTE_PTYPE_INNER_L2_ETHER,
1146 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4 |
1147 RTE_PTYPE_INNER_L4_UDP |
1148 RTE_PTYPE_INNER_L2_ETHER,
1149 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6 |
1150 RTE_PTYPE_INNER_L4_UDP |
1151 RTE_PTYPE_INNER_L2_ETHER,
1152 /* Frags with no VLAN */
1153 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1154 RTE_PTYPE_INNER_L4_FRAG |
1155 RTE_PTYPE_INNER_L2_ETHER,
1156 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1157 RTE_PTYPE_INNER_L4_FRAG |
1158 RTE_PTYPE_INNER_L2_ETHER,
1160 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1161 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1162 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1163 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1164 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1165 RTE_PTYPE_INNER_L4_TCP |
1166 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1167 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1168 RTE_PTYPE_INNER_L4_TCP |
1169 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1170 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
1171 RTE_PTYPE_INNER_L4_UDP |
1172 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1173 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
1174 RTE_PTYPE_INNER_L4_UDP |
1175 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1176 /* Frags with VLAN */
1177 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
1178 RTE_PTYPE_INNER_L4_FRAG |
1179 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1180 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
1181 RTE_PTYPE_INNER_L4_FRAG |
1182 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1185 /* Bits (0..3) provides L3/L4 protocol type */
1186 /* Bits (4,5) provides frag and VLAN info */
1187 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1188 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1189 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1190 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1191 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1192 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1193 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1194 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1196 if (val < QEDE_PKT_TYPE_MAX)
1197 return ptype_lkup_tbl[val];
1199 return RTE_PTYPE_UNKNOWN;
1202 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
1207 static const uint32_t
1208 ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
1209 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
1210 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
1211 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 |
1214 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 |
1217 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 |
1220 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 |
1223 /* Frags with no VLAN */
1224 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4 |
1227 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6 |
1231 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4 |
1232 RTE_PTYPE_L2_ETHER_VLAN,
1233 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6 |
1234 RTE_PTYPE_L2_ETHER_VLAN,
1235 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4 |
1237 RTE_PTYPE_L2_ETHER_VLAN,
1238 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6 |
1240 RTE_PTYPE_L2_ETHER_VLAN,
1241 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4 |
1243 RTE_PTYPE_L2_ETHER_VLAN,
1244 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6 |
1246 RTE_PTYPE_L2_ETHER_VLAN,
1247 /* Frags with VLAN */
1248 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4 |
1250 RTE_PTYPE_L2_ETHER_VLAN,
1251 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6 |
1253 RTE_PTYPE_L2_ETHER_VLAN,
1256 /* Bits (0..3) provides L3/L4 protocol type */
1257 /* Bits (4,5) provides frag and VLAN info */
1258 val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1259 PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1260 (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1261 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1262 (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1263 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1264 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1265 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1267 if (val < QEDE_PKT_TYPE_MAX)
1268 return ptype_lkup_tbl[val];
1270 return RTE_PTYPE_UNKNOWN;
1273 static inline uint8_t
1274 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1276 struct rte_ipv4_hdr *ip;
1281 val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1282 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1284 if (unlikely(val)) {
1285 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1286 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1287 ip = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
1288 sizeof(struct rte_ether_hdr));
1289 pkt_csum = ip->hdr_checksum;
1290 ip->hdr_checksum = 0;
1291 calc_csum = rte_ipv4_cksum(ip);
1292 ip->hdr_checksum = pkt_csum;
1293 return (calc_csum != pkt_csum);
1294 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1301 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1303 ecore_chain_consume(&rxq->rx_bd_ring);
1308 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1309 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1311 struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1312 uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
1313 struct qede_rx_entry *curr_prod;
1314 dma_addr_t new_mapping;
1316 curr_prod = &rxq->sw_rx_ring[idx];
1317 *curr_prod = *curr_cons;
1319 new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1320 curr_prod->page_offset;
1322 rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1323 rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1329 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1330 struct qede_dev *qdev, uint8_t count)
1332 struct qede_rx_entry *curr_cons;
1334 for (; count > 0; count--) {
1335 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1336 qede_reuse_page(qdev, rxq, curr_cons);
1337 qede_rx_bd_ring_consume(rxq);
1342 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1343 struct qede_rx_queue *rxq,
1344 uint8_t agg_index, uint16_t len)
1346 struct qede_agg_info *tpa_info;
1347 struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1350 /* Under certain conditions it is possible that FW may not consume
1351 * additional or new BD. So decision to consume the BD must be made
1352 * based on len_list[0].
1354 if (rte_le_to_cpu_16(len)) {
1355 tpa_info = &rxq->tpa_info[agg_index];
1356 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1357 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1359 curr_frag->nb_segs = 1;
1360 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1361 curr_frag->data_len = curr_frag->pkt_len;
1362 tpa_info->tpa_tail->next = curr_frag;
1363 tpa_info->tpa_tail = curr_frag;
1364 qede_rx_bd_ring_consume(rxq);
1365 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1366 PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1367 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1368 rxq->rx_alloc_errors++;
1374 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1375 struct qede_rx_queue *rxq,
1376 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1378 PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1379 cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1380 /* only len_list[0] will have value */
1381 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1386 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1387 struct qede_rx_queue *rxq,
1388 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1390 struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1392 qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1394 /* Update total length and frags based on end TPA */
1395 rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1396 /* TODO: Add Sanity Checks */
1397 rx_mb->nb_segs = cqe->num_of_bds;
1398 rx_mb->pkt_len = cqe->total_packet_len;
1400 PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1401 " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1402 rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1406 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1411 static const uint32_t
1412 ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1413 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1414 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1415 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1416 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1417 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1418 RTE_PTYPE_TUNNEL_GENEVE,
1419 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1420 RTE_PTYPE_TUNNEL_GRE,
1421 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1422 RTE_PTYPE_TUNNEL_VXLAN,
1423 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1424 RTE_PTYPE_TUNNEL_GENEVE,
1425 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1426 RTE_PTYPE_TUNNEL_GRE,
1427 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1428 RTE_PTYPE_TUNNEL_VXLAN,
1429 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1430 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1431 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1432 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1433 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1434 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1435 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1436 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1437 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1438 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1439 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1440 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1441 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1442 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1443 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1444 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1445 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1446 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1447 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1448 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1449 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1450 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1451 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1452 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1455 /* Cover bits[4-0] to include tunn_type and next protocol */
1456 val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1457 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1458 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1459 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1461 if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1462 return ptype_tunn_lkup_tbl[val];
1464 return RTE_PTYPE_UNKNOWN;
1468 qede_process_sg_pkts(void *p_rxq, struct rte_mbuf *rx_mb,
1469 uint8_t num_segs, uint16_t pkt_len)
1471 struct qede_rx_queue *rxq = p_rxq;
1472 struct qede_dev *qdev = rxq->qdev;
1473 register struct rte_mbuf *seg1 = NULL;
1474 register struct rte_mbuf *seg2 = NULL;
1475 uint16_t sw_rx_index;
1480 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1482 if (unlikely(!cur_size)) {
1483 PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1484 " left for mapping jumbo\n", num_segs);
1485 qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1488 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1489 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1490 qede_rx_bd_ring_consume(rxq);
1491 pkt_len -= cur_size;
1492 seg2->data_len = cur_size;
1502 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1504 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1507 PMD_RX_LOG(INFO, rxq,
1508 "len 0x%04x bf 0x%04x hash_val 0x%x"
1509 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1510 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1511 m->data_len, bitfield, m->hash.rss,
1512 (unsigned long)m->ol_flags,
1513 rte_get_ptype_l2_name(m->packet_type),
1514 rte_get_ptype_l3_name(m->packet_type),
1515 rte_get_ptype_l4_name(m->packet_type),
1516 rte_get_ptype_tunnel_name(m->packet_type),
1517 rte_get_ptype_inner_l2_name(m->packet_type),
1518 rte_get_ptype_inner_l3_name(m->packet_type),
1519 rte_get_ptype_inner_l4_name(m->packet_type));
1524 qede_recv_pkts_regular(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1526 struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1527 register struct rte_mbuf *rx_mb = NULL;
1528 struct qede_rx_queue *rxq = p_rxq;
1529 struct qede_dev *qdev = rxq->qdev;
1530 struct ecore_dev *edev = &qdev->edev;
1531 union eth_rx_cqe *cqe;
1533 enum eth_rx_cqe_type cqe_type;
1534 int rss_enable = qdev->rss_enable;
1535 int rx_alloc_count = 0;
1536 uint32_t packet_type;
1538 uint16_t vlan_tci, port_id;
1539 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index, num_rx_bds;
1540 uint16_t rx_pkt = 0;
1541 uint16_t pkt_len = 0;
1542 uint16_t len; /* Length of first BD */
1543 uint16_t preload_idx;
1544 uint16_t parse_flag;
1545 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1546 uint8_t bitfield_val;
1548 uint8_t offset, flags, bd_num;
1551 /* Allocate buffers that we used in previous loop */
1552 if (rxq->rx_alloc_count) {
1553 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1554 rxq->rx_alloc_count))) {
1555 struct rte_eth_dev *dev;
1557 PMD_RX_LOG(ERR, rxq,
1558 "New buffer allocation failed,"
1559 "dropping incoming packetn");
1560 dev = &rte_eth_devices[rxq->port_id];
1561 dev->data->rx_mbuf_alloc_failed +=
1562 rxq->rx_alloc_count;
1563 rxq->rx_alloc_errors += rxq->rx_alloc_count;
1566 qede_update_rx_prod(qdev, rxq);
1567 rxq->rx_alloc_count = 0;
1570 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1571 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1575 if (hw_comp_cons == sw_comp_cons)
1578 num_rx_bds = NUM_RX_BDS(rxq);
1579 port_id = rxq->port_id;
1581 while (sw_comp_cons != hw_comp_cons) {
1583 packet_type = RTE_PTYPE_UNKNOWN;
1587 /* Get the CQE from the completion ring */
1589 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1590 cqe_type = cqe->fast_path_regular.type;
1591 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1593 if (likely(cqe_type == ETH_RX_CQE_TYPE_REGULAR)) {
1594 fp_cqe = &cqe->fast_path_regular;
1596 if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
1597 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1598 ecore_eth_cqe_completion
1599 (&edev->hwfns[rxq->queue_id %
1601 (struct eth_slow_path_rx_cqe *)cqe);
1606 /* Get the data from the SW ring */
1607 sw_rx_index = rxq->sw_rx_cons & num_rx_bds;
1608 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1609 assert(rx_mb != NULL);
1611 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1612 offset = fp_cqe->placement_offset;
1613 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1614 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1615 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1616 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1617 bd_num = fp_cqe->bd_num;
1618 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1619 bitfield_val = fp_cqe->bitfields;
1622 if (unlikely(qede_tunn_exist(parse_flag))) {
1623 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1624 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1625 PMD_RX_LOG(ERR, rxq,
1626 "L4 csum failed, flags = 0x%x\n",
1628 rxq->rx_hw_errors++;
1629 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1631 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1634 if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1635 PMD_RX_LOG(ERR, rxq,
1636 "Outer L3 csum failed, flags = 0x%x\n",
1638 rxq->rx_hw_errors++;
1639 ol_flags |= PKT_RX_EIP_CKSUM_BAD;
1641 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1644 flags = fp_cqe->tunnel_pars_flags.flags;
1648 qede_rx_cqe_to_tunn_pkt_type(flags);
1652 qede_rx_cqe_to_pkt_type_inner(parse_flag);
1654 /* Outer L3/L4 types is not available in CQE */
1655 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1657 /* Outer L3/L4 types is not available in CQE.
1658 * Need to add offset to parse correctly,
1660 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1661 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1663 packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1666 /* Common handling for non-tunnel packets and for inner
1667 * headers in the case of tunnel.
1669 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1670 PMD_RX_LOG(ERR, rxq,
1671 "L4 csum failed, flags = 0x%x\n",
1673 rxq->rx_hw_errors++;
1674 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1676 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1678 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1679 PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1681 rxq->rx_hw_errors++;
1682 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1684 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1687 if (unlikely(CQE_HAS_VLAN(parse_flag) ||
1688 CQE_HAS_OUTER_VLAN(parse_flag))) {
1689 /* Note: FW doesn't indicate Q-in-Q packet */
1690 ol_flags |= PKT_RX_VLAN;
1691 if (qdev->vlan_strip_flg) {
1692 ol_flags |= PKT_RX_VLAN_STRIPPED;
1693 rx_mb->vlan_tci = vlan_tci;
1698 ol_flags |= PKT_RX_RSS_HASH;
1699 rx_mb->hash.rss = rss_hash;
1703 qede_rx_bd_ring_consume(rxq);
1705 /* Prefetch next mbuf while processing current one. */
1706 preload_idx = rxq->sw_rx_cons & num_rx_bds;
1707 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1709 /* Update rest of the MBUF fields */
1710 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1711 rx_mb->port = port_id;
1712 rx_mb->ol_flags = ol_flags;
1713 rx_mb->data_len = len;
1714 rx_mb->packet_type = packet_type;
1715 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1716 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1718 rx_mb->nb_segs = bd_num;
1719 rx_mb->pkt_len = pkt_len;
1721 rx_pkts[rx_pkt] = rx_mb;
1725 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1726 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1727 if (rx_pkt == nb_pkts) {
1728 PMD_RX_LOG(DEBUG, rxq,
1729 "Budget reached nb_pkts=%u received=%u",
1735 /* Request number of bufferes to be allocated in next loop */
1736 rxq->rx_alloc_count = rx_alloc_count;
1738 rxq->rcv_pkts += rx_pkt;
1739 rxq->rx_segs += rx_pkt;
1740 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1746 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1748 struct qede_rx_queue *rxq = p_rxq;
1749 struct qede_dev *qdev = rxq->qdev;
1750 struct ecore_dev *edev = &qdev->edev;
1751 uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1752 uint16_t rx_pkt = 0;
1753 union eth_rx_cqe *cqe;
1754 struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1755 register struct rte_mbuf *rx_mb = NULL;
1756 register struct rte_mbuf *seg1 = NULL;
1757 enum eth_rx_cqe_type cqe_type;
1758 uint16_t pkt_len = 0; /* Sum of all BD segments */
1759 uint16_t len; /* Length of first BD */
1760 uint8_t num_segs = 1;
1761 uint16_t preload_idx;
1762 uint16_t parse_flag;
1763 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1764 uint8_t bitfield_val;
1766 uint8_t tunn_parse_flag;
1767 struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1769 uint32_t packet_type;
1772 uint8_t offset, tpa_agg_idx, flags;
1773 struct qede_agg_info *tpa_info = NULL;
1775 int rx_alloc_count = 0;
1778 /* Allocate buffers that we used in previous loop */
1779 if (rxq->rx_alloc_count) {
1780 if (unlikely(qede_alloc_rx_bulk_mbufs(rxq,
1781 rxq->rx_alloc_count))) {
1782 struct rte_eth_dev *dev;
1784 PMD_RX_LOG(ERR, rxq,
1785 "New buffer allocation failed,"
1786 "dropping incoming packetn");
1787 dev = &rte_eth_devices[rxq->port_id];
1788 dev->data->rx_mbuf_alloc_failed +=
1789 rxq->rx_alloc_count;
1790 rxq->rx_alloc_errors += rxq->rx_alloc_count;
1793 qede_update_rx_prod(qdev, rxq);
1794 rxq->rx_alloc_count = 0;
1797 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1798 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1802 if (hw_comp_cons == sw_comp_cons)
1805 while (sw_comp_cons != hw_comp_cons) {
1807 packet_type = RTE_PTYPE_UNKNOWN;
1809 tpa_start_flg = false;
1812 /* Get the CQE from the completion ring */
1814 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1815 cqe_type = cqe->fast_path_regular.type;
1816 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1819 case ETH_RX_CQE_TYPE_REGULAR:
1820 fp_cqe = &cqe->fast_path_regular;
1822 case ETH_RX_CQE_TYPE_TPA_START:
1823 cqe_start_tpa = &cqe->fast_path_tpa_start;
1824 tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1825 tpa_start_flg = true;
1826 /* Mark it as LRO packet */
1827 ol_flags |= PKT_RX_LRO;
1828 /* In split mode, seg_len is same as len_on_first_bd
1829 * and bw_ext_bd_len_list will be empty since there are
1830 * no additional buffers
1832 PMD_RX_LOG(INFO, rxq,
1833 "TPA start[%d] - len_on_first_bd %d header %d"
1834 " [bd_list[0] %d], [seg_len %d]\n",
1835 cqe_start_tpa->tpa_agg_index,
1836 rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1837 cqe_start_tpa->header_len,
1838 rte_le_to_cpu_16(cqe_start_tpa->bw_ext_bd_len_list[0]),
1839 rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1842 case ETH_RX_CQE_TYPE_TPA_CONT:
1843 qede_rx_process_tpa_cont_cqe(qdev, rxq,
1844 &cqe->fast_path_tpa_cont);
1846 case ETH_RX_CQE_TYPE_TPA_END:
1847 qede_rx_process_tpa_end_cqe(qdev, rxq,
1848 &cqe->fast_path_tpa_end);
1849 tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1850 tpa_info = &rxq->tpa_info[tpa_agg_idx];
1851 rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1853 case ETH_RX_CQE_TYPE_SLOW_PATH:
1854 PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1855 ecore_eth_cqe_completion(
1856 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1857 (struct eth_slow_path_rx_cqe *)cqe);
1863 /* Get the data from the SW ring */
1864 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1865 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1866 assert(rx_mb != NULL);
1868 /* Handle regular CQE or TPA start CQE */
1869 if (!tpa_start_flg) {
1870 parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1871 offset = fp_cqe->placement_offset;
1872 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1873 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1874 vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1875 rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1876 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1877 bitfield_val = fp_cqe->bitfields;
1881 rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1882 offset = cqe_start_tpa->placement_offset;
1883 /* seg_len = len_on_first_bd */
1884 len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1885 vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1886 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1887 bitfield_val = cqe_start_tpa->bitfields;
1889 rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1891 if (qede_tunn_exist(parse_flag)) {
1892 PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1893 if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1894 PMD_RX_LOG(ERR, rxq,
1895 "L4 csum failed, flags = 0x%x\n",
1897 rxq->rx_hw_errors++;
1898 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1900 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1903 if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1904 PMD_RX_LOG(ERR, rxq,
1905 "Outer L3 csum failed, flags = 0x%x\n",
1907 rxq->rx_hw_errors++;
1908 ol_flags |= PKT_RX_EIP_CKSUM_BAD;
1910 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1914 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1916 flags = fp_cqe->tunnel_pars_flags.flags;
1917 tunn_parse_flag = flags;
1921 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1925 qede_rx_cqe_to_pkt_type_inner(parse_flag);
1927 /* Outer L3/L4 types is not available in CQE */
1928 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1930 /* Outer L3/L4 types is not available in CQE.
1931 * Need to add offset to parse correctly,
1933 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1934 packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1936 packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1939 /* Common handling for non-tunnel packets and for inner
1940 * headers in the case of tunnel.
1942 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1943 PMD_RX_LOG(ERR, rxq,
1944 "L4 csum failed, flags = 0x%x\n",
1946 rxq->rx_hw_errors++;
1947 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1949 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1951 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1952 PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1954 rxq->rx_hw_errors++;
1955 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1957 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1960 if (CQE_HAS_VLAN(parse_flag) ||
1961 CQE_HAS_OUTER_VLAN(parse_flag)) {
1962 /* Note: FW doesn't indicate Q-in-Q packet */
1963 ol_flags |= PKT_RX_VLAN;
1964 if (qdev->vlan_strip_flg) {
1965 ol_flags |= PKT_RX_VLAN_STRIPPED;
1966 rx_mb->vlan_tci = vlan_tci;
1971 if (qdev->rss_enable) {
1972 ol_flags |= PKT_RX_RSS_HASH;
1973 rx_mb->hash.rss = rss_hash;
1977 qede_rx_bd_ring_consume(rxq);
1979 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1980 PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1981 " len on first: %04x Total Len: %04x",
1982 fp_cqe->bd_num, len, pkt_len);
1983 num_segs = fp_cqe->bd_num - 1;
1985 if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1989 rx_alloc_count += num_segs;
1990 rxq->rx_segs += num_segs;
1992 rxq->rx_segs++; /* for the first segment */
1994 /* Prefetch next mbuf while processing current one. */
1995 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1996 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1998 /* Update rest of the MBUF fields */
1999 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
2000 rx_mb->port = rxq->port_id;
2001 rx_mb->ol_flags = ol_flags;
2002 rx_mb->data_len = len;
2003 rx_mb->packet_type = packet_type;
2004 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
2005 print_rx_bd_info(rx_mb, rxq, bitfield_val);
2007 if (!tpa_start_flg) {
2008 rx_mb->nb_segs = fp_cqe->bd_num;
2009 rx_mb->pkt_len = pkt_len;
2011 /* store ref to the updated mbuf */
2012 tpa_info->tpa_head = rx_mb;
2013 tpa_info->tpa_tail = tpa_info->tpa_head;
2015 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
2017 if (!tpa_start_flg) {
2018 rx_pkts[rx_pkt] = rx_mb;
2022 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
2023 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2024 if (rx_pkt == nb_pkts) {
2025 PMD_RX_LOG(DEBUG, rxq,
2026 "Budget reached nb_pkts=%u received=%u",
2032 /* Request number of bufferes to be allocated in next loop */
2033 rxq->rx_alloc_count = rx_alloc_count;
2035 rxq->rcv_pkts += rx_pkt;
2037 PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
2043 qede_recv_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2045 struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2046 uint16_t eng0_pkts, eng1_pkts;
2048 eng0_pkts = nb_pkts / 2;
2050 eng0_pkts = qede_recv_pkts(fp_cmt->fp0->rxq, rx_pkts, eng0_pkts);
2052 eng1_pkts = nb_pkts - eng0_pkts;
2054 eng1_pkts = qede_recv_pkts(fp_cmt->fp1->rxq, rx_pkts + eng0_pkts,
2057 return eng0_pkts + eng1_pkts;
2060 /* Populate scatter gather buffer descriptor fields */
2061 static inline uint16_t
2062 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
2063 struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
2066 struct qede_tx_queue *txq = p_txq;
2067 struct eth_tx_bd *tx_bd = NULL;
2069 uint16_t nb_segs = 0;
2071 /* Check for scattered buffers */
2073 if (start_seg == 0) {
2075 *bd2 = (struct eth_tx_2nd_bd *)
2076 ecore_chain_produce(&txq->tx_pbl);
2077 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
2080 mapping = rte_mbuf_data_iova(m_seg);
2081 QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
2082 PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
2083 } else if (start_seg == 1) {
2085 *bd3 = (struct eth_tx_3rd_bd *)
2086 ecore_chain_produce(&txq->tx_pbl);
2087 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
2090 mapping = rte_mbuf_data_iova(m_seg);
2091 QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
2092 PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
2094 tx_bd = (struct eth_tx_bd *)
2095 ecore_chain_produce(&txq->tx_pbl);
2096 memset(tx_bd, 0, sizeof(*tx_bd));
2098 mapping = rte_mbuf_data_iova(m_seg);
2099 QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
2100 PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
2103 m_seg = m_seg->next;
2106 /* Return total scattered buffers */
2110 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2112 print_tx_bd_info(struct qede_tx_queue *txq,
2113 struct eth_tx_1st_bd *bd1,
2114 struct eth_tx_2nd_bd *bd2,
2115 struct eth_tx_3rd_bd *bd3,
2116 uint64_t tx_ol_flags)
2118 char ol_buf[256] = { 0 }; /* for verbose prints */
2121 PMD_TX_LOG(INFO, txq,
2122 "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
2123 rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
2124 bd1->data.bd_flags.bitfields,
2125 rte_cpu_to_le_16(bd1->data.bitfields));
2127 PMD_TX_LOG(INFO, txq,
2128 "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
2129 rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
2130 bd2->data.bitfields2, bd2->data.tunn_ip_size);
2132 PMD_TX_LOG(INFO, txq,
2133 "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
2134 "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
2135 rte_cpu_to_le_16(bd3->nbytes),
2136 rte_cpu_to_le_16(bd3->data.bitfields),
2137 rte_cpu_to_le_16(bd3->data.lso_mss),
2138 bd3->data.tunn_l4_hdr_start_offset_w,
2139 bd3->data.tunn_hdr_size_w);
2141 rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
2142 PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
2146 /* TX prepare to check packets meets TX conditions */
2148 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2149 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
2152 struct qede_tx_queue *txq = p_txq;
2154 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
2161 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2165 for (i = 0; i < nb_pkts; i++) {
2167 ol_flags = m->ol_flags;
2168 if (ol_flags & PKT_TX_TCP_SEG) {
2169 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
2173 /* TBD: confirm its ~9700B for both ? */
2174 if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
2179 if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
2184 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
2185 /* We support only limited tunnel protocols */
2186 if (ol_flags & PKT_TX_TUNNEL_MASK) {
2189 temp = ol_flags & PKT_TX_TUNNEL_MASK;
2190 if (temp == PKT_TX_TUNNEL_VXLAN ||
2191 temp == PKT_TX_TUNNEL_GENEVE ||
2192 temp == PKT_TX_TUNNEL_MPLSINUDP ||
2193 temp == PKT_TX_TUNNEL_GRE)
2197 rte_errno = ENOTSUP;
2201 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2202 ret = rte_validate_tx_offload(m);
2210 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2211 if (unlikely(i != nb_pkts))
2212 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
2218 #define MPLSINUDP_HDR_SIZE (12)
2220 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2222 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
2223 struct qede_tx_queue *txq)
2225 if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
2226 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
2227 if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
2228 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
2229 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
2230 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
2231 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
2232 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2233 if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
2234 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
2235 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
2240 qede_xmit_pkts_regular(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2242 struct qede_tx_queue *txq = p_txq;
2243 struct qede_dev *qdev = txq->qdev;
2244 struct ecore_dev *edev = &qdev->edev;
2245 struct eth_tx_1st_bd *bd1;
2246 struct eth_tx_2nd_bd *bd2;
2247 struct eth_tx_3rd_bd *bd3;
2248 struct rte_mbuf *m_seg = NULL;
2249 struct rte_mbuf *mbuf;
2250 struct qede_tx_entry *sw_tx_ring;
2251 uint16_t nb_tx_pkts;
2254 uint16_t nb_frags = 0;
2255 uint16_t nb_pkt_sent = 0;
2257 uint64_t tx_ol_flags;
2260 uint8_t bd1_bd_flags_bf;
2262 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2263 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2264 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2265 qede_process_tx_compl(edev, txq);
2268 nb_tx_pkts = nb_pkts;
2269 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2270 sw_tx_ring = txq->sw_tx_ring;
2272 while (nb_tx_pkts--) {
2273 /* Init flags/values */
2279 bd1_bd_flags_bf = 0;
2286 /* Check minimum TX BDS availability against available BDs */
2287 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2290 tx_ol_flags = mbuf->ol_flags;
2291 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2293 if (unlikely(txq->nb_tx_avail <
2294 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2297 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2298 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2300 /* Offload the IP checksum in the hardware */
2301 if (tx_ol_flags & PKT_TX_IP_CKSUM)
2303 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2305 /* L4 checksum offload (tcp or udp) */
2306 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2307 (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM)))
2309 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2311 /* Fill the entry in the SW ring and the BDs in the FW ring */
2313 sw_tx_ring[idx].mbuf = mbuf;
2316 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2317 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2320 /* Map MBUF linear data for DMA and set in the BD1 */
2321 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2323 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2324 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2326 /* Handle fragmented MBUF */
2327 if (unlikely(mbuf->nb_segs > 1)) {
2330 /* Encode scatter gather buffer descriptors */
2331 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3,
2335 bd1->data.nbds = nbds + nb_frags;
2337 txq->nb_tx_avail -= bd1->data.nbds;
2340 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2341 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2342 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2348 /* Write value of prod idx into bd_prod */
2349 txq->tx_db.data.bd_prod = bd_prod;
2351 rte_compiler_barrier();
2352 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2355 /* Check again for Tx completions */
2356 qede_process_tx_compl(edev, txq);
2358 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2359 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2365 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2367 struct qede_tx_queue *txq = p_txq;
2368 struct qede_dev *qdev = txq->qdev;
2369 struct ecore_dev *edev = &qdev->edev;
2370 struct rte_mbuf *mbuf;
2371 struct rte_mbuf *m_seg = NULL;
2372 uint16_t nb_tx_pkts;
2376 uint16_t nb_pkt_sent = 0;
2380 __rte_unused bool tunn_flg;
2381 bool tunn_ipv6_ext_flg;
2382 struct eth_tx_1st_bd *bd1;
2383 struct eth_tx_2nd_bd *bd2;
2384 struct eth_tx_3rd_bd *bd3;
2385 uint64_t tx_ol_flags;
2389 uint8_t bd1_bd_flags_bf;
2398 uint8_t tunn_l4_hdr_start_offset;
2399 uint8_t tunn_hdr_size;
2400 uint8_t inner_l2_hdr_size;
2401 uint16_t inner_l4_hdr_offset;
2403 if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
2404 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
2405 nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
2406 qede_process_tx_compl(edev, txq);
2409 nb_tx_pkts = nb_pkts;
2410 bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2411 while (nb_tx_pkts--) {
2412 /* Init flags/values */
2422 bd1_bd_flags_bf = 0;
2427 mplsoudp_flg = false;
2428 tunn_ipv6_ext_flg = false;
2430 tunn_l4_hdr_start_offset = 0;
2435 /* Check minimum TX BDS availability against available BDs */
2436 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
2439 tx_ol_flags = mbuf->ol_flags;
2440 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
2442 /* TX prepare would have already checked supported tunnel Tx
2443 * offloads. Don't rely on pkt_type marked by Rx, instead use
2444 * tx_ol_flags to decide.
2446 tunn_flg = !!(tx_ol_flags & PKT_TX_TUNNEL_MASK);
2449 /* Check against max which is Tunnel IPv6 + ext */
2450 if (unlikely(txq->nb_tx_avail <
2451 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
2454 /* First indicate its a tunnel pkt */
2455 bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
2456 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2457 /* Legacy FW had flipped behavior in regard to this bit
2458 * i.e. it needed to set to prevent FW from touching
2459 * encapsulated packets when it didn't need to.
2461 if (unlikely(txq->is_legacy)) {
2463 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
2466 /* Outer IP checksum offload */
2467 if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
2468 PKT_TX_OUTER_IPV4)) {
2470 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
2471 ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
2475 * Currently, only inner checksum offload in MPLS-in-UDP
2476 * tunnel with one MPLS label is supported. Both outer
2477 * and inner layers lengths need to be provided in
2480 if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
2481 PKT_TX_TUNNEL_MPLSINUDP) {
2482 mplsoudp_flg = true;
2483 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2484 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
2486 /* Outer L4 offset in two byte words */
2487 tunn_l4_hdr_start_offset =
2488 (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
2489 /* Tunnel header size in two byte words */
2490 tunn_hdr_size = (mbuf->outer_l2_len +
2491 mbuf->outer_l3_len +
2492 MPLSINUDP_HDR_SIZE) / 2;
2493 /* Inner L2 header size in two byte words */
2494 inner_l2_hdr_size = (mbuf->l2_len -
2495 MPLSINUDP_HDR_SIZE) / 2;
2496 /* Inner L4 header offset from the beggining
2497 * of inner packet in two byte words
2499 inner_l4_hdr_offset = (mbuf->l2_len -
2500 MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
2502 /* Inner L2 size and address type */
2503 bd2_bf1 |= (inner_l2_hdr_size &
2504 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
2505 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
2506 bd2_bf1 |= (UNICAST_ADDRESS &
2507 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
2508 ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
2509 /* Treated as IPv6+Ext */
2511 1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
2513 /* Mark inner IPv6 if present */
2514 if (tx_ol_flags & PKT_TX_IPV6)
2516 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
2518 /* Inner L4 offsets */
2519 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2520 (tx_ol_flags & (PKT_TX_UDP_CKSUM |
2521 PKT_TX_TCP_CKSUM))) {
2522 /* Determines if BD3 is needed */
2523 tunn_ipv6_ext_flg = true;
2524 if ((tx_ol_flags & PKT_TX_L4_MASK) ==
2527 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2530 /* TODO other pseudo checksum modes are
2534 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2535 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
2536 bd2_bf2 |= (inner_l4_hdr_offset &
2537 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
2538 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
2540 } /* End MPLSoUDP */
2541 } /* End Tunnel handling */
2543 if (tx_ol_flags & PKT_TX_TCP_SEG) {
2545 if (unlikely(txq->nb_tx_avail <
2546 ETH_TX_MIN_BDS_PER_LSO_PKT))
2548 /* For LSO, packet header and payload must reside on
2549 * buffers pointed by different BDs. Using BD1 for HDR
2550 * and BD2 onwards for data.
2552 hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
2554 hdr_size += mbuf->outer_l2_len +
2557 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
2559 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2560 /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
2562 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2563 mss = rte_cpu_to_le_16(mbuf->tso_segsz);
2564 /* Using one header BD */
2565 bd3_bf |= rte_cpu_to_le_16(1 <<
2566 ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
2568 if (unlikely(txq->nb_tx_avail <
2569 ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
2572 (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
2573 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2576 /* Descriptor based VLAN insertion */
2577 if (tx_ol_flags & PKT_TX_VLAN_PKT) {
2578 vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
2580 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
2583 /* Offload the IP checksum in the hardware */
2584 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
2586 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
2587 /* There's no DPDK flag to request outer-L4 csum
2588 * offload. But in the case of tunnel if inner L3 or L4
2589 * csum offload is requested then we need to force
2590 * recalculation of L4 tunnel header csum also.
2592 if (tunn_flg && ((tx_ol_flags & PKT_TX_TUNNEL_MASK) !=
2593 PKT_TX_TUNNEL_GRE)) {
2595 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2596 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2600 /* L4 checksum offload (tcp or udp) */
2601 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
2602 (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
2604 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2605 /* There's no DPDK flag to request outer-L4 csum
2606 * offload. But in the case of tunnel if inner L3 or L4
2607 * csum offload is requested then we need to force
2608 * recalculation of L4 tunnel header csum also.
2612 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2613 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2617 /* Fill the entry in the SW ring and the BDs in the FW ring */
2619 txq->sw_tx_ring[idx].mbuf = mbuf;
2622 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2623 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2626 /* Map MBUF linear data for DMA and set in the BD1 */
2627 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2629 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2630 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2631 bd1->data.vlan = vlan;
2633 if (lso_flg || mplsoudp_flg) {
2634 bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2636 memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2640 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2643 QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2644 rte_mbuf_data_iova(mbuf)),
2645 mbuf->data_len - hdr_size);
2646 bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2648 bd2->data.bitfields2 =
2649 rte_cpu_to_le_16(bd2_bf2);
2651 bd2->data.tunn_ip_size =
2652 rte_cpu_to_le_16(mbuf->outer_l3_len);
2655 if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2656 bd3 = (struct eth_tx_3rd_bd *)
2657 ecore_chain_produce(&txq->tx_pbl);
2658 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2660 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2662 bd3->data.lso_mss = mss;
2664 bd3->data.tunn_l4_hdr_start_offset_w =
2665 tunn_l4_hdr_start_offset;
2666 bd3->data.tunn_hdr_size_w =
2672 /* Handle fragmented MBUF */
2675 /* Encode scatter gather buffer descriptors if required */
2676 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2677 bd1->data.nbds = nbds + nb_frags;
2679 txq->nb_tx_avail -= bd1->data.nbds;
2682 rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2683 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2684 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2690 /* Write value of prod idx into bd_prod */
2691 txq->tx_db.data.bd_prod = bd_prod;
2693 rte_compiler_barrier();
2694 DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2697 /* Check again for Tx completions */
2698 qede_process_tx_compl(edev, txq);
2700 PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2701 nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2707 qede_xmit_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2709 struct qede_fastpath_cmt *fp_cmt = p_fp_cmt;
2710 uint16_t eng0_pkts, eng1_pkts;
2712 eng0_pkts = nb_pkts / 2;
2714 eng0_pkts = qede_xmit_pkts(fp_cmt->fp0->txq, tx_pkts, eng0_pkts);
2716 eng1_pkts = nb_pkts - eng0_pkts;
2718 eng1_pkts = qede_xmit_pkts(fp_cmt->fp1->txq, tx_pkts + eng0_pkts,
2721 return eng0_pkts + eng1_pkts;
2725 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2726 __rte_unused struct rte_mbuf **pkts,
2727 __rte_unused uint16_t nb_pkts)
2733 /* this function does a fake walk through over completion queue
2734 * to calculate number of BDs used by HW.
2735 * At the end, it restores the state of completion queue.
2738 qede_parse_fp_cqe(struct qede_rx_queue *rxq)
2740 uint16_t hw_comp_cons, sw_comp_cons, bd_count = 0;
2741 union eth_rx_cqe *cqe, *orig_cqe = NULL;
2743 hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
2744 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2746 if (hw_comp_cons == sw_comp_cons)
2749 /* Get the CQE from the completion ring */
2750 cqe = (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2753 while (sw_comp_cons != hw_comp_cons) {
2754 switch (cqe->fast_path_regular.type) {
2755 case ETH_RX_CQE_TYPE_REGULAR:
2756 bd_count += cqe->fast_path_regular.bd_num;
2758 case ETH_RX_CQE_TYPE_TPA_END:
2759 bd_count += cqe->fast_path_tpa_end.num_of_bds;
2766 (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
2767 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
2770 /* revert comp_ring to original state */
2771 ecore_chain_set_cons(&rxq->rx_comp_ring, sw_comp_cons, orig_cqe);
2777 qede_rx_descriptor_status(void *p_rxq, uint16_t offset)
2779 uint16_t hw_bd_cons, sw_bd_cons, sw_bd_prod;
2780 uint16_t produced, consumed;
2781 struct qede_rx_queue *rxq = p_rxq;
2783 if (offset > rxq->nb_rx_desc)
2786 sw_bd_cons = ecore_chain_get_cons_idx(&rxq->rx_bd_ring);
2787 sw_bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
2789 /* find BDs used by HW from completion queue elements */
2790 hw_bd_cons = sw_bd_cons + qede_parse_fp_cqe(rxq);
2792 if (hw_bd_cons < sw_bd_cons)
2793 /* wraparound case */
2794 consumed = (0xffff - sw_bd_cons) + hw_bd_cons;
2796 consumed = hw_bd_cons - sw_bd_cons;
2798 if (offset <= consumed)
2799 return RTE_ETH_RX_DESC_DONE;
2801 if (sw_bd_prod < sw_bd_cons)
2802 /* wraparound case */
2803 produced = (0xffff - sw_bd_cons) + sw_bd_prod;
2805 produced = sw_bd_prod - sw_bd_cons;
2807 if (offset <= produced)
2808 return RTE_ETH_RX_DESC_AVAIL;
2810 return RTE_ETH_RX_DESC_UNAVAIL;