1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
14 static __checkReturn efx_rc_t
20 __in uint32_t instance,
21 __in efsys_mem_t *esmp,
22 __in boolean_t disable_scatter,
23 __in boolean_t want_inner_classes,
24 __in uint32_t ps_bufsize,
25 __in uint32_t es_bufs_per_desc,
26 __in uint32_t es_max_dma_len,
27 __in uint32_t es_buf_stride,
28 __in uint32_t hol_block_timeout)
30 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
32 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V3_IN_LEN,
33 MC_CMD_INIT_RXQ_V3_OUT_LEN);
34 int npages = efx_rxq_nbufs(enp, ndescs);
36 efx_qword_t *dma_addr;
40 boolean_t want_outer_classes;
43 EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs);
46 (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) {
51 no_cont_ev = (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV);
52 if ((no_cont_ev == B_TRUE) && (disable_scatter == B_FALSE)) {
53 /* TODO: Support scatter in NO_CONT_EV mode */
59 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;
60 else if (es_bufs_per_desc > 0)
61 dma_mode = MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER;
63 dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET;
65 if (encp->enc_tunnel_encapsulations_supported != 0 &&
66 !want_inner_classes) {
68 * WANT_OUTER_CLASSES can only be specified on hardware which
69 * supports tunnel encapsulation offloads, even though it is
70 * effectively the behaviour the hardware gives.
72 * Also, on hardware which does support such offloads, older
73 * firmware rejects the flag if the offloads are not supported
74 * by the current firmware variant, which means this may fail if
75 * the capabilities are not updated when the firmware variant
76 * changes. This is not an issue on newer firmware, as it was
77 * changed in bug 69842 (v6.4.2.1007) to permit this flag to be
78 * specified on all firmware variants.
80 want_outer_classes = B_TRUE;
82 want_outer_classes = B_FALSE;
85 req.emr_cmd = MC_CMD_INIT_RXQ;
86 req.emr_in_buf = payload;
87 req.emr_in_length = MC_CMD_INIT_RXQ_V3_IN_LEN;
88 req.emr_out_buf = payload;
89 req.emr_out_length = MC_CMD_INIT_RXQ_V3_OUT_LEN;
91 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);
92 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, eep->ee_index);
93 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);
94 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);
95 MCDI_IN_POPULATE_DWORD_10(req, INIT_RXQ_EXT_IN_FLAGS,
96 INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0,
97 INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0,
98 INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0,
99 INIT_RXQ_EXT_IN_CRC_MODE, 0,
100 INIT_RXQ_EXT_IN_FLAG_PREFIX, 1,
101 INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER, disable_scatter,
102 INIT_RXQ_EXT_IN_DMA_MODE,
104 INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize,
105 INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes,
106 INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV, no_cont_ev);
107 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);
108 MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
110 if (es_bufs_per_desc > 0) {
111 MCDI_IN_SET_DWORD(req,
112 INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET,
114 MCDI_IN_SET_DWORD(req,
115 INIT_RXQ_V3_IN_ES_MAX_DMA_LEN, es_max_dma_len);
116 MCDI_IN_SET_DWORD(req,
117 INIT_RXQ_V3_IN_ES_PACKET_STRIDE, es_buf_stride);
118 MCDI_IN_SET_DWORD(req,
119 INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT,
123 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_RXQ_IN_DMA_ADDR);
124 addr = EFSYS_MEM_ADDR(esmp);
126 for (i = 0; i < npages; i++) {
127 EFX_POPULATE_QWORD_2(*dma_addr,
128 EFX_DWORD_1, (uint32_t)(addr >> 32),
129 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
132 addr += EFX_BUF_SIZE;
135 efx_mcdi_execute(enp, &req);
137 if (req.emr_rc != 0) {
149 EFSYS_PROBE1(fail1, efx_rc_t, rc);
154 static __checkReturn efx_rc_t
157 __in uint32_t instance)
160 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_RXQ_IN_LEN,
161 MC_CMD_FINI_RXQ_OUT_LEN);
164 req.emr_cmd = MC_CMD_FINI_RXQ;
165 req.emr_in_buf = payload;
166 req.emr_in_length = MC_CMD_FINI_RXQ_IN_LEN;
167 req.emr_out_buf = payload;
168 req.emr_out_length = MC_CMD_FINI_RXQ_OUT_LEN;
170 MCDI_IN_SET_DWORD(req, FINI_RXQ_IN_INSTANCE, instance);
172 efx_mcdi_execute_quiet(enp, &req);
174 if (req.emr_rc != 0) {
183 * EALREADY is not an error, but indicates that the MC has rebooted and
184 * that the RXQ has already been destroyed.
187 EFSYS_PROBE1(fail1, efx_rc_t, rc);
192 #if EFSYS_OPT_RX_SCALE
193 static __checkReturn efx_rc_t
194 efx_mcdi_rss_context_alloc(
196 __in efx_rx_scale_context_type_t type,
197 __in uint32_t num_queues,
198 __out uint32_t *rss_contextp)
201 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
202 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
203 uint32_t rss_context;
204 uint32_t context_type;
207 if (num_queues > EFX_MAXRSS) {
213 case EFX_RX_SCALE_EXCLUSIVE:
214 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
216 case EFX_RX_SCALE_SHARED:
217 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
224 req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
225 req.emr_in_buf = payload;
226 req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
227 req.emr_out_buf = payload;
228 req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
230 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
231 EVB_PORT_ID_ASSIGNED);
232 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
235 * For exclusive contexts, NUM_QUEUES is only used to validate
236 * indirection table offsets.
237 * For shared contexts, the provided context will spread traffic over
238 * NUM_QUEUES many queues.
240 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
242 efx_mcdi_execute(enp, &req);
244 if (req.emr_rc != 0) {
249 if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
254 rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
255 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
260 *rss_contextp = rss_context;
273 EFSYS_PROBE1(fail1, efx_rc_t, rc);
277 #endif /* EFSYS_OPT_RX_SCALE */
279 #if EFSYS_OPT_RX_SCALE
281 efx_mcdi_rss_context_free(
283 __in uint32_t rss_context)
286 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
287 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN);
290 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
295 req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
296 req.emr_in_buf = payload;
297 req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
298 req.emr_out_buf = payload;
299 req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
301 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
303 efx_mcdi_execute_quiet(enp, &req);
305 if (req.emr_rc != 0) {
315 EFSYS_PROBE1(fail1, efx_rc_t, rc);
319 #endif /* EFSYS_OPT_RX_SCALE */
321 #if EFSYS_OPT_RX_SCALE
323 efx_mcdi_rss_context_set_flags(
325 __in uint32_t rss_context,
326 __in efx_rx_hash_type_t type)
328 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
330 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
331 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN);
334 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
335 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN);
336 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
337 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH);
338 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
339 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN);
340 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
341 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH);
342 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
343 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN);
344 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
345 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH);
346 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
347 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN);
348 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
349 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH);
351 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
356 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
357 req.emr_in_buf = payload;
358 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
359 req.emr_out_buf = payload;
360 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
362 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
366 * If the firmware lacks support for additional modes, RSS_MODE
367 * fields must contain zeros, otherwise the operation will fail.
369 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE)
370 type &= EFX_RX_HASH_LEGACY_MASK;
372 MCDI_IN_POPULATE_DWORD_10(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
373 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
374 (type & EFX_RX_HASH_IPV4) ? 1 : 0,
375 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
376 (type & EFX_RX_HASH_TCPIPV4) ? 1 : 0,
377 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
378 (type & EFX_RX_HASH_IPV6) ? 1 : 0,
379 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
380 (type & EFX_RX_HASH_TCPIPV6) ? 1 : 0,
381 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE,
382 (type >> EFX_RX_CLASS_IPV4_TCP_LBN) &
383 EFX_MASK32(EFX_RX_CLASS_IPV4_TCP),
384 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE,
385 (type >> EFX_RX_CLASS_IPV4_UDP_LBN) &
386 EFX_MASK32(EFX_RX_CLASS_IPV4_UDP),
387 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE,
388 (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4),
389 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE,
390 (type >> EFX_RX_CLASS_IPV6_TCP_LBN) &
391 EFX_MASK32(EFX_RX_CLASS_IPV6_TCP),
392 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE,
393 (type >> EFX_RX_CLASS_IPV6_UDP_LBN) &
394 EFX_MASK32(EFX_RX_CLASS_IPV6_UDP),
395 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE,
396 (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6));
398 efx_mcdi_execute(enp, &req);
400 if (req.emr_rc != 0) {
410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
414 #endif /* EFSYS_OPT_RX_SCALE */
416 #if EFSYS_OPT_RX_SCALE
418 efx_mcdi_rss_context_set_key(
420 __in uint32_t rss_context,
421 __in_ecount(n) uint8_t *key,
425 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
426 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN);
429 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
434 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
435 req.emr_in_buf = payload;
436 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
437 req.emr_out_buf = payload;
438 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
440 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
443 EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
444 if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
449 memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
452 efx_mcdi_execute(enp, &req);
454 if (req.emr_rc != 0) {
466 EFSYS_PROBE1(fail1, efx_rc_t, rc);
470 #endif /* EFSYS_OPT_RX_SCALE */
472 #if EFSYS_OPT_RX_SCALE
474 efx_mcdi_rss_context_set_table(
476 __in uint32_t rss_context,
477 __in_ecount(n) unsigned int *table,
481 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
482 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN);
486 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
491 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
492 req.emr_in_buf = payload;
493 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
494 req.emr_out_buf = payload;
495 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
497 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
501 MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
504 i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
506 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
509 efx_mcdi_execute(enp, &req);
511 if (req.emr_rc != 0) {
521 EFSYS_PROBE1(fail1, efx_rc_t, rc);
525 #endif /* EFSYS_OPT_RX_SCALE */
528 __checkReturn efx_rc_t
532 #if EFSYS_OPT_RX_SCALE
534 if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
535 &enp->en_rss_context) == 0) {
537 * Allocated an exclusive RSS context, which allows both the
538 * indirection table and key to be modified.
540 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
541 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
544 * Failed to allocate an exclusive RSS context. Continue
545 * operation without support for RSS. The pseudo-header in
546 * received packets will not contain a Toeplitz hash value.
548 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
549 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
552 #endif /* EFSYS_OPT_RX_SCALE */
557 #if EFSYS_OPT_RX_SCATTER
558 __checkReturn efx_rc_t
559 ef10_rx_scatter_enable(
561 __in unsigned int buf_size)
563 _NOTE(ARGUNUSED(enp, buf_size))
566 #endif /* EFSYS_OPT_RX_SCATTER */
568 #if EFSYS_OPT_RX_SCALE
569 __checkReturn efx_rc_t
570 ef10_rx_scale_context_alloc(
572 __in efx_rx_scale_context_type_t type,
573 __in uint32_t num_queues,
574 __out uint32_t *rss_contextp)
578 rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
585 EFSYS_PROBE1(fail1, efx_rc_t, rc);
588 #endif /* EFSYS_OPT_RX_SCALE */
590 #if EFSYS_OPT_RX_SCALE
591 __checkReturn efx_rc_t
592 ef10_rx_scale_context_free(
594 __in uint32_t rss_context)
598 rc = efx_mcdi_rss_context_free(enp, rss_context);
605 EFSYS_PROBE1(fail1, efx_rc_t, rc);
608 #endif /* EFSYS_OPT_RX_SCALE */
610 #if EFSYS_OPT_RX_SCALE
611 __checkReturn efx_rc_t
612 ef10_rx_scale_mode_set(
614 __in uint32_t rss_context,
615 __in efx_rx_hash_alg_t alg,
616 __in efx_rx_hash_type_t type,
617 __in boolean_t insert)
619 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
622 EFSYS_ASSERT3U(insert, ==, B_TRUE);
624 if ((encp->enc_rx_scale_hash_alg_mask & (1U << alg)) == 0 ||
630 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
631 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
635 rss_context = enp->en_rss_context;
638 if ((rc = efx_mcdi_rss_context_set_flags(enp,
639 rss_context, type)) != 0)
649 EFSYS_PROBE1(fail1, efx_rc_t, rc);
653 #endif /* EFSYS_OPT_RX_SCALE */
655 #if EFSYS_OPT_RX_SCALE
656 __checkReturn efx_rc_t
657 ef10_rx_scale_key_set(
659 __in uint32_t rss_context,
660 __in_ecount(n) uint8_t *key,
665 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
666 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
668 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
669 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
673 rss_context = enp->en_rss_context;
676 if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
684 EFSYS_PROBE1(fail1, efx_rc_t, rc);
688 #endif /* EFSYS_OPT_RX_SCALE */
690 #if EFSYS_OPT_RX_SCALE
691 __checkReturn efx_rc_t
692 ef10_rx_scale_tbl_set(
694 __in uint32_t rss_context,
695 __in_ecount(n) unsigned int *table,
701 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
702 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
706 rss_context = enp->en_rss_context;
709 if ((rc = efx_mcdi_rss_context_set_table(enp,
710 rss_context, table, n)) != 0)
718 EFSYS_PROBE1(fail1, efx_rc_t, rc);
722 #endif /* EFSYS_OPT_RX_SCALE */
726 * EF10 RX pseudo-header
727 * ---------------------
729 * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
731 * +00: Toeplitz hash value.
732 * (32bit little-endian)
733 * +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
735 * +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
737 * +08: Packet Length. Zero if the RX datapath was in cut-through mode.
738 * (16bit little-endian)
739 * +10: MAC timestamp. Zero if timestamping is not enabled.
740 * (32bit little-endian)
742 * See "The RX Pseudo-header" in SF-109306-TC.
745 __checkReturn efx_rc_t
746 ef10_rx_prefix_pktlen(
748 __in uint8_t *buffer,
749 __out uint16_t *lengthp)
751 _NOTE(ARGUNUSED(enp))
754 * The RX pseudo-header contains the packet length, excluding the
755 * pseudo-header. If the hardware receive datapath was operating in
756 * cut-through mode then the length in the RX pseudo-header will be
757 * zero, and the packet length must be obtained from the DMA length
758 * reported in the RX event.
760 *lengthp = buffer[8] | (buffer[9] << 8);
764 #if EFSYS_OPT_RX_SCALE
765 __checkReturn uint32_t
768 __in efx_rx_hash_alg_t func,
769 __in uint8_t *buffer)
771 _NOTE(ARGUNUSED(enp))
774 case EFX_RX_HASHALG_PACKED_STREAM:
775 case EFX_RX_HASHALG_TOEPLITZ:
786 #endif /* EFSYS_OPT_RX_SCALE */
788 #if EFSYS_OPT_RX_PACKED_STREAM
790 * Fake length for RXQ descriptors in packed stream mode
791 * to make hardware happy
793 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
799 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
801 __in unsigned int ndescs,
802 __in unsigned int completed,
803 __in unsigned int added)
810 _NOTE(ARGUNUSED(completed))
812 #if EFSYS_OPT_RX_PACKED_STREAM
814 * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
815 * and equal to 0 after applying mask. Hardware does not like it.
817 if (erp->er_ev_qstate->eers_rx_packed_stream)
818 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
821 /* The client driver must not overfill the queue */
822 EFSYS_ASSERT3U(added - completed + ndescs, <=,
823 EFX_RXQ_LIMIT(erp->er_mask + 1));
825 id = added & (erp->er_mask);
826 for (i = 0; i < ndescs; i++) {
827 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
828 unsigned int, id, efsys_dma_addr_t, addrp[i],
831 EFX_POPULATE_QWORD_3(qword,
832 ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
833 ESF_DZ_RX_KER_BUF_ADDR_DW0,
834 (uint32_t)(addrp[i] & 0xffffffff),
835 ESF_DZ_RX_KER_BUF_ADDR_DW1,
836 (uint32_t)(addrp[i] >> 32));
838 offset = id * sizeof (efx_qword_t);
839 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
841 id = (id + 1) & (erp->er_mask);
848 __in unsigned int added,
849 __inout unsigned int *pushedp)
851 efx_nic_t *enp = erp->er_enp;
852 unsigned int pushed = *pushedp;
856 /* Hardware has alignment restriction for WPTR */
857 wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN);
863 /* Push the populated descriptors out */
864 wptr &= erp->er_mask;
866 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
868 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
869 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
870 wptr, pushed & erp->er_mask);
871 EFSYS_PIO_WRITE_BARRIER();
872 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
873 erp->er_index, &dword, B_FALSE);
876 #if EFSYS_OPT_RX_PACKED_STREAM
879 ef10_rx_qpush_ps_credits(
882 efx_nic_t *enp = erp->er_enp;
884 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
887 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
889 if (rxq_state->eers_rx_packed_stream_credits == 0)
893 * It is a bug if we think that FW has utilized more
894 * credits than it is allowed to have (maximum). However,
895 * make sure that we do not credit more than maximum anyway.
897 credits = MIN(rxq_state->eers_rx_packed_stream_credits,
898 EFX_RX_PACKED_STREAM_MAX_CREDITS);
899 EFX_POPULATE_DWORD_3(dword,
900 ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
901 ERF_DZ_RX_DESC_MAGIC_CMD,
902 ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
903 ERF_DZ_RX_DESC_MAGIC_DATA, credits);
904 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
905 erp->er_index, &dword, B_FALSE);
907 rxq_state->eers_rx_packed_stream_credits = 0;
911 * In accordance with SF-112241-TC the received data has the following layout:
912 * - 8 byte pseudo-header which consist of:
913 * - 4 byte little-endian timestamp
914 * - 2 byte little-endian captured length in bytes
915 * - 2 byte little-endian original packet length in bytes
916 * - captured packet bytes
917 * - optional padding to align to 64 bytes boundary
918 * - 64 bytes scratch space for the host software
920 __checkReturn uint8_t *
921 ef10_rx_qps_packet_info(
923 __in uint8_t *buffer,
924 __in uint32_t buffer_length,
925 __in uint32_t current_offset,
926 __out uint16_t *lengthp,
927 __out uint32_t *next_offsetp,
928 __out uint32_t *timestamp)
933 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
935 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
937 buffer += current_offset;
938 pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
940 qwordp = (efx_qword_t *)buffer;
941 *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
942 *lengthp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
943 buf_len = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
945 buf_len = P2ROUNDUP(buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
946 EFX_RX_PACKED_STREAM_ALIGNMENT);
948 current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
950 EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
951 EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
953 if ((*next_offsetp ^ current_offset) &
954 EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
955 rxq_state->eers_rx_packed_stream_credits++;
963 __checkReturn efx_rc_t
967 efx_nic_t *enp = erp->er_enp;
970 if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
977 * EALREADY is not an error, but indicates that the MC has rebooted and
978 * that the RXQ has already been destroyed. Callers need to know that
979 * the RXQ flush has completed to avoid waiting until timeout for a
980 * flush done event that will not be delivered.
983 EFSYS_PROBE1(fail1, efx_rc_t, rc);
993 _NOTE(ARGUNUSED(erp))
997 __checkReturn efx_rc_t
1000 __in unsigned int index,
1001 __in unsigned int label,
1002 __in efx_rxq_type_t type,
1003 __in_opt const efx_rxq_type_data_t *type_data,
1004 __in efsys_mem_t *esmp,
1007 __in unsigned int flags,
1008 __in efx_evq_t *eep,
1009 __in efx_rxq_t *erp)
1011 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1013 boolean_t disable_scatter;
1014 boolean_t want_inner_classes;
1015 unsigned int ps_buf_size;
1016 uint32_t es_bufs_per_desc = 0;
1017 uint32_t es_max_dma_len = 0;
1018 uint32_t es_buf_stride = 0;
1019 uint32_t hol_block_timeout = 0;
1021 _NOTE(ARGUNUSED(id, erp, type_data))
1023 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
1024 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1025 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1027 if (index >= encp->enc_rxq_limit) {
1033 case EFX_RXQ_TYPE_DEFAULT:
1036 #if EFSYS_OPT_RX_PACKED_STREAM
1037 case EFX_RXQ_TYPE_PACKED_STREAM:
1038 if (type_data == NULL) {
1042 switch (type_data->ertd_packed_stream.eps_buf_size) {
1043 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
1044 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
1046 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
1047 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
1049 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
1050 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
1052 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
1053 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
1055 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
1056 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
1063 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1064 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1065 case EFX_RXQ_TYPE_ES_SUPER_BUFFER:
1066 if (type_data == NULL) {
1072 type_data->ertd_es_super_buffer.eessb_bufs_per_desc;
1074 type_data->ertd_es_super_buffer.eessb_max_dma_len;
1076 type_data->ertd_es_super_buffer.eessb_buf_stride;
1078 type_data->ertd_es_super_buffer.eessb_hol_block_timeout;
1080 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1086 #if EFSYS_OPT_RX_PACKED_STREAM
1087 if (ps_buf_size != 0) {
1088 /* Check if datapath firmware supports packed stream mode */
1089 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
1093 /* Check if packed stream allows configurable buffer sizes */
1094 if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
1095 (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
1100 #else /* EFSYS_OPT_RX_PACKED_STREAM */
1101 EFSYS_ASSERT(ps_buf_size == 0);
1102 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1104 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1105 if (es_bufs_per_desc > 0) {
1106 if (encp->enc_rx_es_super_buffer_supported == B_FALSE) {
1110 if (!IS_P2ALIGNED(es_max_dma_len,
1111 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1115 if (!IS_P2ALIGNED(es_buf_stride,
1116 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1121 #else /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1122 EFSYS_ASSERT(es_bufs_per_desc == 0);
1123 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1125 /* Scatter can only be disabled if the firmware supports doing so */
1126 if (flags & EFX_RXQ_FLAG_SCATTER)
1127 disable_scatter = B_FALSE;
1129 disable_scatter = encp->enc_rx_disable_scatter_supported;
1131 if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
1132 want_inner_classes = B_TRUE;
1134 want_inner_classes = B_FALSE;
1136 if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep, label, index,
1137 esmp, disable_scatter, want_inner_classes,
1138 ps_buf_size, es_bufs_per_desc, es_max_dma_len,
1139 es_buf_stride, hol_block_timeout)) != 0)
1143 erp->er_label = label;
1145 ef10_ev_rxlabel_init(eep, erp, label, type);
1147 erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
1152 EFSYS_PROBE(fail11);
1153 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1155 EFSYS_PROBE(fail10);
1160 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1161 #if EFSYS_OPT_RX_PACKED_STREAM
1166 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1169 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1172 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1173 #if EFSYS_OPT_RX_PACKED_STREAM
1178 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1180 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1187 __in efx_rxq_t *erp)
1189 efx_nic_t *enp = erp->er_enp;
1190 efx_evq_t *eep = erp->er_eep;
1191 unsigned int label = erp->er_label;
1193 ef10_ev_rxlabel_fini(eep, label);
1195 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1196 --enp->en_rx_qcount;
1198 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1203 __in efx_nic_t *enp)
1205 #if EFSYS_OPT_RX_SCALE
1206 if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1207 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1208 enp->en_rss_context = 0;
1209 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1211 _NOTE(ARGUNUSED(enp))
1212 #endif /* EFSYS_OPT_RX_SCALE */
1215 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */