1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 extern __checkReturn efx_rc_t
134 __in efx_nic_t *enp);
136 extern __checkReturn efx_rc_t
138 __in efx_nic_t *enp);
140 extern __checkReturn efx_rc_t
142 __in efx_nic_t *enp);
146 extern __checkReturn efx_rc_t
147 efx_nic_register_test(
148 __in efx_nic_t *enp);
150 #endif /* EFSYS_OPT_DIAG */
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
162 __in efx_nic_t *enp);
164 #define EFX_PCIE_LINK_SPEED_GEN1 1
165 #define EFX_PCIE_LINK_SPEED_GEN2 2
166 #define EFX_PCIE_LINK_SPEED_GEN3 3
168 typedef enum efx_pcie_link_performance_e {
169 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
170 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
171 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
172 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
173 } efx_pcie_link_performance_t;
175 extern __checkReturn efx_rc_t
176 efx_nic_calculate_pcie_link_bandwidth(
177 __in uint32_t pcie_link_width,
178 __in uint32_t pcie_link_gen,
179 __out uint32_t *bandwidth_mbpsp);
181 extern __checkReturn efx_rc_t
182 efx_nic_check_pcie_link_speed(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out efx_pcie_link_performance_t *resultp);
190 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
191 /* Huntington and Medford require MCDIv2 commands */
192 #define WITH_MCDI_V2 1
195 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
197 typedef enum efx_mcdi_exception_e {
198 EFX_MCDI_EXCEPTION_MC_REBOOT,
199 EFX_MCDI_EXCEPTION_MC_BADASSERT,
200 } efx_mcdi_exception_t;
202 #if EFSYS_OPT_MCDI_LOGGING
203 typedef enum efx_log_msg_e {
205 EFX_LOG_MCDI_REQUEST,
206 EFX_LOG_MCDI_RESPONSE,
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
210 typedef struct efx_mcdi_transport_s {
212 efsys_mem_t *emt_dma_mem;
213 void (*emt_execute)(void *, efx_mcdi_req_t *);
214 void (*emt_ev_cpl)(void *);
215 void (*emt_exception)(void *, efx_mcdi_exception_t);
216 #if EFSYS_OPT_MCDI_LOGGING
217 void (*emt_logger)(void *, efx_log_msg_t,
218 void *, size_t, void *, size_t);
219 #endif /* EFSYS_OPT_MCDI_LOGGING */
220 #if EFSYS_OPT_MCDI_PROXY_AUTH
221 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
222 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
223 } efx_mcdi_transport_t;
225 extern __checkReturn efx_rc_t
228 __in const efx_mcdi_transport_t *mtp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
236 __in efx_nic_t *enp);
239 efx_mcdi_get_timeout(
241 __in efx_mcdi_req_t *emrp,
242 __out uint32_t *usec_timeoutp);
245 efx_mcdi_request_start(
247 __in efx_mcdi_req_t *emrp,
248 __in boolean_t ev_cpl);
250 extern __checkReturn boolean_t
251 efx_mcdi_request_poll(
252 __in efx_nic_t *enp);
254 extern __checkReturn boolean_t
255 efx_mcdi_request_abort(
256 __in efx_nic_t *enp);
260 __in efx_nic_t *enp);
262 #endif /* EFSYS_OPT_MCDI */
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
412 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
414 #endif /* EFSYS_OPT_MAC_STATS */
416 typedef enum efx_link_mode_e {
417 EFX_LINK_UNKNOWN = 0,
433 #define EFX_MAC_ADDR_LEN 6
435 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
437 #define EFX_MAC_MULTICAST_LIST_MAX 256
439 #define EFX_MAC_SDU_MAX 9202
441 #define EFX_MAC_PDU_ADJUSTMENT \
445 + /* bug16011 */ 16) \
447 #define EFX_MAC_PDU(_sdu) \
448 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
451 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
452 * the SDU rounded up slightly.
454 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
456 #define EFX_MAC_PDU_MIN 60
457 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
459 extern __checkReturn efx_rc_t
464 extern __checkReturn efx_rc_t
469 extern __checkReturn efx_rc_t
474 extern __checkReturn efx_rc_t
477 __in boolean_t all_unicst,
478 __in boolean_t mulcst,
479 __in boolean_t all_mulcst,
480 __in boolean_t brdcst);
482 extern __checkReturn efx_rc_t
483 efx_mac_multicast_list_set(
485 __in_ecount(6*count) uint8_t const *addrs,
488 extern __checkReturn efx_rc_t
489 efx_mac_filter_default_rxq_set(
492 __in boolean_t using_rss);
495 efx_mac_filter_default_rxq_clear(
496 __in efx_nic_t *enp);
498 extern __checkReturn efx_rc_t
501 __in boolean_t enabled);
503 extern __checkReturn efx_rc_t
506 __out boolean_t *mac_upp);
508 #define EFX_FCNTL_RESPOND 0x00000001
509 #define EFX_FCNTL_GENERATE 0x00000002
511 extern __checkReturn efx_rc_t
514 __in unsigned int fcntl,
515 __in boolean_t autoneg);
520 __out unsigned int *fcntl_wantedp,
521 __out unsigned int *fcntl_linkp);
524 #if EFSYS_OPT_MAC_STATS
528 extern __checkReturn const char *
531 __in unsigned int id);
533 #endif /* EFSYS_OPT_NAMES */
535 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
537 #define EFX_MAC_STATS_MASK_NPAGES \
538 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
539 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
542 * Get mask of MAC statistics supported by the hardware.
544 * If mask_size is insufficient to return the mask, EINVAL error is
545 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
546 * (which is sizeof (uint32_t)) is sufficient.
548 extern __checkReturn efx_rc_t
549 efx_mac_stats_get_mask(
551 __out_bcount(mask_size) uint32_t *maskp,
552 __in size_t mask_size);
554 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
555 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
556 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
558 #define EFX_MAC_STATS_SIZE 0x400
560 extern __checkReturn efx_rc_t
562 __in efx_nic_t *enp);
565 * Upload mac statistics supported by the hardware into the given buffer.
567 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
570 * The hardware will only DMA statistics that it understands (of course).
571 * Drivers should not make any assumptions about which statistics are
572 * supported, especially when the statistics are generated by firmware.
574 * Thus, drivers should zero this buffer before use, so that not-understood
575 * statistics read back as zero.
577 extern __checkReturn efx_rc_t
578 efx_mac_stats_upload(
580 __in efsys_mem_t *esmp);
582 extern __checkReturn efx_rc_t
583 efx_mac_stats_periodic(
585 __in efsys_mem_t *esmp,
586 __in uint16_t period_ms,
587 __in boolean_t events);
589 extern __checkReturn efx_rc_t
590 efx_mac_stats_update(
592 __in efsys_mem_t *esmp,
593 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
594 __inout_opt uint32_t *generationp);
596 #endif /* EFSYS_OPT_MAC_STATS */
600 typedef enum efx_mon_type_e {
612 __in efx_nic_t *enp);
614 #endif /* EFSYS_OPT_NAMES */
616 extern __checkReturn efx_rc_t
618 __in efx_nic_t *enp);
620 #if EFSYS_OPT_MON_STATS
622 #define EFX_MON_STATS_PAGE_SIZE 0x100
623 #define EFX_MON_MASK_ELEMENT_SIZE 32
625 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock fcc1b6748432e1ac */
626 typedef enum efx_mon_stat_e {
633 EFX_MON_STAT_EXT_TEMP,
634 EFX_MON_STAT_INT_TEMP,
637 EFX_MON_STAT_INT_COOLING,
638 EFX_MON_STAT_EXT_COOLING,
646 EFX_MON_STAT_AOE_TEMP,
647 EFX_MON_STAT_PSU_AOE_TEMP,
648 EFX_MON_STAT_PSU_TEMP,
654 EFX_MON_STAT_VAOE_IN,
656 EFX_MON_STAT_IAOE_IN,
657 EFX_MON_STAT_NIC_POWER,
661 EFX_MON_STAT_0_9V_ADC,
662 EFX_MON_STAT_INT_TEMP2,
663 EFX_MON_STAT_VREG_TEMP,
664 EFX_MON_STAT_VREG_0_9V_TEMP,
665 EFX_MON_STAT_VREG_1_2V_TEMP,
666 EFX_MON_STAT_INT_VPTAT,
667 EFX_MON_STAT_INT_ADC_TEMP,
668 EFX_MON_STAT_EXT_VPTAT,
669 EFX_MON_STAT_EXT_ADC_TEMP,
670 EFX_MON_STAT_AMBIENT_TEMP,
671 EFX_MON_STAT_AIRFLOW,
672 EFX_MON_STAT_VDD08D_VSS08D_CSR,
673 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
674 EFX_MON_STAT_HOTPOINT_TEMP,
675 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
676 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
677 EFX_MON_STAT_MUM_VCC,
680 EFX_MON_STAT_0V9_A_TEMP,
683 EFX_MON_STAT_0V9_B_TEMP,
684 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
685 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
686 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
687 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
688 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
689 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
690 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
691 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
692 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
693 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
694 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
695 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
696 EFX_MON_STAT_SODIMM_VOUT,
697 EFX_MON_STAT_SODIMM_0_TEMP,
698 EFX_MON_STAT_SODIMM_1_TEMP,
699 EFX_MON_STAT_PHY0_VCC,
700 EFX_MON_STAT_PHY1_VCC,
701 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
702 EFX_MON_STAT_BOARD_FRONT_TEMP,
703 EFX_MON_STAT_BOARD_BACK_TEMP,
711 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
713 typedef enum efx_mon_stat_state_e {
714 EFX_MON_STAT_STATE_OK = 0,
715 EFX_MON_STAT_STATE_WARNING = 1,
716 EFX_MON_STAT_STATE_FATAL = 2,
717 EFX_MON_STAT_STATE_BROKEN = 3,
718 EFX_MON_STAT_STATE_NO_READING = 4,
719 } efx_mon_stat_state_t;
721 typedef struct efx_mon_stat_value_s {
724 } efx_mon_stat_value_t;
731 __in efx_mon_stat_t id);
733 #endif /* EFSYS_OPT_NAMES */
735 extern __checkReturn efx_rc_t
736 efx_mon_stats_update(
738 __in efsys_mem_t *esmp,
739 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
741 #endif /* EFSYS_OPT_MON_STATS */
745 __in efx_nic_t *enp);
749 extern __checkReturn efx_rc_t
751 __in efx_nic_t *enp);
753 #if EFSYS_OPT_PHY_LED_CONTROL
755 typedef enum efx_phy_led_mode_e {
756 EFX_PHY_LED_DEFAULT = 0,
761 } efx_phy_led_mode_t;
763 extern __checkReturn efx_rc_t
766 __in efx_phy_led_mode_t mode);
768 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
770 extern __checkReturn efx_rc_t
772 __in efx_nic_t *enp);
774 #if EFSYS_OPT_LOOPBACK
776 typedef enum efx_loopback_type_e {
777 EFX_LOOPBACK_OFF = 0,
778 EFX_LOOPBACK_DATA = 1,
779 EFX_LOOPBACK_GMAC = 2,
780 EFX_LOOPBACK_XGMII = 3,
781 EFX_LOOPBACK_XGXS = 4,
782 EFX_LOOPBACK_XAUI = 5,
783 EFX_LOOPBACK_GMII = 6,
784 EFX_LOOPBACK_SGMII = 7,
785 EFX_LOOPBACK_XGBR = 8,
786 EFX_LOOPBACK_XFI = 9,
787 EFX_LOOPBACK_XAUI_FAR = 10,
788 EFX_LOOPBACK_GMII_FAR = 11,
789 EFX_LOOPBACK_SGMII_FAR = 12,
790 EFX_LOOPBACK_XFI_FAR = 13,
791 EFX_LOOPBACK_GPHY = 14,
792 EFX_LOOPBACK_PHY_XS = 15,
793 EFX_LOOPBACK_PCS = 16,
794 EFX_LOOPBACK_PMA_PMD = 17,
795 EFX_LOOPBACK_XPORT = 18,
796 EFX_LOOPBACK_XGMII_WS = 19,
797 EFX_LOOPBACK_XAUI_WS = 20,
798 EFX_LOOPBACK_XAUI_WS_FAR = 21,
799 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
800 EFX_LOOPBACK_GMII_WS = 23,
801 EFX_LOOPBACK_XFI_WS = 24,
802 EFX_LOOPBACK_XFI_WS_FAR = 25,
803 EFX_LOOPBACK_PHYXS_WS = 26,
804 EFX_LOOPBACK_PMA_INT = 27,
805 EFX_LOOPBACK_SD_NEAR = 28,
806 EFX_LOOPBACK_SD_FAR = 29,
807 EFX_LOOPBACK_PMA_INT_WS = 30,
808 EFX_LOOPBACK_SD_FEP2_WS = 31,
809 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
810 EFX_LOOPBACK_SD_FEP_WS = 33,
811 EFX_LOOPBACK_SD_FES_WS = 34,
812 EFX_LOOPBACK_AOE_INT_NEAR = 35,
813 EFX_LOOPBACK_DATA_WS = 36,
814 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
816 } efx_loopback_type_t;
818 typedef enum efx_loopback_kind_e {
819 EFX_LOOPBACK_KIND_OFF = 0,
820 EFX_LOOPBACK_KIND_ALL,
821 EFX_LOOPBACK_KIND_MAC,
822 EFX_LOOPBACK_KIND_PHY,
824 } efx_loopback_kind_t;
828 __in efx_loopback_kind_t loopback_kind,
829 __out efx_qword_t *maskp);
831 extern __checkReturn efx_rc_t
832 efx_port_loopback_set(
834 __in efx_link_mode_t link_mode,
835 __in efx_loopback_type_t type);
839 extern __checkReturn const char *
840 efx_loopback_type_name(
842 __in efx_loopback_type_t type);
844 #endif /* EFSYS_OPT_NAMES */
846 #endif /* EFSYS_OPT_LOOPBACK */
848 extern __checkReturn efx_rc_t
851 __out_opt efx_link_mode_t *link_modep);
855 __in efx_nic_t *enp);
857 typedef enum efx_phy_cap_type_e {
858 EFX_PHY_CAP_INVALID = 0,
865 EFX_PHY_CAP_10000FDX,
869 EFX_PHY_CAP_40000FDX,
871 EFX_PHY_CAP_100000FDX,
872 EFX_PHY_CAP_25000FDX,
873 EFX_PHY_CAP_50000FDX,
875 } efx_phy_cap_type_t;
878 #define EFX_PHY_CAP_CURRENT 0x00000000
879 #define EFX_PHY_CAP_DEFAULT 0x00000001
880 #define EFX_PHY_CAP_PERM 0x00000002
886 __out uint32_t *maskp);
888 extern __checkReturn efx_rc_t
896 __out uint32_t *maskp);
898 extern __checkReturn efx_rc_t
901 __out uint32_t *ouip);
903 typedef enum efx_phy_media_type_e {
904 EFX_PHY_MEDIA_INVALID = 0,
909 EFX_PHY_MEDIA_SFP_PLUS,
910 EFX_PHY_MEDIA_BASE_T,
911 EFX_PHY_MEDIA_QSFP_PLUS,
913 } efx_phy_media_type_t;
916 * Get the type of medium currently used. If the board has ports for
917 * modules, a module is present, and we recognise the media type of
918 * the module, then this will be the media type of the module.
919 * Otherwise it will be the media type of the port.
922 efx_phy_media_type_get(
924 __out efx_phy_media_type_t *typep);
926 extern __checkReturn efx_rc_t
927 efx_phy_module_get_info(
929 __in uint8_t dev_addr,
932 __out_bcount(len) uint8_t *data);
934 #if EFSYS_OPT_PHY_STATS
936 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
937 typedef enum efx_phy_stat_e {
939 EFX_PHY_STAT_PMA_PMD_LINK_UP,
940 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
941 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
942 EFX_PHY_STAT_PMA_PMD_REV_A,
943 EFX_PHY_STAT_PMA_PMD_REV_B,
944 EFX_PHY_STAT_PMA_PMD_REV_C,
945 EFX_PHY_STAT_PMA_PMD_REV_D,
946 EFX_PHY_STAT_PCS_LINK_UP,
947 EFX_PHY_STAT_PCS_RX_FAULT,
948 EFX_PHY_STAT_PCS_TX_FAULT,
949 EFX_PHY_STAT_PCS_BER,
950 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
951 EFX_PHY_STAT_PHY_XS_LINK_UP,
952 EFX_PHY_STAT_PHY_XS_RX_FAULT,
953 EFX_PHY_STAT_PHY_XS_TX_FAULT,
954 EFX_PHY_STAT_PHY_XS_ALIGN,
955 EFX_PHY_STAT_PHY_XS_SYNC_A,
956 EFX_PHY_STAT_PHY_XS_SYNC_B,
957 EFX_PHY_STAT_PHY_XS_SYNC_C,
958 EFX_PHY_STAT_PHY_XS_SYNC_D,
959 EFX_PHY_STAT_AN_LINK_UP,
960 EFX_PHY_STAT_AN_MASTER,
961 EFX_PHY_STAT_AN_LOCAL_RX_OK,
962 EFX_PHY_STAT_AN_REMOTE_RX_OK,
963 EFX_PHY_STAT_CL22EXT_LINK_UP,
968 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
969 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
970 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
971 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
972 EFX_PHY_STAT_AN_COMPLETE,
973 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
974 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
975 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
976 EFX_PHY_STAT_PCS_FW_VERSION_0,
977 EFX_PHY_STAT_PCS_FW_VERSION_1,
978 EFX_PHY_STAT_PCS_FW_VERSION_2,
979 EFX_PHY_STAT_PCS_FW_VERSION_3,
980 EFX_PHY_STAT_PCS_FW_BUILD_YY,
981 EFX_PHY_STAT_PCS_FW_BUILD_MM,
982 EFX_PHY_STAT_PCS_FW_BUILD_DD,
983 EFX_PHY_STAT_PCS_OP_MODE,
987 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
994 __in efx_phy_stat_t stat);
996 #endif /* EFSYS_OPT_NAMES */
998 #define EFX_PHY_STATS_SIZE 0x100
1000 extern __checkReturn efx_rc_t
1001 efx_phy_stats_update(
1002 __in efx_nic_t *enp,
1003 __in efsys_mem_t *esmp,
1004 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1006 #endif /* EFSYS_OPT_PHY_STATS */
1011 typedef enum efx_bist_type_e {
1012 EFX_BIST_TYPE_UNKNOWN,
1013 EFX_BIST_TYPE_PHY_NORMAL,
1014 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1015 EFX_BIST_TYPE_PHY_CABLE_LONG,
1016 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1017 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1018 EFX_BIST_TYPE_REG, /* Test the register memories */
1019 EFX_BIST_TYPE_NTYPES,
1022 typedef enum efx_bist_result_e {
1023 EFX_BIST_RESULT_UNKNOWN,
1024 EFX_BIST_RESULT_RUNNING,
1025 EFX_BIST_RESULT_PASSED,
1026 EFX_BIST_RESULT_FAILED,
1027 } efx_bist_result_t;
1029 typedef enum efx_phy_cable_status_e {
1030 EFX_PHY_CABLE_STATUS_OK,
1031 EFX_PHY_CABLE_STATUS_INVALID,
1032 EFX_PHY_CABLE_STATUS_OPEN,
1033 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1034 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1035 EFX_PHY_CABLE_STATUS_BUSY,
1036 } efx_phy_cable_status_t;
1038 typedef enum efx_bist_value_e {
1039 EFX_BIST_PHY_CABLE_LENGTH_A,
1040 EFX_BIST_PHY_CABLE_LENGTH_B,
1041 EFX_BIST_PHY_CABLE_LENGTH_C,
1042 EFX_BIST_PHY_CABLE_LENGTH_D,
1043 EFX_BIST_PHY_CABLE_STATUS_A,
1044 EFX_BIST_PHY_CABLE_STATUS_B,
1045 EFX_BIST_PHY_CABLE_STATUS_C,
1046 EFX_BIST_PHY_CABLE_STATUS_D,
1047 EFX_BIST_FAULT_CODE,
1049 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1055 EFX_BIST_MEM_EXPECT,
1056 EFX_BIST_MEM_ACTUAL,
1058 EFX_BIST_MEM_ECC_PARITY,
1059 EFX_BIST_MEM_ECC_FATAL,
1063 extern __checkReturn efx_rc_t
1064 efx_bist_enable_offline(
1065 __in efx_nic_t *enp);
1067 extern __checkReturn efx_rc_t
1069 __in efx_nic_t *enp,
1070 __in efx_bist_type_t type);
1072 extern __checkReturn efx_rc_t
1074 __in efx_nic_t *enp,
1075 __in efx_bist_type_t type,
1076 __out efx_bist_result_t *resultp,
1077 __out_opt uint32_t *value_maskp,
1078 __out_ecount_opt(count) unsigned long *valuesp,
1083 __in efx_nic_t *enp,
1084 __in efx_bist_type_t type);
1086 #endif /* EFSYS_OPT_BIST */
1088 #define EFX_FEATURE_IPV6 0x00000001
1089 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1090 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1091 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1092 #define EFX_FEATURE_MCDI 0x00000020
1093 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1094 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1095 #define EFX_FEATURE_TURBO 0x00000100
1096 #define EFX_FEATURE_MCDI_DMA 0x00000200
1097 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1098 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1099 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1100 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1101 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1103 typedef enum efx_tunnel_protocol_e {
1104 EFX_TUNNEL_PROTOCOL_NONE = 0,
1105 EFX_TUNNEL_PROTOCOL_VXLAN,
1106 EFX_TUNNEL_PROTOCOL_GENEVE,
1107 EFX_TUNNEL_PROTOCOL_NVGRE,
1109 } efx_tunnel_protocol_t;
1111 typedef enum efx_vi_window_shift_e {
1112 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1113 EFX_VI_WINDOW_SHIFT_8K = 13,
1114 EFX_VI_WINDOW_SHIFT_16K = 14,
1115 EFX_VI_WINDOW_SHIFT_64K = 16,
1116 } efx_vi_window_shift_t;
1118 typedef struct efx_nic_cfg_s {
1119 uint32_t enc_board_type;
1120 uint32_t enc_phy_type;
1122 char enc_phy_name[21];
1124 char enc_phy_revision[21];
1125 efx_mon_type_t enc_mon_type;
1126 #if EFSYS_OPT_MON_STATS
1127 uint32_t enc_mon_stat_dma_buf_size;
1128 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1130 unsigned int enc_features;
1131 efx_vi_window_shift_t enc_vi_window_shift;
1132 uint8_t enc_mac_addr[6];
1133 uint8_t enc_port; /* PHY port number */
1134 uint32_t enc_intr_vec_base;
1135 uint32_t enc_intr_limit;
1136 uint32_t enc_evq_limit;
1137 uint32_t enc_txq_limit;
1138 uint32_t enc_rxq_limit;
1139 uint32_t enc_txq_max_ndescs;
1140 uint32_t enc_buftbl_limit;
1141 uint32_t enc_piobuf_limit;
1142 uint32_t enc_piobuf_size;
1143 uint32_t enc_piobuf_min_alloc_size;
1144 uint32_t enc_evq_timer_quantum_ns;
1145 uint32_t enc_evq_timer_max_us;
1146 uint32_t enc_clk_mult;
1147 uint32_t enc_rx_prefix_size;
1148 uint32_t enc_rx_buf_align_start;
1149 uint32_t enc_rx_buf_align_end;
1150 uint32_t enc_rx_scale_max_exclusive_contexts;
1151 #if EFSYS_OPT_LOOPBACK
1152 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1153 #endif /* EFSYS_OPT_LOOPBACK */
1154 #if EFSYS_OPT_PHY_FLAGS
1155 uint32_t enc_phy_flags_mask;
1156 #endif /* EFSYS_OPT_PHY_FLAGS */
1157 #if EFSYS_OPT_PHY_LED_CONTROL
1158 uint32_t enc_led_mask;
1159 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1160 #if EFSYS_OPT_PHY_STATS
1161 uint64_t enc_phy_stat_mask;
1162 #endif /* EFSYS_OPT_PHY_STATS */
1164 uint8_t enc_mcdi_mdio_channel;
1165 #if EFSYS_OPT_PHY_STATS
1166 uint32_t enc_mcdi_phy_stat_mask;
1167 #endif /* EFSYS_OPT_PHY_STATS */
1168 #if EFSYS_OPT_MON_STATS
1169 uint32_t *enc_mcdi_sensor_maskp;
1170 uint32_t enc_mcdi_sensor_mask_size;
1171 #endif /* EFSYS_OPT_MON_STATS */
1172 #endif /* EFSYS_OPT_MCDI */
1174 uint32_t enc_bist_mask;
1175 #endif /* EFSYS_OPT_BIST */
1176 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1179 uint32_t enc_privilege_mask;
1180 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1181 boolean_t enc_bug26807_workaround;
1182 boolean_t enc_bug35388_workaround;
1183 boolean_t enc_bug41750_workaround;
1184 boolean_t enc_bug61265_workaround;
1185 boolean_t enc_rx_batching_enabled;
1186 /* Maximum number of descriptors completed in an rx event. */
1187 uint32_t enc_rx_batch_max;
1188 /* Number of rx descriptors the hardware requires for a push. */
1189 uint32_t enc_rx_push_align;
1190 /* Maximum amount of data in DMA descriptor */
1191 uint32_t enc_tx_dma_desc_size_max;
1193 * Boundary which DMA descriptor data must not cross or 0 if no
1196 uint32_t enc_tx_dma_desc_boundary;
1198 * Maximum number of bytes into the packet the TCP header can start for
1199 * the hardware to apply TSO packet edits.
1201 uint32_t enc_tx_tso_tcp_header_offset_limit;
1202 boolean_t enc_fw_assisted_tso_enabled;
1203 boolean_t enc_fw_assisted_tso_v2_enabled;
1204 /* Number of TSO contexts on the NIC (FATSOv2) */
1205 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1206 boolean_t enc_hw_tx_insert_vlan_enabled;
1207 /* Number of PFs on the NIC */
1208 uint32_t enc_hw_pf_count;
1209 /* Datapath firmware vadapter/vport/vswitch support */
1210 boolean_t enc_datapath_cap_evb;
1211 boolean_t enc_rx_disable_scatter_supported;
1212 boolean_t enc_allow_set_mac_with_installed_filters;
1213 boolean_t enc_enhanced_set_mac_supported;
1214 boolean_t enc_init_evq_v2_supported;
1215 boolean_t enc_rx_packed_stream_supported;
1216 boolean_t enc_rx_var_packed_stream_supported;
1217 boolean_t enc_pm_and_rxdp_counters;
1218 boolean_t enc_mac_stats_40g_tx_size_bins;
1219 uint32_t enc_tunnel_encapsulations_supported;
1221 * NIC global maximum for unique UDP tunnel ports shared by all
1224 uint32_t enc_tunnel_config_udp_entries_max;
1225 /* External port identifier */
1226 uint8_t enc_external_port;
1227 uint32_t enc_mcdi_max_payload_length;
1228 /* VPD may be per-PF or global */
1229 boolean_t enc_vpd_is_global;
1230 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1231 uint32_t enc_required_pcie_bandwidth_mbps;
1232 uint32_t enc_max_pcie_link_gen;
1233 /* Firmware verifies integrity of NVRAM updates */
1234 uint32_t enc_nvram_update_verify_result_supported;
1237 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1238 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1240 #define EFX_PCI_FUNCTION(_encp) \
1241 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1243 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1245 extern const efx_nic_cfg_t *
1247 __in efx_nic_t *enp);
1249 typedef struct efx_nic_fw_info_s {
1250 /* Basic FW version information */
1251 uint16_t enfi_mc_fw_version[4];
1253 * If datapath capabilities can be detected,
1254 * additional FW information is to be shown
1256 boolean_t enfi_dpcpu_fw_ids_valid;
1257 /* Rx and Tx datapath CPU FW IDs */
1258 uint16_t enfi_rx_dpcpu_fw_id;
1259 uint16_t enfi_tx_dpcpu_fw_id;
1260 } efx_nic_fw_info_t;
1262 extern __checkReturn efx_rc_t
1263 efx_nic_get_fw_version(
1264 __in efx_nic_t *enp,
1265 __out efx_nic_fw_info_t *enfip);
1267 /* Driver resource limits (minimum required/maximum usable). */
1268 typedef struct efx_drv_limits_s {
1269 uint32_t edl_min_evq_count;
1270 uint32_t edl_max_evq_count;
1272 uint32_t edl_min_rxq_count;
1273 uint32_t edl_max_rxq_count;
1275 uint32_t edl_min_txq_count;
1276 uint32_t edl_max_txq_count;
1278 /* PIO blocks (sub-allocated from piobuf) */
1279 uint32_t edl_min_pio_alloc_size;
1280 uint32_t edl_max_pio_alloc_count;
1283 extern __checkReturn efx_rc_t
1284 efx_nic_set_drv_limits(
1285 __inout efx_nic_t *enp,
1286 __in efx_drv_limits_t *edlp);
1288 typedef enum efx_nic_region_e {
1289 EFX_REGION_VI, /* Memory BAR UC mapping */
1290 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1293 extern __checkReturn efx_rc_t
1294 efx_nic_get_bar_region(
1295 __in efx_nic_t *enp,
1296 __in efx_nic_region_t region,
1297 __out uint32_t *offsetp,
1298 __out size_t *sizep);
1300 extern __checkReturn efx_rc_t
1301 efx_nic_get_vi_pool(
1302 __in efx_nic_t *enp,
1303 __out uint32_t *evq_countp,
1304 __out uint32_t *rxq_countp,
1305 __out uint32_t *txq_countp);
1310 typedef enum efx_vpd_tag_e {
1317 typedef uint16_t efx_vpd_keyword_t;
1319 typedef struct efx_vpd_value_s {
1320 efx_vpd_tag_t evv_tag;
1321 efx_vpd_keyword_t evv_keyword;
1323 uint8_t evv_value[0x100];
1327 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1329 extern __checkReturn efx_rc_t
1331 __in efx_nic_t *enp);
1333 extern __checkReturn efx_rc_t
1335 __in efx_nic_t *enp,
1336 __out size_t *sizep);
1338 extern __checkReturn efx_rc_t
1340 __in efx_nic_t *enp,
1341 __out_bcount(size) caddr_t data,
1344 extern __checkReturn efx_rc_t
1346 __in efx_nic_t *enp,
1347 __in_bcount(size) caddr_t data,
1350 extern __checkReturn efx_rc_t
1352 __in efx_nic_t *enp,
1353 __in_bcount(size) caddr_t data,
1356 extern __checkReturn efx_rc_t
1358 __in efx_nic_t *enp,
1359 __in_bcount(size) caddr_t data,
1361 __inout efx_vpd_value_t *evvp);
1363 extern __checkReturn efx_rc_t
1365 __in efx_nic_t *enp,
1366 __inout_bcount(size) caddr_t data,
1368 __in efx_vpd_value_t *evvp);
1370 extern __checkReturn efx_rc_t
1372 __in efx_nic_t *enp,
1373 __inout_bcount(size) caddr_t data,
1375 __out efx_vpd_value_t *evvp,
1376 __inout unsigned int *contp);
1378 extern __checkReturn efx_rc_t
1380 __in efx_nic_t *enp,
1381 __in_bcount(size) caddr_t data,
1386 __in efx_nic_t *enp);
1388 #endif /* EFSYS_OPT_VPD */
1394 typedef enum efx_nvram_type_e {
1395 EFX_NVRAM_INVALID = 0,
1397 EFX_NVRAM_BOOTROM_CFG,
1398 EFX_NVRAM_MC_FIRMWARE,
1399 EFX_NVRAM_MC_GOLDEN,
1405 EFX_NVRAM_FPGA_BACKUP,
1406 EFX_NVRAM_DYNAMIC_CFG,
1409 EFX_NVRAM_MUM_FIRMWARE,
1413 extern __checkReturn efx_rc_t
1415 __in efx_nic_t *enp);
1419 extern __checkReturn efx_rc_t
1421 __in efx_nic_t *enp);
1423 #endif /* EFSYS_OPT_DIAG */
1425 extern __checkReturn efx_rc_t
1427 __in efx_nic_t *enp,
1428 __in efx_nvram_type_t type,
1429 __out size_t *sizep);
1431 extern __checkReturn efx_rc_t
1433 __in efx_nic_t *enp,
1434 __in efx_nvram_type_t type,
1435 __out_opt size_t *pref_chunkp);
1437 extern __checkReturn efx_rc_t
1438 efx_nvram_rw_finish(
1439 __in efx_nic_t *enp,
1440 __in efx_nvram_type_t type,
1441 __out_opt uint32_t *verify_resultp);
1443 extern __checkReturn efx_rc_t
1444 efx_nvram_get_version(
1445 __in efx_nic_t *enp,
1446 __in efx_nvram_type_t type,
1447 __out uint32_t *subtypep,
1448 __out_ecount(4) uint16_t version[4]);
1450 extern __checkReturn efx_rc_t
1451 efx_nvram_read_chunk(
1452 __in efx_nic_t *enp,
1453 __in efx_nvram_type_t type,
1454 __in unsigned int offset,
1455 __out_bcount(size) caddr_t data,
1458 extern __checkReturn efx_rc_t
1459 efx_nvram_read_backup(
1460 __in efx_nic_t *enp,
1461 __in efx_nvram_type_t type,
1462 __in unsigned int offset,
1463 __out_bcount(size) caddr_t data,
1466 extern __checkReturn efx_rc_t
1467 efx_nvram_set_version(
1468 __in efx_nic_t *enp,
1469 __in efx_nvram_type_t type,
1470 __in_ecount(4) uint16_t version[4]);
1472 extern __checkReturn efx_rc_t
1474 __in efx_nic_t *enp,
1475 __in efx_nvram_type_t type,
1476 __in_bcount(partn_size) caddr_t partn_data,
1477 __in size_t partn_size);
1479 extern __checkReturn efx_rc_t
1481 __in efx_nic_t *enp,
1482 __in efx_nvram_type_t type);
1484 extern __checkReturn efx_rc_t
1485 efx_nvram_write_chunk(
1486 __in efx_nic_t *enp,
1487 __in efx_nvram_type_t type,
1488 __in unsigned int offset,
1489 __in_bcount(size) caddr_t data,
1494 __in efx_nic_t *enp);
1496 #endif /* EFSYS_OPT_NVRAM */
1498 #if EFSYS_OPT_BOOTCFG
1500 /* Report size and offset of bootcfg sector in NVRAM partition. */
1501 extern __checkReturn efx_rc_t
1502 efx_bootcfg_sector_info(
1503 __in efx_nic_t *enp,
1505 __out_opt uint32_t *sector_countp,
1506 __out size_t *offsetp,
1507 __out size_t *max_sizep);
1510 * Copy bootcfg sector data to a target buffer which may differ in size.
1511 * Optionally corrects format errors in source buffer.
1514 efx_bootcfg_copy_sector(
1515 __in efx_nic_t *enp,
1516 __inout_bcount(sector_length)
1518 __in size_t sector_length,
1519 __out_bcount(data_size) uint8_t *data,
1520 __in size_t data_size,
1521 __in boolean_t handle_format_errors);
1525 __in efx_nic_t *enp,
1526 __out_bcount(size) uint8_t *data,
1531 __in efx_nic_t *enp,
1532 __in_bcount(size) uint8_t *data,
1535 #endif /* EFSYS_OPT_BOOTCFG */
1539 typedef enum efx_pattern_type_t {
1540 EFX_PATTERN_BYTE_INCREMENT = 0,
1541 EFX_PATTERN_ALL_THE_SAME,
1542 EFX_PATTERN_BIT_ALTERNATE,
1543 EFX_PATTERN_BYTE_ALTERNATE,
1544 EFX_PATTERN_BYTE_CHANGING,
1545 EFX_PATTERN_BIT_SWEEP,
1547 } efx_pattern_type_t;
1550 (*efx_sram_pattern_fn_t)(
1552 __in boolean_t negate,
1553 __out efx_qword_t *eqp);
1555 extern __checkReturn efx_rc_t
1557 __in efx_nic_t *enp,
1558 __in efx_pattern_type_t type);
1560 #endif /* EFSYS_OPT_DIAG */
1562 extern __checkReturn efx_rc_t
1563 efx_sram_buf_tbl_set(
1564 __in efx_nic_t *enp,
1566 __in efsys_mem_t *esmp,
1570 efx_sram_buf_tbl_clear(
1571 __in efx_nic_t *enp,
1575 #define EFX_BUF_TBL_SIZE 0x20000
1577 #define EFX_BUF_SIZE 4096
1581 typedef struct efx_evq_s efx_evq_t;
1583 #if EFSYS_OPT_QSTATS
1585 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1586 typedef enum efx_ev_qstat_e {
1592 EV_RX_PAUSE_FRM_ERR,
1593 EV_RX_BUF_OWNER_ID_ERR,
1594 EV_RX_IPV4_HDR_CHKSUM_ERR,
1595 EV_RX_TCP_UDP_CHKSUM_ERR,
1599 EV_RX_MCAST_HASH_MATCH,
1616 EV_DRIVER_SRM_UPD_DONE,
1617 EV_DRIVER_TX_DESCQ_FLS_DONE,
1618 EV_DRIVER_RX_DESCQ_FLS_DONE,
1619 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1620 EV_DRIVER_RX_DSC_ERROR,
1621 EV_DRIVER_TX_DSC_ERROR,
1627 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1629 #endif /* EFSYS_OPT_QSTATS */
1631 extern __checkReturn efx_rc_t
1633 __in efx_nic_t *enp);
1637 __in efx_nic_t *enp);
1639 #define EFX_EVQ_MAXNEVS 32768
1640 #define EFX_EVQ_MINNEVS 512
1642 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1643 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1645 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1646 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1647 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1648 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1650 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1651 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1652 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1654 extern __checkReturn efx_rc_t
1656 __in efx_nic_t *enp,
1657 __in unsigned int index,
1658 __in efsys_mem_t *esmp,
1662 __in uint32_t flags,
1663 __deref_out efx_evq_t **eepp);
1667 __in efx_evq_t *eep,
1668 __in uint16_t data);
1670 typedef __checkReturn boolean_t
1671 (*efx_initialized_ev_t)(
1672 __in_opt void *arg);
1674 #define EFX_PKT_UNICAST 0x0004
1675 #define EFX_PKT_START 0x0008
1677 #define EFX_PKT_VLAN_TAGGED 0x0010
1678 #define EFX_CKSUM_TCPUDP 0x0020
1679 #define EFX_CKSUM_IPV4 0x0040
1680 #define EFX_PKT_CONT 0x0080
1682 #define EFX_CHECK_VLAN 0x0100
1683 #define EFX_PKT_TCP 0x0200
1684 #define EFX_PKT_UDP 0x0400
1685 #define EFX_PKT_IPV4 0x0800
1687 #define EFX_PKT_IPV6 0x1000
1688 #define EFX_PKT_PREFIX_LEN 0x2000
1689 #define EFX_ADDR_MISMATCH 0x4000
1690 #define EFX_DISCARD 0x8000
1693 * The following flags are used only for packed stream
1694 * mode. The values for the flags are reused to fit into 16 bit,
1695 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1696 * packed stream mode
1698 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1699 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1702 #define EFX_EV_RX_NLABELS 32
1703 #define EFX_EV_TX_NLABELS 32
1705 typedef __checkReturn boolean_t
1708 __in uint32_t label,
1711 __in uint16_t flags);
1713 #if EFSYS_OPT_RX_PACKED_STREAM
1716 * Packed stream mode is documented in SF-112241-TC.
1717 * The general idea is that, instead of putting each incoming
1718 * packet into a separate buffer which is specified in a RX
1719 * descriptor, a large buffer is provided to the hardware and
1720 * packets are put there in a continuous stream.
1721 * The main advantage of such an approach is that RX queue refilling
1722 * happens much less frequently.
1725 typedef __checkReturn boolean_t
1728 __in uint32_t label,
1730 __in uint32_t pkt_count,
1731 __in uint16_t flags);
1735 typedef __checkReturn boolean_t
1738 __in uint32_t label,
1741 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1742 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1743 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1744 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1745 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1746 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1747 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1748 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1749 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1751 typedef __checkReturn boolean_t
1752 (*efx_exception_ev_t)(
1754 __in uint32_t label,
1755 __in uint32_t data);
1757 typedef __checkReturn boolean_t
1758 (*efx_rxq_flush_done_ev_t)(
1760 __in uint32_t rxq_index);
1762 typedef __checkReturn boolean_t
1763 (*efx_rxq_flush_failed_ev_t)(
1765 __in uint32_t rxq_index);
1767 typedef __checkReturn boolean_t
1768 (*efx_txq_flush_done_ev_t)(
1770 __in uint32_t txq_index);
1772 typedef __checkReturn boolean_t
1773 (*efx_software_ev_t)(
1775 __in uint16_t magic);
1777 typedef __checkReturn boolean_t
1780 __in uint32_t code);
1782 #define EFX_SRAM_CLEAR 0
1783 #define EFX_SRAM_UPDATE 1
1784 #define EFX_SRAM_ILLEGAL_CLEAR 2
1786 typedef __checkReturn boolean_t
1787 (*efx_wake_up_ev_t)(
1789 __in uint32_t label);
1791 typedef __checkReturn boolean_t
1794 __in uint32_t label);
1796 typedef __checkReturn boolean_t
1797 (*efx_link_change_ev_t)(
1799 __in efx_link_mode_t link_mode);
1801 #if EFSYS_OPT_MON_STATS
1803 typedef __checkReturn boolean_t
1804 (*efx_monitor_ev_t)(
1806 __in efx_mon_stat_t id,
1807 __in efx_mon_stat_value_t value);
1809 #endif /* EFSYS_OPT_MON_STATS */
1811 #if EFSYS_OPT_MAC_STATS
1813 typedef __checkReturn boolean_t
1814 (*efx_mac_stats_ev_t)(
1816 __in uint32_t generation);
1818 #endif /* EFSYS_OPT_MAC_STATS */
1820 typedef struct efx_ev_callbacks_s {
1821 efx_initialized_ev_t eec_initialized;
1823 #if EFSYS_OPT_RX_PACKED_STREAM
1824 efx_rx_ps_ev_t eec_rx_ps;
1827 efx_exception_ev_t eec_exception;
1828 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1829 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1830 efx_txq_flush_done_ev_t eec_txq_flush_done;
1831 efx_software_ev_t eec_software;
1832 efx_sram_ev_t eec_sram;
1833 efx_wake_up_ev_t eec_wake_up;
1834 efx_timer_ev_t eec_timer;
1835 efx_link_change_ev_t eec_link_change;
1836 #if EFSYS_OPT_MON_STATS
1837 efx_monitor_ev_t eec_monitor;
1838 #endif /* EFSYS_OPT_MON_STATS */
1839 #if EFSYS_OPT_MAC_STATS
1840 efx_mac_stats_ev_t eec_mac_stats;
1841 #endif /* EFSYS_OPT_MAC_STATS */
1842 } efx_ev_callbacks_t;
1844 extern __checkReturn boolean_t
1846 __in efx_evq_t *eep,
1847 __in unsigned int count);
1849 #if EFSYS_OPT_EV_PREFETCH
1853 __in efx_evq_t *eep,
1854 __in unsigned int count);
1856 #endif /* EFSYS_OPT_EV_PREFETCH */
1860 __in efx_evq_t *eep,
1861 __inout unsigned int *countp,
1862 __in const efx_ev_callbacks_t *eecp,
1863 __in_opt void *arg);
1865 extern __checkReturn efx_rc_t
1866 efx_ev_usecs_to_ticks(
1867 __in efx_nic_t *enp,
1868 __in unsigned int usecs,
1869 __out unsigned int *ticksp);
1871 extern __checkReturn efx_rc_t
1873 __in efx_evq_t *eep,
1874 __in unsigned int us);
1876 extern __checkReturn efx_rc_t
1878 __in efx_evq_t *eep,
1879 __in unsigned int count);
1881 #if EFSYS_OPT_QSTATS
1887 __in efx_nic_t *enp,
1888 __in unsigned int id);
1890 #endif /* EFSYS_OPT_NAMES */
1893 efx_ev_qstats_update(
1894 __in efx_evq_t *eep,
1895 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1897 #endif /* EFSYS_OPT_QSTATS */
1901 __in efx_evq_t *eep);
1905 extern __checkReturn efx_rc_t
1907 __inout efx_nic_t *enp);
1911 __in efx_nic_t *enp);
1913 #if EFSYS_OPT_RX_SCATTER
1914 __checkReturn efx_rc_t
1915 efx_rx_scatter_enable(
1916 __in efx_nic_t *enp,
1917 __in unsigned int buf_size);
1918 #endif /* EFSYS_OPT_RX_SCATTER */
1920 /* Handle to represent use of the default RSS context. */
1921 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1923 #if EFSYS_OPT_RX_SCALE
1925 typedef enum efx_rx_hash_alg_e {
1926 EFX_RX_HASHALG_LFSR = 0,
1927 EFX_RX_HASHALG_TOEPLITZ
1928 } efx_rx_hash_alg_t;
1930 #define EFX_RX_HASH_IPV4 (1U << 0)
1931 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1932 #define EFX_RX_HASH_IPV6 (1U << 2)
1933 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1935 typedef unsigned int efx_rx_hash_type_t;
1937 typedef enum efx_rx_hash_support_e {
1938 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1939 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1940 } efx_rx_hash_support_t;
1942 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1943 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1944 #define EFX_MAXRSS 64 /* RX indirection entry range */
1945 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1947 typedef enum efx_rx_scale_context_type_e {
1948 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1949 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1950 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1951 } efx_rx_scale_context_type_t;
1953 extern __checkReturn efx_rc_t
1954 efx_rx_hash_default_support_get(
1955 __in efx_nic_t *enp,
1956 __out efx_rx_hash_support_t *supportp);
1959 extern __checkReturn efx_rc_t
1960 efx_rx_scale_default_support_get(
1961 __in efx_nic_t *enp,
1962 __out efx_rx_scale_context_type_t *typep);
1964 extern __checkReturn efx_rc_t
1965 efx_rx_scale_context_alloc(
1966 __in efx_nic_t *enp,
1967 __in efx_rx_scale_context_type_t type,
1968 __in uint32_t num_queues,
1969 __out uint32_t *rss_contextp);
1971 extern __checkReturn efx_rc_t
1972 efx_rx_scale_context_free(
1973 __in efx_nic_t *enp,
1974 __in uint32_t rss_context);
1976 extern __checkReturn efx_rc_t
1977 efx_rx_scale_mode_set(
1978 __in efx_nic_t *enp,
1979 __in uint32_t rss_context,
1980 __in efx_rx_hash_alg_t alg,
1981 __in efx_rx_hash_type_t type,
1982 __in boolean_t insert);
1984 extern __checkReturn efx_rc_t
1985 efx_rx_scale_tbl_set(
1986 __in efx_nic_t *enp,
1987 __in uint32_t rss_context,
1988 __in_ecount(n) unsigned int *table,
1991 extern __checkReturn efx_rc_t
1992 efx_rx_scale_key_set(
1993 __in efx_nic_t *enp,
1994 __in uint32_t rss_context,
1995 __in_ecount(n) uint8_t *key,
1998 extern __checkReturn uint32_t
1999 efx_pseudo_hdr_hash_get(
2000 __in efx_rxq_t *erp,
2001 __in efx_rx_hash_alg_t func,
2002 __in uint8_t *buffer);
2004 #endif /* EFSYS_OPT_RX_SCALE */
2006 extern __checkReturn efx_rc_t
2007 efx_pseudo_hdr_pkt_length_get(
2008 __in efx_rxq_t *erp,
2009 __in uint8_t *buffer,
2010 __out uint16_t *pkt_lengthp);
2012 #define EFX_RXQ_MAXNDESCS 4096
2013 #define EFX_RXQ_MINNDESCS 512
2015 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2016 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2017 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2018 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2020 typedef enum efx_rxq_type_e {
2021 EFX_RXQ_TYPE_DEFAULT,
2022 EFX_RXQ_TYPE_PACKED_STREAM,
2027 * Dummy flag to be used instead of 0 to make it clear that the argument
2028 * is receive queue flags.
2030 #define EFX_RXQ_FLAG_NONE 0x0
2031 #define EFX_RXQ_FLAG_SCATTER 0x1
2033 * If tunnels are supported and Rx event can provide information about
2034 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2035 * full-feature firmware variant running), outer classes are requested by
2036 * default. However, if the driver supports tunnels, the flag allows to
2037 * request inner classes which are required to be able to interpret inner
2038 * Rx checksum offload results.
2040 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2042 extern __checkReturn efx_rc_t
2044 __in efx_nic_t *enp,
2045 __in unsigned int index,
2046 __in unsigned int label,
2047 __in efx_rxq_type_t type,
2048 __in efsys_mem_t *esmp,
2051 __in unsigned int flags,
2052 __in efx_evq_t *eep,
2053 __deref_out efx_rxq_t **erpp);
2055 #if EFSYS_OPT_RX_PACKED_STREAM
2057 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2058 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2059 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2060 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2061 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2063 extern __checkReturn efx_rc_t
2064 efx_rx_qcreate_packed_stream(
2065 __in efx_nic_t *enp,
2066 __in unsigned int index,
2067 __in unsigned int label,
2068 __in uint32_t ps_buf_size,
2069 __in efsys_mem_t *esmp,
2071 __in efx_evq_t *eep,
2072 __deref_out efx_rxq_t **erpp);
2076 typedef struct efx_buffer_s {
2077 efsys_dma_addr_t eb_addr;
2082 typedef struct efx_desc_s {
2088 __in efx_rxq_t *erp,
2089 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2091 __in unsigned int ndescs,
2092 __in unsigned int completed,
2093 __in unsigned int added);
2097 __in efx_rxq_t *erp,
2098 __in unsigned int added,
2099 __inout unsigned int *pushedp);
2101 #if EFSYS_OPT_RX_PACKED_STREAM
2104 efx_rx_qpush_ps_credits(
2105 __in efx_rxq_t *erp);
2107 extern __checkReturn uint8_t *
2108 efx_rx_qps_packet_info(
2109 __in efx_rxq_t *erp,
2110 __in uint8_t *buffer,
2111 __in uint32_t buffer_length,
2112 __in uint32_t current_offset,
2113 __out uint16_t *lengthp,
2114 __out uint32_t *next_offsetp,
2115 __out uint32_t *timestamp);
2118 extern __checkReturn efx_rc_t
2120 __in efx_rxq_t *erp);
2124 __in efx_rxq_t *erp);
2128 __in efx_rxq_t *erp);
2132 typedef struct efx_txq_s efx_txq_t;
2134 #if EFSYS_OPT_QSTATS
2136 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2137 typedef enum efx_tx_qstat_e {
2143 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2145 #endif /* EFSYS_OPT_QSTATS */
2147 extern __checkReturn efx_rc_t
2149 __in efx_nic_t *enp);
2153 __in efx_nic_t *enp);
2155 #define EFX_TXQ_MINNDESCS 512
2157 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2158 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2159 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2161 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2163 #define EFX_TXQ_CKSUM_IPV4 0x0001
2164 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2165 #define EFX_TXQ_FATSOV2 0x0004
2166 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2167 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2169 extern __checkReturn efx_rc_t
2171 __in efx_nic_t *enp,
2172 __in unsigned int index,
2173 __in unsigned int label,
2174 __in efsys_mem_t *esmp,
2177 __in uint16_t flags,
2178 __in efx_evq_t *eep,
2179 __deref_out efx_txq_t **etpp,
2180 __out unsigned int *addedp);
2182 extern __checkReturn efx_rc_t
2184 __in efx_txq_t *etp,
2185 __in_ecount(ndescs) efx_buffer_t *eb,
2186 __in unsigned int ndescs,
2187 __in unsigned int completed,
2188 __inout unsigned int *addedp);
2190 extern __checkReturn efx_rc_t
2192 __in efx_txq_t *etp,
2193 __in unsigned int ns);
2197 __in efx_txq_t *etp,
2198 __in unsigned int added,
2199 __in unsigned int pushed);
2201 extern __checkReturn efx_rc_t
2203 __in efx_txq_t *etp);
2207 __in efx_txq_t *etp);
2209 extern __checkReturn efx_rc_t
2211 __in efx_txq_t *etp);
2214 efx_tx_qpio_disable(
2215 __in efx_txq_t *etp);
2217 extern __checkReturn efx_rc_t
2219 __in efx_txq_t *etp,
2220 __in_ecount(buf_length) uint8_t *buffer,
2221 __in size_t buf_length,
2222 __in size_t pio_buf_offset);
2224 extern __checkReturn efx_rc_t
2226 __in efx_txq_t *etp,
2227 __in size_t pkt_length,
2228 __in unsigned int completed,
2229 __inout unsigned int *addedp);
2231 extern __checkReturn efx_rc_t
2233 __in efx_txq_t *etp,
2234 __in_ecount(n) efx_desc_t *ed,
2235 __in unsigned int n,
2236 __in unsigned int completed,
2237 __inout unsigned int *addedp);
2240 efx_tx_qdesc_dma_create(
2241 __in efx_txq_t *etp,
2242 __in efsys_dma_addr_t addr,
2245 __out efx_desc_t *edp);
2248 efx_tx_qdesc_tso_create(
2249 __in efx_txq_t *etp,
2250 __in uint16_t ipv4_id,
2251 __in uint32_t tcp_seq,
2252 __in uint8_t tcp_flags,
2253 __out efx_desc_t *edp);
2255 /* Number of FATSOv2 option descriptors */
2256 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2258 /* Maximum number of DMA segments per TSO packet (not superframe) */
2259 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2262 efx_tx_qdesc_tso2_create(
2263 __in efx_txq_t *etp,
2264 __in uint16_t ipv4_id,
2265 __in uint32_t tcp_seq,
2266 __in uint16_t tcp_mss,
2267 __out_ecount(count) efx_desc_t *edp,
2271 efx_tx_qdesc_vlantci_create(
2272 __in efx_txq_t *etp,
2274 __out efx_desc_t *edp);
2277 efx_tx_qdesc_checksum_create(
2278 __in efx_txq_t *etp,
2279 __in uint16_t flags,
2280 __out efx_desc_t *edp);
2282 #if EFSYS_OPT_QSTATS
2288 __in efx_nic_t *etp,
2289 __in unsigned int id);
2291 #endif /* EFSYS_OPT_NAMES */
2294 efx_tx_qstats_update(
2295 __in efx_txq_t *etp,
2296 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2298 #endif /* EFSYS_OPT_QSTATS */
2302 __in efx_txq_t *etp);
2307 #if EFSYS_OPT_FILTER
2309 #define EFX_ETHER_TYPE_IPV4 0x0800
2310 #define EFX_ETHER_TYPE_IPV6 0x86DD
2312 #define EFX_IPPROTO_TCP 6
2313 #define EFX_IPPROTO_UDP 17
2314 #define EFX_IPPROTO_GRE 47
2316 /* Use RSS to spread across multiple queues */
2317 #define EFX_FILTER_FLAG_RX_RSS 0x01
2318 /* Enable RX scatter */
2319 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2321 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2322 * May only be set by the filter implementation for each type.
2323 * A removal request will restore the automatic filter in its place.
2325 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2326 /* Filter is for RX */
2327 #define EFX_FILTER_FLAG_RX 0x08
2328 /* Filter is for TX */
2329 #define EFX_FILTER_FLAG_TX 0x10
2331 typedef uint8_t efx_filter_flags_t;
2334 * Flags which specify the fields to match on. The values are the same as in the
2335 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2338 /* Match by remote IP host address */
2339 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2340 /* Match by local IP host address */
2341 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2342 /* Match by remote MAC address */
2343 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2344 /* Match by remote TCP/UDP port */
2345 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2346 /* Match by remote TCP/UDP port */
2347 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2348 /* Match by local TCP/UDP port */
2349 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2350 /* Match by Ether-type */
2351 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2352 /* Match by inner VLAN ID */
2353 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2354 /* Match by outer VLAN ID */
2355 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2356 /* Match by IP transport protocol */
2357 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2358 /* For encapsulated packets, match all multicast inner frames */
2359 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2360 /* For encapsulated packets, match all unicast inner frames */
2361 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2362 /* Match otherwise-unmatched multicast and broadcast packets */
2363 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2364 /* Match otherwise-unmatched unicast packets */
2365 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2367 typedef uint32_t efx_filter_match_flags_t;
2369 typedef enum efx_filter_priority_s {
2370 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2371 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2372 * address list or hardware
2373 * requirements. This may only be used
2374 * by the filter implementation for
2376 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2377 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2378 * client (e.g. SR-IOV, HyperV VMQ etc.)
2380 } efx_filter_priority_t;
2383 * FIXME: All these fields are assumed to be in little-endian byte order.
2384 * It may be better for some to be big-endian. See bug42804.
2387 typedef struct efx_filter_spec_s {
2388 efx_filter_match_flags_t efs_match_flags;
2389 uint8_t efs_priority;
2390 efx_filter_flags_t efs_flags;
2391 uint16_t efs_dmaq_id;
2392 uint32_t efs_rss_context;
2393 uint16_t efs_outer_vid;
2394 uint16_t efs_inner_vid;
2395 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2396 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2397 uint16_t efs_ether_type;
2398 uint8_t efs_ip_proto;
2399 efx_tunnel_protocol_t efs_encap_type;
2400 uint16_t efs_loc_port;
2401 uint16_t efs_rem_port;
2402 efx_oword_t efs_rem_host;
2403 efx_oword_t efs_loc_host;
2404 } efx_filter_spec_t;
2407 /* Default values for use in filter specifications */
2408 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2409 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2411 extern __checkReturn efx_rc_t
2413 __in efx_nic_t *enp);
2417 __in efx_nic_t *enp);
2419 extern __checkReturn efx_rc_t
2421 __in efx_nic_t *enp,
2422 __inout efx_filter_spec_t *spec);
2424 extern __checkReturn efx_rc_t
2426 __in efx_nic_t *enp,
2427 __inout efx_filter_spec_t *spec);
2429 extern __checkReturn efx_rc_t
2431 __in efx_nic_t *enp);
2433 extern __checkReturn efx_rc_t
2434 efx_filter_supported_filters(
2435 __in efx_nic_t *enp,
2436 __out_ecount(buffer_length) uint32_t *buffer,
2437 __in size_t buffer_length,
2438 __out size_t *list_lengthp);
2441 efx_filter_spec_init_rx(
2442 __out efx_filter_spec_t *spec,
2443 __in efx_filter_priority_t priority,
2444 __in efx_filter_flags_t flags,
2445 __in efx_rxq_t *erp);
2448 efx_filter_spec_init_tx(
2449 __out efx_filter_spec_t *spec,
2450 __in efx_txq_t *etp);
2452 extern __checkReturn efx_rc_t
2453 efx_filter_spec_set_ipv4_local(
2454 __inout efx_filter_spec_t *spec,
2457 __in uint16_t port);
2459 extern __checkReturn efx_rc_t
2460 efx_filter_spec_set_ipv4_full(
2461 __inout efx_filter_spec_t *spec,
2463 __in uint32_t lhost,
2464 __in uint16_t lport,
2465 __in uint32_t rhost,
2466 __in uint16_t rport);
2468 extern __checkReturn efx_rc_t
2469 efx_filter_spec_set_eth_local(
2470 __inout efx_filter_spec_t *spec,
2472 __in const uint8_t *addr);
2475 efx_filter_spec_set_ether_type(
2476 __inout efx_filter_spec_t *spec,
2477 __in uint16_t ether_type);
2479 extern __checkReturn efx_rc_t
2480 efx_filter_spec_set_uc_def(
2481 __inout efx_filter_spec_t *spec);
2483 extern __checkReturn efx_rc_t
2484 efx_filter_spec_set_mc_def(
2485 __inout efx_filter_spec_t *spec);
2487 typedef enum efx_filter_inner_frame_match_e {
2488 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2489 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2490 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2491 } efx_filter_inner_frame_match_t;
2493 extern __checkReturn efx_rc_t
2494 efx_filter_spec_set_encap_type(
2495 __inout efx_filter_spec_t *spec,
2496 __in efx_tunnel_protocol_t encap_type,
2497 __in efx_filter_inner_frame_match_t inner_frame_match);
2499 #if EFSYS_OPT_RX_SCALE
2500 extern __checkReturn efx_rc_t
2501 efx_filter_spec_set_rss_context(
2502 __inout efx_filter_spec_t *spec,
2503 __in uint32_t rss_context);
2505 #endif /* EFSYS_OPT_FILTER */
2509 extern __checkReturn uint32_t
2511 __in_ecount(count) uint32_t const *input,
2513 __in uint32_t init);
2515 extern __checkReturn uint32_t
2517 __in_ecount(length) uint8_t const *input,
2519 __in uint32_t init);
2521 #if EFSYS_OPT_LICENSING
2525 typedef struct efx_key_stats_s {
2527 uint32_t eks_invalid;
2528 uint32_t eks_blacklisted;
2529 uint32_t eks_unverifiable;
2530 uint32_t eks_wrong_node;
2531 uint32_t eks_licensed_apps_lo;
2532 uint32_t eks_licensed_apps_hi;
2533 uint32_t eks_licensed_features_lo;
2534 uint32_t eks_licensed_features_hi;
2537 extern __checkReturn efx_rc_t
2539 __in efx_nic_t *enp);
2543 __in efx_nic_t *enp);
2545 extern __checkReturn boolean_t
2546 efx_lic_check_support(
2547 __in efx_nic_t *enp);
2549 extern __checkReturn efx_rc_t
2550 efx_lic_update_licenses(
2551 __in efx_nic_t *enp);
2553 extern __checkReturn efx_rc_t
2554 efx_lic_get_key_stats(
2555 __in efx_nic_t *enp,
2556 __out efx_key_stats_t *ksp);
2558 extern __checkReturn efx_rc_t
2560 __in efx_nic_t *enp,
2561 __in uint64_t app_id,
2562 __out boolean_t *licensedp);
2564 extern __checkReturn efx_rc_t
2566 __in efx_nic_t *enp,
2567 __in size_t buffer_size,
2568 __out uint32_t *typep,
2569 __out size_t *lengthp,
2570 __out_opt uint8_t *bufferp);
2573 extern __checkReturn efx_rc_t
2575 __in efx_nic_t *enp,
2576 __in_bcount(buffer_size)
2578 __in size_t buffer_size,
2579 __out uint32_t *startp);
2581 extern __checkReturn efx_rc_t
2583 __in efx_nic_t *enp,
2584 __in_bcount(buffer_size)
2586 __in size_t buffer_size,
2587 __in uint32_t offset,
2588 __out uint32_t *endp);
2590 extern __checkReturn __success(return != B_FALSE) boolean_t
2592 __in efx_nic_t *enp,
2593 __in_bcount(buffer_size)
2595 __in size_t buffer_size,
2596 __in uint32_t offset,
2597 __out uint32_t *startp,
2598 __out uint32_t *lengthp);
2600 extern __checkReturn __success(return != B_FALSE) boolean_t
2601 efx_lic_validate_key(
2602 __in efx_nic_t *enp,
2603 __in_bcount(length) caddr_t keyp,
2604 __in uint32_t length);
2606 extern __checkReturn efx_rc_t
2608 __in efx_nic_t *enp,
2609 __in_bcount(buffer_size)
2611 __in size_t buffer_size,
2612 __in uint32_t offset,
2613 __in uint32_t length,
2614 __out_bcount_part(key_max_size, *lengthp)
2616 __in size_t key_max_size,
2617 __out uint32_t *lengthp);
2619 extern __checkReturn efx_rc_t
2621 __in efx_nic_t *enp,
2622 __in_bcount(buffer_size)
2624 __in size_t buffer_size,
2625 __in uint32_t offset,
2626 __in_bcount(length) caddr_t keyp,
2627 __in uint32_t length,
2628 __out uint32_t *lengthp);
2630 __checkReturn efx_rc_t
2632 __in efx_nic_t *enp,
2633 __in_bcount(buffer_size)
2635 __in size_t buffer_size,
2636 __in uint32_t offset,
2637 __in uint32_t length,
2639 __out uint32_t *deltap);
2641 extern __checkReturn efx_rc_t
2642 efx_lic_create_partition(
2643 __in efx_nic_t *enp,
2644 __in_bcount(buffer_size)
2646 __in size_t buffer_size);
2648 extern __checkReturn efx_rc_t
2649 efx_lic_finish_partition(
2650 __in efx_nic_t *enp,
2651 __in_bcount(buffer_size)
2653 __in size_t buffer_size);
2655 #endif /* EFSYS_OPT_LICENSING */
2659 #if EFSYS_OPT_TUNNEL
2661 extern __checkReturn efx_rc_t
2663 __in efx_nic_t *enp);
2667 __in efx_nic_t *enp);
2670 * For overlay network encapsulation using UDP, the firmware needs to know
2671 * the configured UDP port for the overlay so it can decode encapsulated
2673 * The UDP port/protocol list is global.
2676 extern __checkReturn efx_rc_t
2677 efx_tunnel_config_udp_add(
2678 __in efx_nic_t *enp,
2679 __in uint16_t port /* host/cpu-endian */,
2680 __in efx_tunnel_protocol_t protocol);
2682 extern __checkReturn efx_rc_t
2683 efx_tunnel_config_udp_remove(
2684 __in efx_nic_t *enp,
2685 __in uint16_t port /* host/cpu-endian */,
2686 __in efx_tunnel_protocol_t protocol);
2689 efx_tunnel_config_clear(
2690 __in efx_nic_t *enp);
2693 * Apply tunnel UDP ports configuration to hardware.
2695 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2698 extern __checkReturn efx_rc_t
2699 efx_tunnel_reconfigure(
2700 __in efx_nic_t *enp);
2702 #endif /* EFSYS_OPT_TUNNEL */
2709 #endif /* _SYS_EFX_H */