1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
15 static __checkReturn efx_rc_t
23 static __checkReturn efx_rc_t
27 static __checkReturn efx_rc_t
30 __inout efx_filter_spec_t *spec,
31 __in boolean_t may_replace);
33 static __checkReturn efx_rc_t
36 __inout efx_filter_spec_t *spec);
38 static __checkReturn efx_rc_t
39 siena_filter_supported_filters(
41 __out_ecount(buffer_length) uint32_t *buffer,
42 __in size_t buffer_length,
43 __out size_t *list_lengthp);
45 #endif /* EFSYS_OPT_SIENA */
48 static const efx_filter_ops_t __efx_filter_siena_ops = {
49 siena_filter_init, /* efo_init */
50 siena_filter_fini, /* efo_fini */
51 siena_filter_restore, /* efo_restore */
52 siena_filter_add, /* efo_add */
53 siena_filter_delete, /* efo_delete */
54 siena_filter_supported_filters, /* efo_supported_filters */
55 NULL, /* efo_reconfigure */
57 #endif /* EFSYS_OPT_SIENA */
59 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
60 static const efx_filter_ops_t __efx_filter_ef10_ops = {
61 ef10_filter_init, /* efo_init */
62 ef10_filter_fini, /* efo_fini */
63 ef10_filter_restore, /* efo_restore */
64 ef10_filter_add, /* efo_add */
65 ef10_filter_delete, /* efo_delete */
66 ef10_filter_supported_filters, /* efo_supported_filters */
67 ef10_filter_reconfigure, /* efo_reconfigure */
69 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
71 __checkReturn efx_rc_t
74 __inout efx_filter_spec_t *spec)
76 const efx_filter_ops_t *efop = enp->en_efop;
78 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
79 EFSYS_ASSERT3P(spec, !=, NULL);
80 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
82 return (efop->efo_add(enp, spec, B_FALSE));
85 __checkReturn efx_rc_t
88 __inout efx_filter_spec_t *spec)
90 const efx_filter_ops_t *efop = enp->en_efop;
92 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
93 EFSYS_ASSERT3P(spec, !=, NULL);
94 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
96 return (efop->efo_delete(enp, spec));
99 __checkReturn efx_rc_t
105 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
107 if ((rc = enp->en_efop->efo_restore(enp)) != 0)
113 EFSYS_PROBE1(fail1, efx_rc_t, rc);
118 __checkReturn efx_rc_t
122 const efx_filter_ops_t *efop;
125 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
126 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
127 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER));
129 switch (enp->en_family) {
131 case EFX_FAMILY_SIENA:
132 efop = &__efx_filter_siena_ops;
134 #endif /* EFSYS_OPT_SIENA */
136 #if EFSYS_OPT_HUNTINGTON
137 case EFX_FAMILY_HUNTINGTON:
138 efop = &__efx_filter_ef10_ops;
140 #endif /* EFSYS_OPT_HUNTINGTON */
142 #if EFSYS_OPT_MEDFORD
143 case EFX_FAMILY_MEDFORD:
144 efop = &__efx_filter_ef10_ops;
146 #endif /* EFSYS_OPT_MEDFORD */
148 #if EFSYS_OPT_MEDFORD2
149 case EFX_FAMILY_MEDFORD2:
150 efop = &__efx_filter_ef10_ops;
152 #endif /* EFSYS_OPT_MEDFORD2 */
160 if ((rc = efop->efo_init(enp)) != 0)
164 enp->en_mod_flags |= EFX_MOD_FILTER;
170 EFSYS_PROBE1(fail1, efx_rc_t, rc);
173 enp->en_mod_flags &= ~EFX_MOD_FILTER;
181 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
182 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
183 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
185 enp->en_efop->efo_fini(enp);
188 enp->en_mod_flags &= ~EFX_MOD_FILTER;
192 * Query the possible combinations of match flags which can be filtered on.
193 * These are returned as a list, of which each 32 bit element is a bitmask
194 * formed of EFX_FILTER_MATCH flags.
196 * The combinations are ordered in priority from highest to lowest.
198 * If the provided buffer is too short to hold the list, the call with fail with
199 * ENOSPC and *list_lengthp will be set to the buffer length required.
201 __checkReturn efx_rc_t
202 efx_filter_supported_filters(
204 __out_ecount(buffer_length) uint32_t *buffer,
205 __in size_t buffer_length,
206 __out size_t *list_lengthp)
210 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
211 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
212 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
213 EFSYS_ASSERT(enp->en_efop->efo_supported_filters != NULL);
215 if (buffer == NULL) {
220 rc = enp->en_efop->efo_supported_filters(enp, buffer, buffer_length,
230 EFSYS_PROBE1(fail1, efx_rc_t, rc);
235 __checkReturn efx_rc_t
236 efx_filter_reconfigure(
238 __in_ecount(6) uint8_t const *mac_addr,
239 __in boolean_t all_unicst,
240 __in boolean_t mulcst,
241 __in boolean_t all_mulcst,
242 __in boolean_t brdcst,
243 __in_ecount(6*count) uint8_t const *addrs,
248 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
249 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
250 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
252 if (enp->en_efop->efo_reconfigure != NULL) {
253 if ((rc = enp->en_efop->efo_reconfigure(enp, mac_addr,
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
269 efx_filter_spec_init_rx(
270 __out efx_filter_spec_t *spec,
271 __in efx_filter_priority_t priority,
272 __in efx_filter_flags_t flags,
275 EFSYS_ASSERT3P(spec, !=, NULL);
276 EFSYS_ASSERT3P(erp, !=, NULL);
277 EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
278 EFX_FILTER_FLAG_RX_SCATTER)) == 0);
280 memset(spec, 0, sizeof (*spec));
281 spec->efs_priority = priority;
282 spec->efs_flags = EFX_FILTER_FLAG_RX | flags;
283 spec->efs_rss_context = EFX_RSS_CONTEXT_DEFAULT;
284 spec->efs_dmaq_id = (uint16_t)erp->er_index;
288 efx_filter_spec_init_tx(
289 __out efx_filter_spec_t *spec,
292 EFSYS_ASSERT3P(spec, !=, NULL);
293 EFSYS_ASSERT3P(etp, !=, NULL);
295 memset(spec, 0, sizeof (*spec));
296 spec->efs_priority = EFX_FILTER_PRI_REQUIRED;
297 spec->efs_flags = EFX_FILTER_FLAG_TX;
298 spec->efs_dmaq_id = (uint16_t)etp->et_index;
303 * Specify IPv4 host, transport protocol and port in a filter specification
305 __checkReturn efx_rc_t
306 efx_filter_spec_set_ipv4_local(
307 __inout efx_filter_spec_t *spec,
312 EFSYS_ASSERT3P(spec, !=, NULL);
314 spec->efs_match_flags |=
315 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
316 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
317 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
318 spec->efs_ip_proto = proto;
319 spec->efs_loc_host.eo_u32[0] = host;
320 spec->efs_loc_port = port;
325 * Specify IPv4 hosts, transport protocol and ports in a filter specification
327 __checkReturn efx_rc_t
328 efx_filter_spec_set_ipv4_full(
329 __inout efx_filter_spec_t *spec,
336 EFSYS_ASSERT3P(spec, !=, NULL);
338 spec->efs_match_flags |=
339 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
340 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
341 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
342 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
343 spec->efs_ip_proto = proto;
344 spec->efs_loc_host.eo_u32[0] = lhost;
345 spec->efs_loc_port = lport;
346 spec->efs_rem_host.eo_u32[0] = rhost;
347 spec->efs_rem_port = rport;
352 * Specify local Ethernet address and/or VID in filter specification
354 __checkReturn efx_rc_t
355 efx_filter_spec_set_eth_local(
356 __inout efx_filter_spec_t *spec,
358 __in const uint8_t *addr)
360 EFSYS_ASSERT3P(spec, !=, NULL);
361 EFSYS_ASSERT3P(addr, !=, NULL);
363 if (vid == EFX_FILTER_SPEC_VID_UNSPEC && addr == NULL)
366 if (vid != EFX_FILTER_SPEC_VID_UNSPEC) {
367 spec->efs_match_flags |= EFX_FILTER_MATCH_OUTER_VID;
368 spec->efs_outer_vid = vid;
371 spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC;
372 memcpy(spec->efs_loc_mac, addr, EFX_MAC_ADDR_LEN);
378 efx_filter_spec_set_ether_type(
379 __inout efx_filter_spec_t *spec,
380 __in uint16_t ether_type)
382 EFSYS_ASSERT3P(spec, !=, NULL);
384 spec->efs_ether_type = ether_type;
385 spec->efs_match_flags |= EFX_FILTER_MATCH_ETHER_TYPE;
389 * Specify matching otherwise-unmatched unicast in a filter specification
391 __checkReturn efx_rc_t
392 efx_filter_spec_set_uc_def(
393 __inout efx_filter_spec_t *spec)
395 EFSYS_ASSERT3P(spec, !=, NULL);
397 spec->efs_match_flags |= EFX_FILTER_MATCH_UNKNOWN_UCAST_DST;
402 * Specify matching otherwise-unmatched multicast in a filter specification
404 __checkReturn efx_rc_t
405 efx_filter_spec_set_mc_def(
406 __inout efx_filter_spec_t *spec)
408 EFSYS_ASSERT3P(spec, !=, NULL);
410 spec->efs_match_flags |= EFX_FILTER_MATCH_UNKNOWN_MCAST_DST;
415 __checkReturn efx_rc_t
416 efx_filter_spec_set_encap_type(
417 __inout efx_filter_spec_t *spec,
418 __in efx_tunnel_protocol_t encap_type,
419 __in efx_filter_inner_frame_match_t inner_frame_match)
421 uint32_t match_flags = 0;
425 EFSYS_ASSERT3P(spec, !=, NULL);
427 switch (encap_type) {
428 case EFX_TUNNEL_PROTOCOL_VXLAN:
429 case EFX_TUNNEL_PROTOCOL_GENEVE:
430 ip_proto = EFX_IPPROTO_UDP;
432 case EFX_TUNNEL_PROTOCOL_NVGRE:
433 ip_proto = EFX_IPPROTO_GRE;
441 switch (inner_frame_match) {
442 case EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST:
443 match_flags |= EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST;
445 case EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST:
446 match_flags |= EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST;
448 case EFX_FILTER_INNER_FRAME_MATCH_OTHER:
449 /* This is for when specific inner frames are to be matched. */
457 spec->efs_encap_type = encap_type;
458 spec->efs_ip_proto = ip_proto;
459 spec->efs_match_flags |= (match_flags | EFX_FILTER_MATCH_IP_PROTO);
466 EFSYS_PROBE1(fail1, efx_rc_t, rc);
471 #if EFSYS_OPT_RX_SCALE
472 __checkReturn efx_rc_t
473 efx_filter_spec_set_rss_context(
474 __inout efx_filter_spec_t *spec,
475 __in uint32_t rss_context)
479 EFSYS_ASSERT3P(spec, !=, NULL);
481 /* The filter must have been created with EFX_FILTER_FLAG_RX_RSS. */
482 if ((spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) == 0) {
487 spec->efs_rss_context = rss_context;
492 EFSYS_PROBE1(fail1, efx_rc_t, rc);
501 * "Fudge factors" - difference between programmed value and actual depth.
502 * Due to pipelined implementation we need to program H/W with a value that
503 * is larger than the hop limit we want.
505 #define FILTER_CTL_SRCH_FUDGE_WILD 3
506 #define FILTER_CTL_SRCH_FUDGE_FULL 1
509 * Hard maximum hop limit. Hardware will time-out beyond 200-something.
510 * We also need to avoid infinite loops in efx_filter_search() when the
513 #define FILTER_CTL_SRCH_MAX 200
515 static __checkReturn efx_rc_t
516 siena_filter_spec_from_gen_spec(
517 __out siena_filter_spec_t *sf_spec,
518 __in efx_filter_spec_t *gen_spec)
521 boolean_t is_full = B_FALSE;
523 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX)
524 EFSYS_ASSERT3U(gen_spec->efs_flags, ==, EFX_FILTER_FLAG_TX);
526 EFSYS_ASSERT3U(gen_spec->efs_flags, &, EFX_FILTER_FLAG_RX);
528 /* Siena only has one RSS context */
529 if ((gen_spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) &&
530 gen_spec->efs_rss_context != EFX_RSS_CONTEXT_DEFAULT) {
535 sf_spec->sfs_flags = gen_spec->efs_flags;
536 sf_spec->sfs_dmaq_id = gen_spec->efs_dmaq_id;
538 switch (gen_spec->efs_match_flags) {
539 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
540 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
541 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT:
544 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
545 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT: {
546 uint32_t rhost, host1, host2;
547 uint16_t rport, port1, port2;
549 if (gen_spec->efs_ether_type != EFX_ETHER_TYPE_IPV4) {
553 if (gen_spec->efs_loc_port == 0 ||
554 (is_full && gen_spec->efs_rem_port == 0)) {
558 switch (gen_spec->efs_ip_proto) {
559 case EFX_IPPROTO_TCP:
560 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
561 sf_spec->sfs_type = (is_full ?
562 EFX_SIENA_FILTER_TX_TCP_FULL :
563 EFX_SIENA_FILTER_TX_TCP_WILD);
565 sf_spec->sfs_type = (is_full ?
566 EFX_SIENA_FILTER_RX_TCP_FULL :
567 EFX_SIENA_FILTER_RX_TCP_WILD);
570 case EFX_IPPROTO_UDP:
571 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
572 sf_spec->sfs_type = (is_full ?
573 EFX_SIENA_FILTER_TX_UDP_FULL :
574 EFX_SIENA_FILTER_TX_UDP_WILD);
576 sf_spec->sfs_type = (is_full ?
577 EFX_SIENA_FILTER_RX_UDP_FULL :
578 EFX_SIENA_FILTER_RX_UDP_WILD);
586 * The filter is constructed in terms of source and destination,
587 * with the odd wrinkle that the ports are swapped in a UDP
588 * wildcard filter. We need to convert from local and remote
589 * addresses (zero for a wildcard).
591 rhost = is_full ? gen_spec->efs_rem_host.eo_u32[0] : 0;
592 rport = is_full ? gen_spec->efs_rem_port : 0;
593 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
594 host1 = gen_spec->efs_loc_host.eo_u32[0];
598 host2 = gen_spec->efs_loc_host.eo_u32[0];
600 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
601 if (sf_spec->sfs_type ==
602 EFX_SIENA_FILTER_TX_UDP_WILD) {
604 port2 = gen_spec->efs_loc_port;
606 port1 = gen_spec->efs_loc_port;
610 if (sf_spec->sfs_type ==
611 EFX_SIENA_FILTER_RX_UDP_WILD) {
612 port1 = gen_spec->efs_loc_port;
616 port2 = gen_spec->efs_loc_port;
619 sf_spec->sfs_dword[0] = (host1 << 16) | port1;
620 sf_spec->sfs_dword[1] = (port2 << 16) | (host1 >> 16);
621 sf_spec->sfs_dword[2] = host2;
625 case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
628 case EFX_FILTER_MATCH_LOC_MAC:
629 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
630 sf_spec->sfs_type = (is_full ?
631 EFX_SIENA_FILTER_TX_MAC_FULL :
632 EFX_SIENA_FILTER_TX_MAC_WILD);
634 sf_spec->sfs_type = (is_full ?
635 EFX_SIENA_FILTER_RX_MAC_FULL :
636 EFX_SIENA_FILTER_RX_MAC_WILD);
638 sf_spec->sfs_dword[0] = is_full ? gen_spec->efs_outer_vid : 0;
639 sf_spec->sfs_dword[1] =
640 gen_spec->efs_loc_mac[2] << 24 |
641 gen_spec->efs_loc_mac[3] << 16 |
642 gen_spec->efs_loc_mac[4] << 8 |
643 gen_spec->efs_loc_mac[5];
644 sf_spec->sfs_dword[2] =
645 gen_spec->efs_loc_mac[0] << 8 |
646 gen_spec->efs_loc_mac[1];
650 EFSYS_ASSERT(B_FALSE);
666 EFSYS_PROBE1(fail1, efx_rc_t, rc);
672 * The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
673 * key derived from the n-tuple.
676 siena_filter_tbl_hash(
681 /* First 16 rounds */
682 tmp = 0x1fff ^ (uint16_t)(key >> 16);
683 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
684 tmp = tmp ^ tmp >> 9;
687 tmp = tmp ^ tmp << 13 ^ (uint16_t)(key & 0xffff);
688 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
689 tmp = tmp ^ tmp >> 9;
695 * To allow for hash collisions, filter search continues at these
696 * increments from the first possible entry selected by the hash.
699 siena_filter_tbl_increment(
702 return ((uint16_t)(key * 2 - 1));
705 static __checkReturn boolean_t
706 siena_filter_test_used(
707 __in siena_filter_tbl_t *sftp,
708 __in unsigned int index)
710 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
711 return ((sftp->sft_bitmap[index / 32] & (1 << (index % 32))) != 0);
715 siena_filter_set_used(
716 __in siena_filter_tbl_t *sftp,
717 __in unsigned int index)
719 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
720 sftp->sft_bitmap[index / 32] |= (1 << (index % 32));
725 siena_filter_clear_used(
726 __in siena_filter_tbl_t *sftp,
727 __in unsigned int index)
729 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
730 sftp->sft_bitmap[index / 32] &= ~(1 << (index % 32));
733 EFSYS_ASSERT3U(sftp->sft_used, >=, 0);
737 static siena_filter_tbl_id_t
739 __in siena_filter_type_t type)
741 siena_filter_tbl_id_t tbl_id;
744 case EFX_SIENA_FILTER_RX_TCP_FULL:
745 case EFX_SIENA_FILTER_RX_TCP_WILD:
746 case EFX_SIENA_FILTER_RX_UDP_FULL:
747 case EFX_SIENA_FILTER_RX_UDP_WILD:
748 tbl_id = EFX_SIENA_FILTER_TBL_RX_IP;
751 case EFX_SIENA_FILTER_RX_MAC_FULL:
752 case EFX_SIENA_FILTER_RX_MAC_WILD:
753 tbl_id = EFX_SIENA_FILTER_TBL_RX_MAC;
756 case EFX_SIENA_FILTER_TX_TCP_FULL:
757 case EFX_SIENA_FILTER_TX_TCP_WILD:
758 case EFX_SIENA_FILTER_TX_UDP_FULL:
759 case EFX_SIENA_FILTER_TX_UDP_WILD:
760 tbl_id = EFX_SIENA_FILTER_TBL_TX_IP;
763 case EFX_SIENA_FILTER_TX_MAC_FULL:
764 case EFX_SIENA_FILTER_TX_MAC_WILD:
765 tbl_id = EFX_SIENA_FILTER_TBL_TX_MAC;
769 EFSYS_ASSERT(B_FALSE);
770 tbl_id = EFX_SIENA_FILTER_NTBLS;
777 siena_filter_reset_search_depth(
778 __inout siena_filter_t *sfp,
779 __in siena_filter_tbl_id_t tbl_id)
782 case EFX_SIENA_FILTER_TBL_RX_IP:
783 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] = 0;
784 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] = 0;
785 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] = 0;
786 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] = 0;
789 case EFX_SIENA_FILTER_TBL_RX_MAC:
790 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] = 0;
791 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] = 0;
794 case EFX_SIENA_FILTER_TBL_TX_IP:
795 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] = 0;
796 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] = 0;
797 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] = 0;
798 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] = 0;
801 case EFX_SIENA_FILTER_TBL_TX_MAC:
802 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] = 0;
803 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] = 0;
807 EFSYS_ASSERT(B_FALSE);
813 siena_filter_push_rx_limits(
816 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
819 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
821 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_FULL_SRCH_LIMIT,
822 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] +
823 FILTER_CTL_SRCH_FUDGE_FULL);
824 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_WILD_SRCH_LIMIT,
825 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] +
826 FILTER_CTL_SRCH_FUDGE_WILD);
827 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_FULL_SRCH_LIMIT,
828 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] +
829 FILTER_CTL_SRCH_FUDGE_FULL);
830 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_WILD_SRCH_LIMIT,
831 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] +
832 FILTER_CTL_SRCH_FUDGE_WILD);
834 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC].sft_size) {
835 EFX_SET_OWORD_FIELD(oword,
836 FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
837 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] +
838 FILTER_CTL_SRCH_FUDGE_FULL);
839 EFX_SET_OWORD_FIELD(oword,
840 FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
841 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] +
842 FILTER_CTL_SRCH_FUDGE_WILD);
845 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
849 siena_filter_push_tx_limits(
852 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
855 EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
857 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP].sft_size != 0) {
858 EFX_SET_OWORD_FIELD(oword,
859 FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE,
860 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] +
861 FILTER_CTL_SRCH_FUDGE_FULL);
862 EFX_SET_OWORD_FIELD(oword,
863 FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE,
864 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] +
865 FILTER_CTL_SRCH_FUDGE_WILD);
866 EFX_SET_OWORD_FIELD(oword,
867 FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE,
868 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] +
869 FILTER_CTL_SRCH_FUDGE_FULL);
870 EFX_SET_OWORD_FIELD(oword,
871 FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE,
872 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] +
873 FILTER_CTL_SRCH_FUDGE_WILD);
876 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC].sft_size != 0) {
878 oword, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
879 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] +
880 FILTER_CTL_SRCH_FUDGE_FULL);
882 oword, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
883 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] +
884 FILTER_CTL_SRCH_FUDGE_WILD);
887 EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
890 /* Build a filter entry and return its n-tuple key. */
891 static __checkReturn uint32_t
893 __out efx_oword_t *filter,
894 __in siena_filter_spec_t *spec)
898 uint8_t type = spec->sfs_type;
899 uint32_t flags = spec->sfs_flags;
901 switch (siena_filter_tbl_id(type)) {
902 case EFX_SIENA_FILTER_TBL_RX_IP: {
903 boolean_t is_udp = (type == EFX_SIENA_FILTER_RX_UDP_FULL ||
904 type == EFX_SIENA_FILTER_RX_UDP_WILD);
905 EFX_POPULATE_OWORD_7(*filter,
907 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
909 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
910 FRF_AZ_TCP_UDP, is_udp,
911 FRF_AZ_RXQ_ID, spec->sfs_dmaq_id,
912 EFX_DWORD_2, spec->sfs_dword[2],
913 EFX_DWORD_1, spec->sfs_dword[1],
914 EFX_DWORD_0, spec->sfs_dword[0]);
919 case EFX_SIENA_FILTER_TBL_RX_MAC: {
920 boolean_t is_wild = (type == EFX_SIENA_FILTER_RX_MAC_WILD);
921 EFX_POPULATE_OWORD_7(*filter,
923 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
924 FRF_CZ_RMFT_SCATTER_EN,
925 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
926 FRF_CZ_RMFT_RXQ_ID, spec->sfs_dmaq_id,
927 FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
928 FRF_CZ_RMFT_DEST_MAC_DW1, spec->sfs_dword[2],
929 FRF_CZ_RMFT_DEST_MAC_DW0, spec->sfs_dword[1],
930 FRF_CZ_RMFT_VLAN_ID, spec->sfs_dword[0]);
935 case EFX_SIENA_FILTER_TBL_TX_IP: {
936 boolean_t is_udp = (type == EFX_SIENA_FILTER_TX_UDP_FULL ||
937 type == EFX_SIENA_FILTER_TX_UDP_WILD);
938 EFX_POPULATE_OWORD_5(*filter,
939 FRF_CZ_TIFT_TCP_UDP, is_udp,
940 FRF_CZ_TIFT_TXQ_ID, spec->sfs_dmaq_id,
941 EFX_DWORD_2, spec->sfs_dword[2],
942 EFX_DWORD_1, spec->sfs_dword[1],
943 EFX_DWORD_0, spec->sfs_dword[0]);
944 dword3 = is_udp | spec->sfs_dmaq_id << 1;
948 case EFX_SIENA_FILTER_TBL_TX_MAC: {
949 boolean_t is_wild = (type == EFX_SIENA_FILTER_TX_MAC_WILD);
950 EFX_POPULATE_OWORD_5(*filter,
951 FRF_CZ_TMFT_TXQ_ID, spec->sfs_dmaq_id,
952 FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
953 FRF_CZ_TMFT_SRC_MAC_DW1, spec->sfs_dword[2],
954 FRF_CZ_TMFT_SRC_MAC_DW0, spec->sfs_dword[1],
955 FRF_CZ_TMFT_VLAN_ID, spec->sfs_dword[0]);
956 dword3 = is_wild | spec->sfs_dmaq_id << 1;
961 EFSYS_ASSERT(B_FALSE);
962 EFX_ZERO_OWORD(*filter);
975 static __checkReturn efx_rc_t
976 siena_filter_push_entry(
977 __inout efx_nic_t *enp,
978 __in siena_filter_type_t type,
980 __in efx_oword_t *eop)
985 case EFX_SIENA_FILTER_RX_TCP_FULL:
986 case EFX_SIENA_FILTER_RX_TCP_WILD:
987 case EFX_SIENA_FILTER_RX_UDP_FULL:
988 case EFX_SIENA_FILTER_RX_UDP_WILD:
989 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index,
993 case EFX_SIENA_FILTER_RX_MAC_FULL:
994 case EFX_SIENA_FILTER_RX_MAC_WILD:
995 EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index,
999 case EFX_SIENA_FILTER_TX_TCP_FULL:
1000 case EFX_SIENA_FILTER_TX_TCP_WILD:
1001 case EFX_SIENA_FILTER_TX_UDP_FULL:
1002 case EFX_SIENA_FILTER_TX_UDP_WILD:
1003 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index,
1007 case EFX_SIENA_FILTER_TX_MAC_FULL:
1008 case EFX_SIENA_FILTER_TX_MAC_WILD:
1009 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index,
1014 EFSYS_ASSERT(B_FALSE);
1025 static __checkReturn boolean_t
1027 __in const siena_filter_spec_t *left,
1028 __in const siena_filter_spec_t *right)
1030 siena_filter_tbl_id_t tbl_id;
1032 tbl_id = siena_filter_tbl_id(left->sfs_type);
1035 if (left->sfs_type != right->sfs_type)
1038 if (memcmp(left->sfs_dword, right->sfs_dword,
1039 sizeof (left->sfs_dword)))
1042 if ((tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
1043 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC) &&
1044 left->sfs_dmaq_id != right->sfs_dmaq_id)
1050 static __checkReturn efx_rc_t
1051 siena_filter_search(
1052 __in siena_filter_tbl_t *sftp,
1053 __in siena_filter_spec_t *spec,
1055 __in boolean_t for_insert,
1056 __out int *filter_index,
1057 __out unsigned int *depth_required)
1059 unsigned int hash, incr, filter_idx, depth;
1061 hash = siena_filter_tbl_hash(key);
1062 incr = siena_filter_tbl_increment(key);
1064 filter_idx = hash & (sftp->sft_size - 1);
1069 * Return success if entry is used and matches this spec
1070 * or entry is unused and we are trying to insert.
1072 if (siena_filter_test_used(sftp, filter_idx) ?
1073 siena_filter_equal(spec,
1074 &sftp->sft_spec[filter_idx]) :
1076 *filter_index = filter_idx;
1077 *depth_required = depth;
1081 /* Return failure if we reached the maximum search depth */
1082 if (depth == FILTER_CTL_SRCH_MAX)
1083 return (for_insert ? EBUSY : ENOENT);
1085 filter_idx = (filter_idx + incr) & (sftp->sft_size - 1);
1091 siena_filter_clear_entry(
1092 __in efx_nic_t *enp,
1093 __in siena_filter_tbl_t *sftp,
1098 if (siena_filter_test_used(sftp, index)) {
1099 siena_filter_clear_used(sftp, index);
1101 EFX_ZERO_OWORD(filter);
1102 siena_filter_push_entry(enp,
1103 sftp->sft_spec[index].sfs_type,
1106 memset(&sftp->sft_spec[index],
1107 0, sizeof (sftp->sft_spec[0]));
1112 siena_filter_tbl_clear(
1113 __in efx_nic_t *enp,
1114 __in siena_filter_tbl_id_t tbl_id)
1116 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1117 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1119 efsys_lock_state_t state;
1121 EFSYS_LOCK(enp->en_eslp, state);
1123 for (index = 0; index < sftp->sft_size; ++index) {
1124 siena_filter_clear_entry(enp, sftp, index);
1127 if (sftp->sft_used == 0)
1128 siena_filter_reset_search_depth(sfp, tbl_id);
1130 EFSYS_UNLOCK(enp->en_eslp, state);
1133 static __checkReturn efx_rc_t
1135 __in efx_nic_t *enp)
1137 siena_filter_t *sfp;
1138 siena_filter_tbl_t *sftp;
1142 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (siena_filter_t), sfp);
1149 enp->en_filter.ef_siena_filter = sfp;
1151 switch (enp->en_family) {
1152 case EFX_FAMILY_SIENA:
1153 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_IP];
1154 sftp->sft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
1156 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC];
1157 sftp->sft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
1159 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP];
1160 sftp->sft_size = FR_CZ_TX_FILTER_TBL0_ROWS;
1162 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC];
1163 sftp->sft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
1171 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1172 unsigned int bitmap_size;
1174 sftp = &sfp->sf_tbl[tbl_id];
1175 if (sftp->sft_size == 0)
1178 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1181 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1183 EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, sftp->sft_bitmap);
1184 if (!sftp->sft_bitmap) {
1189 EFSYS_KMEM_ALLOC(enp->en_esip,
1190 sftp->sft_size * sizeof (*sftp->sft_spec),
1192 if (!sftp->sft_spec) {
1196 memset(sftp->sft_spec, 0,
1197 sftp->sft_size * sizeof (*sftp->sft_spec));
1210 siena_filter_fini(enp);
1213 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1219 __in efx_nic_t *enp)
1221 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1222 siena_filter_tbl_id_t tbl_id;
1224 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1225 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
1230 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1231 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1232 unsigned int bitmap_size;
1234 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1237 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1239 if (sftp->sft_bitmap != NULL) {
1240 EFSYS_KMEM_FREE(enp->en_esip, bitmap_size,
1242 sftp->sft_bitmap = NULL;
1245 if (sftp->sft_spec != NULL) {
1246 EFSYS_KMEM_FREE(enp->en_esip, sftp->sft_size *
1247 sizeof (*sftp->sft_spec), sftp->sft_spec);
1248 sftp->sft_spec = NULL;
1252 EFSYS_KMEM_FREE(enp->en_esip, sizeof (siena_filter_t),
1253 enp->en_filter.ef_siena_filter);
1256 /* Restore filter state after a reset */
1257 static __checkReturn efx_rc_t
1258 siena_filter_restore(
1259 __in efx_nic_t *enp)
1261 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1262 siena_filter_tbl_id_t tbl_id;
1263 siena_filter_tbl_t *sftp;
1264 siena_filter_spec_t *spec;
1267 efsys_lock_state_t state;
1271 EFSYS_LOCK(enp->en_eslp, state);
1273 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1274 sftp = &sfp->sf_tbl[tbl_id];
1275 for (filter_idx = 0;
1276 filter_idx < sftp->sft_size;
1278 if (!siena_filter_test_used(sftp, filter_idx))
1281 spec = &sftp->sft_spec[filter_idx];
1282 if ((key = siena_filter_build(&filter, spec)) == 0) {
1286 if ((rc = siena_filter_push_entry(enp,
1287 spec->sfs_type, filter_idx, &filter)) != 0)
1292 siena_filter_push_rx_limits(enp);
1293 siena_filter_push_tx_limits(enp);
1295 EFSYS_UNLOCK(enp->en_eslp, state);
1303 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1305 EFSYS_UNLOCK(enp->en_eslp, state);
1310 static __checkReturn efx_rc_t
1312 __in efx_nic_t *enp,
1313 __inout efx_filter_spec_t *spec,
1314 __in boolean_t may_replace)
1317 siena_filter_spec_t sf_spec;
1318 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1319 siena_filter_tbl_id_t tbl_id;
1320 siena_filter_tbl_t *sftp;
1321 siena_filter_spec_t *saved_sf_spec;
1325 efsys_lock_state_t state;
1329 EFSYS_ASSERT3P(spec, !=, NULL);
1331 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1334 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1335 sftp = &sfp->sf_tbl[tbl_id];
1337 if (sftp->sft_size == 0) {
1342 key = siena_filter_build(&filter, &sf_spec);
1344 EFSYS_LOCK(enp->en_eslp, state);
1346 rc = siena_filter_search(sftp, &sf_spec, key, B_TRUE,
1347 &filter_idx, &depth);
1351 EFSYS_ASSERT3U(filter_idx, <, sftp->sft_size);
1352 saved_sf_spec = &sftp->sft_spec[filter_idx];
1354 if (siena_filter_test_used(sftp, filter_idx)) {
1355 if (may_replace == B_FALSE) {
1360 siena_filter_set_used(sftp, filter_idx);
1361 *saved_sf_spec = sf_spec;
1363 if (sfp->sf_depth[sf_spec.sfs_type] < depth) {
1364 sfp->sf_depth[sf_spec.sfs_type] = depth;
1365 if (tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
1366 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC)
1367 siena_filter_push_tx_limits(enp);
1369 siena_filter_push_rx_limits(enp);
1372 siena_filter_push_entry(enp, sf_spec.sfs_type,
1373 filter_idx, &filter);
1375 EFSYS_UNLOCK(enp->en_eslp, state);
1382 EFSYS_UNLOCK(enp->en_eslp, state);
1389 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1393 static __checkReturn efx_rc_t
1394 siena_filter_delete(
1395 __in efx_nic_t *enp,
1396 __inout efx_filter_spec_t *spec)
1399 siena_filter_spec_t sf_spec;
1400 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1401 siena_filter_tbl_id_t tbl_id;
1402 siena_filter_tbl_t *sftp;
1406 efsys_lock_state_t state;
1409 EFSYS_ASSERT3P(spec, !=, NULL);
1411 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1414 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1415 sftp = &sfp->sf_tbl[tbl_id];
1417 key = siena_filter_build(&filter, &sf_spec);
1419 EFSYS_LOCK(enp->en_eslp, state);
1421 rc = siena_filter_search(sftp, &sf_spec, key, B_FALSE,
1422 &filter_idx, &depth);
1426 siena_filter_clear_entry(enp, sftp, filter_idx);
1427 if (sftp->sft_used == 0)
1428 siena_filter_reset_search_depth(sfp, tbl_id);
1430 EFSYS_UNLOCK(enp->en_eslp, state);
1434 EFSYS_UNLOCK(enp->en_eslp, state);
1438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1442 #define SIENA_MAX_SUPPORTED_MATCHES 4
1444 static __checkReturn efx_rc_t
1445 siena_filter_supported_filters(
1446 __in efx_nic_t *enp,
1447 __out_ecount(buffer_length) uint32_t *buffer,
1448 __in size_t buffer_length,
1449 __out size_t *list_lengthp)
1452 uint32_t rx_matches[SIENA_MAX_SUPPORTED_MATCHES];
1456 rx_matches[index++] =
1457 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1458 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
1459 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
1461 rx_matches[index++] =
1462 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1463 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
1465 if (enp->en_features & EFX_FEATURE_MAC_HEADER_FILTERS) {
1466 rx_matches[index++] =
1467 EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC;
1469 rx_matches[index++] = EFX_FILTER_MATCH_LOC_MAC;
1472 EFSYS_ASSERT3U(index, <=, SIENA_MAX_SUPPORTED_MATCHES);
1473 list_length = index;
1475 *list_lengthp = list_length;
1477 if (buffer_length < list_length) {
1482 memcpy(buffer, rx_matches, list_length * sizeof (rx_matches[0]));
1487 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1492 #undef MAX_SUPPORTED
1494 #endif /* EFSYS_OPT_SIENA */
1496 #endif /* EFSYS_OPT_FILTER */