1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
14 /* FIXME: Add definition for driver generated software events */
15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
21 #include "siena_impl.h"
22 #endif /* EFSYS_OPT_SIENA */
24 #if EFSYS_OPT_HUNTINGTON
25 #include "hunt_impl.h"
26 #endif /* EFSYS_OPT_HUNTINGTON */
29 #include "medford_impl.h"
30 #endif /* EFSYS_OPT_MEDFORD */
32 #if EFSYS_OPT_MEDFORD2
33 #include "medford2_impl.h"
34 #endif /* EFSYS_OPT_MEDFORD2 */
36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
37 #include "ef10_impl.h"
38 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
44 #define EFX_MOD_MCDI 0x00000001
45 #define EFX_MOD_PROBE 0x00000002
46 #define EFX_MOD_NVRAM 0x00000004
47 #define EFX_MOD_VPD 0x00000008
48 #define EFX_MOD_NIC 0x00000010
49 #define EFX_MOD_INTR 0x00000020
50 #define EFX_MOD_EV 0x00000040
51 #define EFX_MOD_RX 0x00000080
52 #define EFX_MOD_TX 0x00000100
53 #define EFX_MOD_PORT 0x00000200
54 #define EFX_MOD_MON 0x00000400
55 #define EFX_MOD_FILTER 0x00001000
56 #define EFX_MOD_LIC 0x00002000
57 #define EFX_MOD_TUNNEL 0x00004000
59 #define EFX_RESET_PHY 0x00000001
60 #define EFX_RESET_RXQ_ERR 0x00000002
61 #define EFX_RESET_TXQ_ERR 0x00000004
63 typedef enum efx_mac_type_e {
72 typedef struct efx_ev_ops_s {
73 efx_rc_t (*eevo_init)(efx_nic_t *);
74 void (*eevo_fini)(efx_nic_t *);
75 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
76 efsys_mem_t *, size_t, uint32_t,
77 uint32_t, uint32_t, efx_evq_t *);
78 void (*eevo_qdestroy)(efx_evq_t *);
79 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
80 void (*eevo_qpost)(efx_evq_t *, uint16_t);
81 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
83 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
87 typedef struct efx_tx_ops_s {
88 efx_rc_t (*etxo_init)(efx_nic_t *);
89 void (*etxo_fini)(efx_nic_t *);
90 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
91 unsigned int, unsigned int,
92 efsys_mem_t *, size_t,
94 efx_evq_t *, efx_txq_t *,
96 void (*etxo_qdestroy)(efx_txq_t *);
97 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
98 unsigned int, unsigned int,
100 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
101 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
102 efx_rc_t (*etxo_qflush)(efx_txq_t *);
103 void (*etxo_qenable)(efx_txq_t *);
104 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
105 void (*etxo_qpio_disable)(efx_txq_t *);
106 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
108 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
110 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
111 unsigned int, unsigned int,
113 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
116 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
119 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
122 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
125 void (*etxo_qstats_update)(efx_txq_t *,
130 typedef struct efx_rx_ops_s {
131 efx_rc_t (*erxo_init)(efx_nic_t *);
132 void (*erxo_fini)(efx_nic_t *);
133 #if EFSYS_OPT_RX_SCATTER
134 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
136 #if EFSYS_OPT_RX_SCALE
137 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
138 efx_rx_scale_context_type_t,
139 uint32_t, uint32_t *);
140 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
141 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
143 efx_rx_hash_type_t, boolean_t);
144 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
146 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
147 unsigned int *, size_t);
148 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
150 #endif /* EFSYS_OPT_RX_SCALE */
151 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
153 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
154 unsigned int, unsigned int,
156 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
157 #if EFSYS_OPT_RX_PACKED_STREAM
158 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
159 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
161 uint16_t *, uint32_t *, uint32_t *);
163 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
164 void (*erxo_qenable)(efx_rxq_t *);
165 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
166 unsigned int, efx_rxq_type_t, uint32_t,
167 efsys_mem_t *, size_t, uint32_t,
169 efx_evq_t *, efx_rxq_t *);
170 void (*erxo_qdestroy)(efx_rxq_t *);
173 typedef struct efx_mac_ops_s {
174 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
175 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
176 efx_rc_t (*emo_addr_set)(efx_nic_t *);
177 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
178 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
179 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
180 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
181 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
182 efx_rxq_t *, boolean_t);
183 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
184 #if EFSYS_OPT_LOOPBACK
185 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
186 efx_loopback_type_t);
187 #endif /* EFSYS_OPT_LOOPBACK */
188 #if EFSYS_OPT_MAC_STATS
189 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
190 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
191 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
192 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
193 uint16_t, boolean_t);
194 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
195 efsys_stat_t *, uint32_t *);
196 #endif /* EFSYS_OPT_MAC_STATS */
199 typedef struct efx_phy_ops_s {
200 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
201 efx_rc_t (*epo_reset)(efx_nic_t *);
202 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
203 efx_rc_t (*epo_verify)(efx_nic_t *);
204 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
205 #if EFSYS_OPT_PHY_STATS
206 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
208 #endif /* EFSYS_OPT_PHY_STATS */
210 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
211 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
212 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
213 efx_bist_result_t *, uint32_t *,
214 unsigned long *, size_t);
215 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
216 #endif /* EFSYS_OPT_BIST */
220 typedef struct efx_filter_ops_s {
221 efx_rc_t (*efo_init)(efx_nic_t *);
222 void (*efo_fini)(efx_nic_t *);
223 efx_rc_t (*efo_restore)(efx_nic_t *);
224 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
225 boolean_t may_replace);
226 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
227 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
229 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
230 boolean_t, boolean_t, boolean_t,
231 uint8_t const *, uint32_t);
234 extern __checkReturn efx_rc_t
235 efx_filter_reconfigure(
237 __in_ecount(6) uint8_t const *mac_addr,
238 __in boolean_t all_unicst,
239 __in boolean_t mulcst,
240 __in boolean_t all_mulcst,
241 __in boolean_t brdcst,
242 __in_ecount(6*count) uint8_t const *addrs,
243 __in uint32_t count);
245 #endif /* EFSYS_OPT_FILTER */
248 typedef struct efx_tunnel_ops_s {
249 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
250 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
252 #endif /* EFSYS_OPT_TUNNEL */
254 typedef struct efx_port_s {
255 efx_mac_type_t ep_mac_type;
256 uint32_t ep_phy_type;
259 uint8_t ep_mac_addr[6];
260 efx_link_mode_t ep_link_mode;
261 boolean_t ep_all_unicst;
263 boolean_t ep_all_mulcst;
265 unsigned int ep_fcntl;
266 boolean_t ep_fcntl_autoneg;
267 efx_oword_t ep_multicst_hash[2];
268 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
269 EFX_MAC_MULTICAST_LIST_MAX];
270 uint32_t ep_mulcst_addr_count;
271 #if EFSYS_OPT_LOOPBACK
272 efx_loopback_type_t ep_loopback_type;
273 efx_link_mode_t ep_loopback_link_mode;
274 #endif /* EFSYS_OPT_LOOPBACK */
275 #if EFSYS_OPT_PHY_FLAGS
276 uint32_t ep_phy_flags;
277 #endif /* EFSYS_OPT_PHY_FLAGS */
278 #if EFSYS_OPT_PHY_LED_CONTROL
279 efx_phy_led_mode_t ep_phy_led_mode;
280 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
281 efx_phy_media_type_t ep_fixed_port_type;
282 efx_phy_media_type_t ep_module_type;
283 uint32_t ep_adv_cap_mask;
284 uint32_t ep_lp_cap_mask;
285 uint32_t ep_default_adv_cap_mask;
286 uint32_t ep_phy_cap_mask;
287 boolean_t ep_mac_drain;
289 efx_bist_type_t ep_current_bist;
291 const efx_mac_ops_t *ep_emop;
292 const efx_phy_ops_t *ep_epop;
295 typedef struct efx_mon_ops_s {
296 #if EFSYS_OPT_MON_STATS
297 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
298 efx_mon_stat_value_t *);
299 #endif /* EFSYS_OPT_MON_STATS */
302 typedef struct efx_mon_s {
303 efx_mon_type_t em_type;
304 const efx_mon_ops_t *em_emop;
307 typedef struct efx_intr_ops_s {
308 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
309 void (*eio_enable)(efx_nic_t *);
310 void (*eio_disable)(efx_nic_t *);
311 void (*eio_disable_unlocked)(efx_nic_t *);
312 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
313 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
314 void (*eio_status_message)(efx_nic_t *, unsigned int,
316 void (*eio_fatal)(efx_nic_t *);
317 void (*eio_fini)(efx_nic_t *);
320 typedef struct efx_intr_s {
321 const efx_intr_ops_t *ei_eiop;
322 efsys_mem_t *ei_esmp;
323 efx_intr_type_t ei_type;
324 unsigned int ei_level;
327 typedef struct efx_nic_ops_s {
328 efx_rc_t (*eno_probe)(efx_nic_t *);
329 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
330 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
331 efx_rc_t (*eno_reset)(efx_nic_t *);
332 efx_rc_t (*eno_init)(efx_nic_t *);
333 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
334 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
335 uint32_t *, size_t *);
337 efx_rc_t (*eno_register_test)(efx_nic_t *);
338 #endif /* EFSYS_OPT_DIAG */
339 void (*eno_fini)(efx_nic_t *);
340 void (*eno_unprobe)(efx_nic_t *);
343 #ifndef EFX_TXQ_LIMIT_TARGET
344 #define EFX_TXQ_LIMIT_TARGET 259
346 #ifndef EFX_RXQ_LIMIT_TARGET
347 #define EFX_RXQ_LIMIT_TARGET 512
355 typedef struct siena_filter_spec_s {
358 uint32_t sfs_dmaq_id;
359 uint32_t sfs_dword[3];
360 } siena_filter_spec_t;
362 typedef enum siena_filter_type_e {
363 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
364 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
365 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
366 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
367 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
368 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
370 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
371 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
372 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
373 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
374 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
375 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
377 EFX_SIENA_FILTER_NTYPES
378 } siena_filter_type_t;
380 typedef enum siena_filter_tbl_id_e {
381 EFX_SIENA_FILTER_TBL_RX_IP = 0,
382 EFX_SIENA_FILTER_TBL_RX_MAC,
383 EFX_SIENA_FILTER_TBL_TX_IP,
384 EFX_SIENA_FILTER_TBL_TX_MAC,
385 EFX_SIENA_FILTER_NTBLS
386 } siena_filter_tbl_id_t;
388 typedef struct siena_filter_tbl_s {
389 int sft_size; /* number of entries */
390 int sft_used; /* active count */
391 uint32_t *sft_bitmap; /* active bitmap */
392 siena_filter_spec_t *sft_spec; /* array of saved specs */
393 } siena_filter_tbl_t;
395 typedef struct siena_filter_s {
396 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
397 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
400 #endif /* EFSYS_OPT_SIENA */
402 typedef struct efx_filter_s {
404 siena_filter_t *ef_siena_filter;
405 #endif /* EFSYS_OPT_SIENA */
406 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
407 ef10_filter_table_t *ef_ef10_filter_table;
408 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
414 siena_filter_tbl_clear(
416 __in siena_filter_tbl_id_t tbl);
418 #endif /* EFSYS_OPT_SIENA */
420 #endif /* EFSYS_OPT_FILTER */
424 #define EFX_TUNNEL_MAXNENTRIES (16)
428 typedef struct efx_tunnel_udp_entry_s {
429 uint16_t etue_port; /* host/cpu-endian */
430 uint16_t etue_protocol;
431 } efx_tunnel_udp_entry_t;
433 typedef struct efx_tunnel_cfg_s {
434 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
435 unsigned int etc_udp_entries_num;
438 #endif /* EFSYS_OPT_TUNNEL */
440 typedef struct efx_mcdi_ops_s {
441 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
442 void (*emco_send_request)(efx_nic_t *, void *, size_t,
444 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
445 boolean_t (*emco_poll_response)(efx_nic_t *);
446 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
447 void (*emco_fini)(efx_nic_t *);
448 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
449 efx_mcdi_feature_id_t, boolean_t *);
450 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
454 typedef struct efx_mcdi_s {
455 const efx_mcdi_ops_t *em_emcop;
456 const efx_mcdi_transport_t *em_emtp;
457 efx_mcdi_iface_t em_emip;
460 #endif /* EFSYS_OPT_MCDI */
464 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
465 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
467 typedef struct efx_nvram_ops_s {
469 efx_rc_t (*envo_test)(efx_nic_t *);
470 #endif /* EFSYS_OPT_DIAG */
471 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
473 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
474 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
475 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
476 unsigned int, caddr_t, size_t);
477 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
478 unsigned int, caddr_t, size_t);
479 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
480 unsigned int, size_t);
481 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
482 unsigned int, caddr_t, size_t);
483 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
485 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
486 uint32_t *, uint16_t *);
487 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
489 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
492 #endif /* EFSYS_OPT_NVRAM */
495 typedef struct efx_vpd_ops_s {
496 efx_rc_t (*evpdo_init)(efx_nic_t *);
497 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
498 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
499 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
500 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
501 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
503 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
505 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
506 efx_vpd_value_t *, unsigned int *);
507 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
508 void (*evpdo_fini)(efx_nic_t *);
510 #endif /* EFSYS_OPT_VPD */
512 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
514 __checkReturn efx_rc_t
515 efx_mcdi_nvram_partitions(
517 __out_bcount(size) caddr_t data,
519 __out unsigned int *npartnp);
521 __checkReturn efx_rc_t
522 efx_mcdi_nvram_metadata(
525 __out uint32_t *subtypep,
526 __out_ecount(4) uint16_t version[4],
527 __out_bcount_opt(size) char *descp,
530 __checkReturn efx_rc_t
534 __out_opt size_t *sizep,
535 __out_opt uint32_t *addressp,
536 __out_opt uint32_t *erase_sizep,
537 __out_opt uint32_t *write_sizep);
539 __checkReturn efx_rc_t
540 efx_mcdi_nvram_update_start(
542 __in uint32_t partn);
544 __checkReturn efx_rc_t
548 __in uint32_t offset,
549 __out_bcount(size) caddr_t data,
553 __checkReturn efx_rc_t
554 efx_mcdi_nvram_erase(
557 __in uint32_t offset,
560 __checkReturn efx_rc_t
561 efx_mcdi_nvram_write(
564 __in uint32_t offset,
565 __out_bcount(size) caddr_t data,
568 __checkReturn efx_rc_t
569 efx_mcdi_nvram_update_finish(
572 __in boolean_t reboot,
573 __out_opt uint32_t *verify_resultp);
577 __checkReturn efx_rc_t
580 __in uint32_t partn);
582 #endif /* EFSYS_OPT_DIAG */
584 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
586 #if EFSYS_OPT_LICENSING
588 typedef struct efx_lic_ops_s {
589 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
590 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
591 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
592 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
593 size_t *, uint8_t *);
594 efx_rc_t (*elo_find_start)
595 (efx_nic_t *, caddr_t, size_t, uint32_t *);
596 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
597 uint32_t, uint32_t *);
598 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
599 uint32_t, uint32_t *, uint32_t *);
600 boolean_t (*elo_validate_key)(efx_nic_t *,
602 efx_rc_t (*elo_read_key)(efx_nic_t *,
603 caddr_t, size_t, uint32_t, uint32_t,
604 caddr_t, size_t, uint32_t *);
605 efx_rc_t (*elo_write_key)(efx_nic_t *,
606 caddr_t, size_t, uint32_t,
607 caddr_t, uint32_t, uint32_t *);
608 efx_rc_t (*elo_delete_key)(efx_nic_t *,
609 caddr_t, size_t, uint32_t,
610 uint32_t, uint32_t, uint32_t *);
611 efx_rc_t (*elo_create_partition)(efx_nic_t *,
613 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
619 typedef struct efx_drv_cfg_s {
620 uint32_t edc_min_vi_count;
621 uint32_t edc_max_vi_count;
623 uint32_t edc_max_piobuf_count;
624 uint32_t edc_pio_alloc_size;
629 efx_family_t en_family;
630 uint32_t en_features;
631 efsys_identifier_t *en_esip;
632 efsys_lock_t *en_eslp;
633 efsys_bar_t *en_esbp;
634 unsigned int en_mod_flags;
635 unsigned int en_reset_flags;
636 efx_nic_cfg_t en_nic_cfg;
637 efx_drv_cfg_t en_drv_cfg;
641 uint32_t en_ev_qcount;
642 uint32_t en_rx_qcount;
643 uint32_t en_tx_qcount;
644 const efx_nic_ops_t *en_enop;
645 const efx_ev_ops_t *en_eevop;
646 const efx_tx_ops_t *en_etxop;
647 const efx_rx_ops_t *en_erxop;
649 efx_filter_t en_filter;
650 const efx_filter_ops_t *en_efop;
651 #endif /* EFSYS_OPT_FILTER */
653 efx_tunnel_cfg_t en_tunnel_cfg;
654 const efx_tunnel_ops_t *en_etop;
655 #endif /* EFSYS_OPT_TUNNEL */
658 #endif /* EFSYS_OPT_MCDI */
660 uint32_t en_nvram_partn_locked;
661 const efx_nvram_ops_t *en_envop;
662 #endif /* EFSYS_OPT_NVRAM */
664 const efx_vpd_ops_t *en_evpdop;
665 #endif /* EFSYS_OPT_VPD */
666 #if EFSYS_OPT_RX_SCALE
667 efx_rx_hash_support_t en_hash_support;
668 efx_rx_scale_context_type_t en_rss_context_type;
669 uint32_t en_rss_context;
670 #endif /* EFSYS_OPT_RX_SCALE */
671 uint32_t en_vport_id;
672 #if EFSYS_OPT_LICENSING
673 const efx_lic_ops_t *en_elop;
674 boolean_t en_licensing_supported;
679 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
680 unsigned int enu_partn_mask;
681 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
684 size_t enu_svpd_length;
685 #endif /* EFSYS_OPT_VPD */
688 #endif /* EFSYS_OPT_SIENA */
691 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
699 size_t ena_svpd_length;
700 #endif /* EFSYS_OPT_VPD */
701 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
702 uint32_t ena_piobuf_count;
703 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
704 uint32_t ena_pio_write_vi_base;
705 /* Memory BAR mapping regions */
706 uint32_t ena_uc_mem_map_offset;
707 size_t ena_uc_mem_map_size;
708 uint32_t ena_wc_mem_map_offset;
709 size_t ena_wc_mem_map_size;
712 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
716 #define EFX_NIC_MAGIC 0x02121996
718 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
719 const efx_ev_callbacks_t *, void *);
721 typedef struct efx_evq_rxq_state_s {
722 unsigned int eers_rx_read_ptr;
723 unsigned int eers_rx_mask;
724 #if EFSYS_OPT_RX_PACKED_STREAM
725 unsigned int eers_rx_stream_npackets;
726 boolean_t eers_rx_packed_stream;
727 unsigned int eers_rx_packed_stream_credits;
729 } efx_evq_rxq_state_t;
734 unsigned int ee_index;
735 unsigned int ee_mask;
736 efsys_mem_t *ee_esmp;
738 uint32_t ee_stat[EV_NQSTATS];
739 #endif /* EFSYS_OPT_QSTATS */
741 efx_ev_handler_t ee_rx;
742 efx_ev_handler_t ee_tx;
743 efx_ev_handler_t ee_driver;
744 efx_ev_handler_t ee_global;
745 efx_ev_handler_t ee_drv_gen;
747 efx_ev_handler_t ee_mcdi;
748 #endif /* EFSYS_OPT_MCDI */
750 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
755 #define EFX_EVQ_MAGIC 0x08081997
757 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
763 unsigned int er_index;
764 unsigned int er_label;
765 unsigned int er_mask;
766 efsys_mem_t *er_esmp;
767 efx_evq_rxq_state_t *er_ev_qstate;
770 #define EFX_RXQ_MAGIC 0x15022005
775 unsigned int et_index;
776 unsigned int et_mask;
777 efsys_mem_t *et_esmp;
778 #if EFSYS_OPT_HUNTINGTON
779 uint32_t et_pio_bufnum;
780 uint32_t et_pio_blknum;
781 uint32_t et_pio_write_offset;
782 uint32_t et_pio_offset;
786 uint32_t et_stat[TX_NQSTATS];
787 #endif /* EFSYS_OPT_QSTATS */
790 #define EFX_TXQ_MAGIC 0x05092005
792 #define EFX_MAC_ADDR_COPY(_dst, _src) \
794 (_dst)[0] = (_src)[0]; \
795 (_dst)[1] = (_src)[1]; \
796 (_dst)[2] = (_src)[2]; \
797 (_dst)[3] = (_src)[3]; \
798 (_dst)[4] = (_src)[4]; \
799 (_dst)[5] = (_src)[5]; \
800 _NOTE(CONSTANTCONDITION) \
803 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
805 uint16_t *_d = (uint16_t *)(_dst); \
809 _NOTE(CONSTANTCONDITION) \
812 #if EFSYS_OPT_CHECK_REG
813 #define EFX_CHECK_REG(_enp, _reg) \
815 const char *name = #_reg; \
816 char min = name[4]; \
817 char max = name[5]; \
820 switch ((_enp)->en_family) { \
821 case EFX_FAMILY_SIENA: \
825 case EFX_FAMILY_HUNTINGTON: \
829 case EFX_FAMILY_MEDFORD: \
833 case EFX_FAMILY_MEDFORD2: \
842 EFSYS_ASSERT3S(rev, >=, min); \
843 EFSYS_ASSERT3S(rev, <=, max); \
845 _NOTE(CONSTANTCONDITION) \
848 #define EFX_CHECK_REG(_enp, _reg) do { \
849 _NOTE(CONSTANTCONDITION) \
853 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
855 EFX_CHECK_REG((_enp), (_reg)); \
856 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
858 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
859 uint32_t, _reg ## _OFST, \
860 uint32_t, (_edp)->ed_u32[0]); \
861 _NOTE(CONSTANTCONDITION) \
864 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
866 EFX_CHECK_REG((_enp), (_reg)); \
867 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
868 uint32_t, _reg ## _OFST, \
869 uint32_t, (_edp)->ed_u32[0]); \
870 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
872 _NOTE(CONSTANTCONDITION) \
875 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
877 EFX_CHECK_REG((_enp), (_reg)); \
878 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
880 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
881 uint32_t, _reg ## _OFST, \
882 uint32_t, (_eqp)->eq_u32[1], \
883 uint32_t, (_eqp)->eq_u32[0]); \
884 _NOTE(CONSTANTCONDITION) \
887 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
889 EFX_CHECK_REG((_enp), (_reg)); \
890 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
891 uint32_t, _reg ## _OFST, \
892 uint32_t, (_eqp)->eq_u32[1], \
893 uint32_t, (_eqp)->eq_u32[0]); \
894 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
896 _NOTE(CONSTANTCONDITION) \
899 #define EFX_BAR_READO(_enp, _reg, _eop) \
901 EFX_CHECK_REG((_enp), (_reg)); \
902 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
904 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
905 uint32_t, _reg ## _OFST, \
906 uint32_t, (_eop)->eo_u32[3], \
907 uint32_t, (_eop)->eo_u32[2], \
908 uint32_t, (_eop)->eo_u32[1], \
909 uint32_t, (_eop)->eo_u32[0]); \
910 _NOTE(CONSTANTCONDITION) \
913 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
915 EFX_CHECK_REG((_enp), (_reg)); \
916 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
917 uint32_t, _reg ## _OFST, \
918 uint32_t, (_eop)->eo_u32[3], \
919 uint32_t, (_eop)->eo_u32[2], \
920 uint32_t, (_eop)->eo_u32[1], \
921 uint32_t, (_eop)->eo_u32[0]); \
922 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
924 _NOTE(CONSTANTCONDITION) \
928 * Accessors for memory BAR non-VI tables.
930 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
931 * to ensure the correct runtime VI window size is used on Medford2.
933 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
936 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
938 EFX_CHECK_REG((_enp), (_reg)); \
939 EFSYS_BAR_READD((_enp)->en_esbp, \
940 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
942 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
943 uint32_t, (_index), \
944 uint32_t, _reg ## _OFST, \
945 uint32_t, (_edp)->ed_u32[0]); \
946 _NOTE(CONSTANTCONDITION) \
949 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
951 EFX_CHECK_REG((_enp), (_reg)); \
952 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
953 uint32_t, (_index), \
954 uint32_t, _reg ## _OFST, \
955 uint32_t, (_edp)->ed_u32[0]); \
956 EFSYS_BAR_WRITED((_enp)->en_esbp, \
957 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
959 _NOTE(CONSTANTCONDITION) \
962 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
964 EFX_CHECK_REG((_enp), (_reg)); \
965 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
966 uint32_t, (_index), \
967 uint32_t, _reg ## _OFST, \
968 uint32_t, (_edp)->ed_u32[0]); \
969 EFSYS_BAR_WRITED((_enp)->en_esbp, \
971 (3 * sizeof (efx_dword_t)) + \
972 ((_index) * _reg ## _STEP)), \
974 _NOTE(CONSTANTCONDITION) \
977 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
979 EFX_CHECK_REG((_enp), (_reg)); \
980 EFSYS_BAR_READQ((_enp)->en_esbp, \
981 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
983 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
984 uint32_t, (_index), \
985 uint32_t, _reg ## _OFST, \
986 uint32_t, (_eqp)->eq_u32[1], \
987 uint32_t, (_eqp)->eq_u32[0]); \
988 _NOTE(CONSTANTCONDITION) \
991 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
993 EFX_CHECK_REG((_enp), (_reg)); \
994 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
995 uint32_t, (_index), \
996 uint32_t, _reg ## _OFST, \
997 uint32_t, (_eqp)->eq_u32[1], \
998 uint32_t, (_eqp)->eq_u32[0]); \
999 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1000 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1002 _NOTE(CONSTANTCONDITION) \
1005 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1007 EFX_CHECK_REG((_enp), (_reg)); \
1008 EFSYS_BAR_READO((_enp)->en_esbp, \
1009 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1011 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1012 uint32_t, (_index), \
1013 uint32_t, _reg ## _OFST, \
1014 uint32_t, (_eop)->eo_u32[3], \
1015 uint32_t, (_eop)->eo_u32[2], \
1016 uint32_t, (_eop)->eo_u32[1], \
1017 uint32_t, (_eop)->eo_u32[0]); \
1018 _NOTE(CONSTANTCONDITION) \
1021 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1023 EFX_CHECK_REG((_enp), (_reg)); \
1024 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1025 uint32_t, (_index), \
1026 uint32_t, _reg ## _OFST, \
1027 uint32_t, (_eop)->eo_u32[3], \
1028 uint32_t, (_eop)->eo_u32[2], \
1029 uint32_t, (_eop)->eo_u32[1], \
1030 uint32_t, (_eop)->eo_u32[0]); \
1031 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1032 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1034 _NOTE(CONSTANTCONDITION) \
1038 * Accessors for memory BAR per-VI registers.
1040 * The VI window size is 8KB for Medford and all earlier controllers.
1041 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1044 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1046 EFX_CHECK_REG((_enp), (_reg)); \
1047 EFSYS_BAR_READD((_enp)->en_esbp, \
1048 ((_reg ## _OFST) + \
1049 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1051 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1052 uint32_t, (_index), \
1053 uint32_t, _reg ## _OFST, \
1054 uint32_t, (_edp)->ed_u32[0]); \
1055 _NOTE(CONSTANTCONDITION) \
1058 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1060 EFX_CHECK_REG((_enp), (_reg)); \
1061 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1062 uint32_t, (_index), \
1063 uint32_t, _reg ## _OFST, \
1064 uint32_t, (_edp)->ed_u32[0]); \
1065 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1066 ((_reg ## _OFST) + \
1067 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1069 _NOTE(CONSTANTCONDITION) \
1072 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1074 EFX_CHECK_REG((_enp), (_reg)); \
1075 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1076 uint32_t, (_index), \
1077 uint32_t, _reg ## _OFST, \
1078 uint32_t, (_edp)->ed_u32[0]); \
1079 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1080 ((_reg ## _OFST) + \
1081 (2 * sizeof (efx_dword_t)) + \
1082 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1084 _NOTE(CONSTANTCONDITION) \
1088 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1089 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1090 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1091 * the need for locking in the host, and are the only ones known to be safe to
1092 * use 128-bites write with.
1094 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1096 EFX_CHECK_REG((_enp), (_reg)); \
1097 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1098 const char *, #_reg, \
1099 uint32_t, (_index), \
1100 uint32_t, _reg ## _OFST, \
1101 uint32_t, (_eop)->eo_u32[3], \
1102 uint32_t, (_eop)->eo_u32[2], \
1103 uint32_t, (_eop)->eo_u32[1], \
1104 uint32_t, (_eop)->eo_u32[0]); \
1105 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1107 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1109 _NOTE(CONSTANTCONDITION) \
1112 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1114 unsigned int _new = (_wptr); \
1115 unsigned int _old = (_owptr); \
1117 if ((_new) >= (_old)) \
1118 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1119 (_old) * sizeof (efx_desc_t), \
1120 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1123 * It is cheaper to sync entire map than sync \
1124 * two parts especially when offset/size are \
1125 * ignored and entire map is synced in any case.\
1127 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1129 (_entries) * sizeof (efx_desc_t)); \
1130 _NOTE(CONSTANTCONDITION) \
1133 extern __checkReturn efx_rc_t
1135 __in efx_nic_t *enp);
1138 efx_mac_multicast_hash_compute(
1139 __in_ecount(6*count) uint8_t const *addrs,
1141 __out efx_oword_t *hash_low,
1142 __out efx_oword_t *hash_high);
1144 extern __checkReturn efx_rc_t
1146 __in efx_nic_t *enp);
1150 __in efx_nic_t *enp);
1154 /* VPD utility functions */
1156 extern __checkReturn efx_rc_t
1157 efx_vpd_hunk_length(
1158 __in_bcount(size) caddr_t data,
1160 __out size_t *lengthp);
1162 extern __checkReturn efx_rc_t
1163 efx_vpd_hunk_verify(
1164 __in_bcount(size) caddr_t data,
1166 __out_opt boolean_t *cksummedp);
1168 extern __checkReturn efx_rc_t
1169 efx_vpd_hunk_reinit(
1170 __in_bcount(size) caddr_t data,
1172 __in boolean_t wantpid);
1174 extern __checkReturn efx_rc_t
1176 __in_bcount(size) caddr_t data,
1178 __in efx_vpd_tag_t tag,
1179 __in efx_vpd_keyword_t keyword,
1180 __out unsigned int *payloadp,
1181 __out uint8_t *paylenp);
1183 extern __checkReturn efx_rc_t
1185 __in_bcount(size) caddr_t data,
1187 __out efx_vpd_tag_t *tagp,
1188 __out efx_vpd_keyword_t *keyword,
1189 __out_opt unsigned int *payloadp,
1190 __out_opt uint8_t *paylenp,
1191 __inout unsigned int *contp);
1193 extern __checkReturn efx_rc_t
1195 __in_bcount(size) caddr_t data,
1197 __in efx_vpd_value_t *evvp);
1199 #endif /* EFSYS_OPT_VPD */
1203 extern __checkReturn efx_rc_t
1204 efx_mcdi_set_workaround(
1205 __in efx_nic_t *enp,
1207 __in boolean_t enabled,
1208 __out_opt uint32_t *flagsp);
1210 extern __checkReturn efx_rc_t
1211 efx_mcdi_get_workarounds(
1212 __in efx_nic_t *enp,
1213 __out_opt uint32_t *implementedp,
1214 __out_opt uint32_t *enabledp);
1216 #endif /* EFSYS_OPT_MCDI */
1218 #if EFSYS_OPT_MAC_STATS
1221 * Closed range of stats (i.e. the first and the last are included).
1222 * The last must be greater or equal (if the range is one item only) to
1225 struct efx_mac_stats_range {
1226 efx_mac_stat_t first;
1227 efx_mac_stat_t last;
1231 efx_mac_stats_mask_add_ranges(
1232 __inout_bcount(mask_size) uint32_t *maskp,
1233 __in size_t mask_size,
1234 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1235 __in unsigned int rng_count);
1237 #endif /* EFSYS_OPT_MAC_STATS */
1243 #endif /* _SYS_EFX_IMPL_H */