1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
14 /* FIXME: Add definition for driver generated software events */
15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
21 #include "siena_impl.h"
22 #endif /* EFSYS_OPT_SIENA */
24 #if EFSYS_OPT_HUNTINGTON
25 #include "hunt_impl.h"
26 #endif /* EFSYS_OPT_HUNTINGTON */
29 #include "medford_impl.h"
30 #endif /* EFSYS_OPT_MEDFORD */
32 #if EFSYS_OPT_MEDFORD2
33 #include "medford2_impl.h"
34 #endif /* EFSYS_OPT_MEDFORD2 */
36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
37 #include "ef10_impl.h"
38 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
44 #define EFX_MOD_MCDI 0x00000001
45 #define EFX_MOD_PROBE 0x00000002
46 #define EFX_MOD_NVRAM 0x00000004
47 #define EFX_MOD_VPD 0x00000008
48 #define EFX_MOD_NIC 0x00000010
49 #define EFX_MOD_INTR 0x00000020
50 #define EFX_MOD_EV 0x00000040
51 #define EFX_MOD_RX 0x00000080
52 #define EFX_MOD_TX 0x00000100
53 #define EFX_MOD_PORT 0x00000200
54 #define EFX_MOD_MON 0x00000400
55 #define EFX_MOD_FILTER 0x00001000
56 #define EFX_MOD_LIC 0x00002000
57 #define EFX_MOD_TUNNEL 0x00004000
59 #define EFX_RESET_PHY 0x00000001
60 #define EFX_RESET_RXQ_ERR 0x00000002
61 #define EFX_RESET_TXQ_ERR 0x00000004
62 #define EFX_RESET_HW_UNAVAIL 0x00000008
64 typedef enum efx_mac_type_e {
73 typedef struct efx_ev_ops_s {
74 efx_rc_t (*eevo_init)(efx_nic_t *);
75 void (*eevo_fini)(efx_nic_t *);
76 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
77 efsys_mem_t *, size_t, uint32_t,
78 uint32_t, uint32_t, efx_evq_t *);
79 void (*eevo_qdestroy)(efx_evq_t *);
80 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
81 void (*eevo_qpost)(efx_evq_t *, uint16_t);
82 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
84 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
88 typedef struct efx_tx_ops_s {
89 efx_rc_t (*etxo_init)(efx_nic_t *);
90 void (*etxo_fini)(efx_nic_t *);
91 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
92 unsigned int, unsigned int,
93 efsys_mem_t *, size_t,
95 efx_evq_t *, efx_txq_t *,
97 void (*etxo_qdestroy)(efx_txq_t *);
98 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
99 unsigned int, unsigned int,
101 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
102 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
103 efx_rc_t (*etxo_qflush)(efx_txq_t *);
104 void (*etxo_qenable)(efx_txq_t *);
105 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
106 void (*etxo_qpio_disable)(efx_txq_t *);
107 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
109 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
111 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
112 unsigned int, unsigned int,
114 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
117 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
120 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
121 uint16_t, uint32_t, uint16_t,
123 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
125 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
128 void (*etxo_qstats_update)(efx_txq_t *,
133 typedef union efx_rxq_type_data_u {
134 /* Dummy member to have non-empty union if no options are enabled */
136 #if EFSYS_OPT_RX_PACKED_STREAM
138 uint32_t eps_buf_size;
139 } ertd_packed_stream;
141 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
143 uint32_t eessb_bufs_per_desc;
144 uint32_t eessb_max_dma_len;
145 uint32_t eessb_buf_stride;
146 uint32_t eessb_hol_block_timeout;
147 } ertd_es_super_buffer;
149 } efx_rxq_type_data_t;
151 typedef struct efx_rx_ops_s {
152 efx_rc_t (*erxo_init)(efx_nic_t *);
153 void (*erxo_fini)(efx_nic_t *);
154 #if EFSYS_OPT_RX_SCATTER
155 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
157 #if EFSYS_OPT_RX_SCALE
158 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
159 efx_rx_scale_context_type_t,
160 uint32_t, uint32_t *);
161 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
162 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
164 efx_rx_hash_type_t, boolean_t);
165 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
167 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
168 unsigned int *, size_t);
169 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
171 #endif /* EFSYS_OPT_RX_SCALE */
172 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
174 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
175 unsigned int, unsigned int,
177 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
178 #if EFSYS_OPT_RX_PACKED_STREAM
179 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
180 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
182 uint16_t *, uint32_t *, uint32_t *);
184 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
185 void (*erxo_qenable)(efx_rxq_t *);
186 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
187 unsigned int, efx_rxq_type_t,
188 const efx_rxq_type_data_t *,
189 efsys_mem_t *, size_t, uint32_t,
191 efx_evq_t *, efx_rxq_t *);
192 void (*erxo_qdestroy)(efx_rxq_t *);
195 typedef struct efx_mac_ops_s {
196 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
197 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
198 efx_rc_t (*emo_addr_set)(efx_nic_t *);
199 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
200 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
201 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
202 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
203 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
204 efx_rxq_t *, boolean_t);
205 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
206 #if EFSYS_OPT_LOOPBACK
207 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
208 efx_loopback_type_t);
209 #endif /* EFSYS_OPT_LOOPBACK */
210 #if EFSYS_OPT_MAC_STATS
211 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
212 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
213 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
214 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
215 uint16_t, boolean_t);
216 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
217 efsys_stat_t *, uint32_t *);
218 #endif /* EFSYS_OPT_MAC_STATS */
221 typedef struct efx_phy_ops_s {
222 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
223 efx_rc_t (*epo_reset)(efx_nic_t *);
224 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
225 efx_rc_t (*epo_verify)(efx_nic_t *);
226 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
227 #if EFSYS_OPT_PHY_STATS
228 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
230 #endif /* EFSYS_OPT_PHY_STATS */
232 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
233 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
234 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
235 efx_bist_result_t *, uint32_t *,
236 unsigned long *, size_t);
237 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
238 #endif /* EFSYS_OPT_BIST */
242 typedef struct efx_filter_ops_s {
243 efx_rc_t (*efo_init)(efx_nic_t *);
244 void (*efo_fini)(efx_nic_t *);
245 efx_rc_t (*efo_restore)(efx_nic_t *);
246 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
247 boolean_t may_replace);
248 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
249 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
251 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
252 boolean_t, boolean_t, boolean_t,
253 uint8_t const *, uint32_t);
256 extern __checkReturn efx_rc_t
257 efx_filter_reconfigure(
259 __in_ecount(6) uint8_t const *mac_addr,
260 __in boolean_t all_unicst,
261 __in boolean_t mulcst,
262 __in boolean_t all_mulcst,
263 __in boolean_t brdcst,
264 __in_ecount(6*count) uint8_t const *addrs,
265 __in uint32_t count);
267 #endif /* EFSYS_OPT_FILTER */
270 typedef struct efx_tunnel_ops_s {
271 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
272 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
274 #endif /* EFSYS_OPT_TUNNEL */
276 typedef struct efx_port_s {
277 efx_mac_type_t ep_mac_type;
278 uint32_t ep_phy_type;
281 uint8_t ep_mac_addr[6];
282 efx_link_mode_t ep_link_mode;
283 boolean_t ep_all_unicst;
285 boolean_t ep_all_mulcst;
287 unsigned int ep_fcntl;
288 boolean_t ep_fcntl_autoneg;
289 efx_oword_t ep_multicst_hash[2];
290 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
291 EFX_MAC_MULTICAST_LIST_MAX];
292 uint32_t ep_mulcst_addr_count;
293 #if EFSYS_OPT_LOOPBACK
294 efx_loopback_type_t ep_loopback_type;
295 efx_link_mode_t ep_loopback_link_mode;
296 #endif /* EFSYS_OPT_LOOPBACK */
297 #if EFSYS_OPT_PHY_FLAGS
298 uint32_t ep_phy_flags;
299 #endif /* EFSYS_OPT_PHY_FLAGS */
300 #if EFSYS_OPT_PHY_LED_CONTROL
301 efx_phy_led_mode_t ep_phy_led_mode;
302 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
303 efx_phy_media_type_t ep_fixed_port_type;
304 efx_phy_media_type_t ep_module_type;
305 uint32_t ep_adv_cap_mask;
306 uint32_t ep_lp_cap_mask;
307 uint32_t ep_default_adv_cap_mask;
308 uint32_t ep_phy_cap_mask;
309 boolean_t ep_mac_drain;
311 efx_bist_type_t ep_current_bist;
313 const efx_mac_ops_t *ep_emop;
314 const efx_phy_ops_t *ep_epop;
317 typedef struct efx_mon_ops_s {
318 #if EFSYS_OPT_MON_STATS
319 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
320 efx_mon_stat_value_t *);
321 efx_rc_t (*emo_limits_update)(efx_nic_t *,
322 efx_mon_stat_limits_t *);
323 #endif /* EFSYS_OPT_MON_STATS */
326 typedef struct efx_mon_s {
327 efx_mon_type_t em_type;
328 const efx_mon_ops_t *em_emop;
331 typedef struct efx_intr_ops_s {
332 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
333 void (*eio_enable)(efx_nic_t *);
334 void (*eio_disable)(efx_nic_t *);
335 void (*eio_disable_unlocked)(efx_nic_t *);
336 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
337 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
338 void (*eio_status_message)(efx_nic_t *, unsigned int,
340 void (*eio_fatal)(efx_nic_t *);
341 void (*eio_fini)(efx_nic_t *);
344 typedef struct efx_intr_s {
345 const efx_intr_ops_t *ei_eiop;
346 efsys_mem_t *ei_esmp;
347 efx_intr_type_t ei_type;
348 unsigned int ei_level;
351 typedef struct efx_nic_ops_s {
352 efx_rc_t (*eno_probe)(efx_nic_t *);
353 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
354 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
355 efx_rc_t (*eno_reset)(efx_nic_t *);
356 efx_rc_t (*eno_init)(efx_nic_t *);
357 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
358 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
359 uint32_t *, size_t *);
360 boolean_t (*eno_hw_unavailable)(efx_nic_t *);
361 void (*eno_set_hw_unavailable)(efx_nic_t *);
363 efx_rc_t (*eno_register_test)(efx_nic_t *);
364 #endif /* EFSYS_OPT_DIAG */
365 void (*eno_fini)(efx_nic_t *);
366 void (*eno_unprobe)(efx_nic_t *);
369 #ifndef EFX_TXQ_LIMIT_TARGET
370 #define EFX_TXQ_LIMIT_TARGET 259
372 #ifndef EFX_RXQ_LIMIT_TARGET
373 #define EFX_RXQ_LIMIT_TARGET 512
381 typedef struct siena_filter_spec_s {
384 uint32_t sfs_dmaq_id;
385 uint32_t sfs_dword[3];
386 } siena_filter_spec_t;
388 typedef enum siena_filter_type_e {
389 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
390 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
391 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
392 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
393 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
394 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
396 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
397 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
398 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
399 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
400 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
401 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
403 EFX_SIENA_FILTER_NTYPES
404 } siena_filter_type_t;
406 typedef enum siena_filter_tbl_id_e {
407 EFX_SIENA_FILTER_TBL_RX_IP = 0,
408 EFX_SIENA_FILTER_TBL_RX_MAC,
409 EFX_SIENA_FILTER_TBL_TX_IP,
410 EFX_SIENA_FILTER_TBL_TX_MAC,
411 EFX_SIENA_FILTER_NTBLS
412 } siena_filter_tbl_id_t;
414 typedef struct siena_filter_tbl_s {
415 int sft_size; /* number of entries */
416 int sft_used; /* active count */
417 uint32_t *sft_bitmap; /* active bitmap */
418 siena_filter_spec_t *sft_spec; /* array of saved specs */
419 } siena_filter_tbl_t;
421 typedef struct siena_filter_s {
422 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
423 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
426 #endif /* EFSYS_OPT_SIENA */
428 typedef struct efx_filter_s {
430 siena_filter_t *ef_siena_filter;
431 #endif /* EFSYS_OPT_SIENA */
432 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
433 ef10_filter_table_t *ef_ef10_filter_table;
434 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
440 siena_filter_tbl_clear(
442 __in siena_filter_tbl_id_t tbl);
444 #endif /* EFSYS_OPT_SIENA */
446 #endif /* EFSYS_OPT_FILTER */
450 #define EFX_TUNNEL_MAXNENTRIES (16)
454 typedef struct efx_tunnel_udp_entry_s {
455 uint16_t etue_port; /* host/cpu-endian */
456 uint16_t etue_protocol;
457 } efx_tunnel_udp_entry_t;
459 typedef struct efx_tunnel_cfg_s {
460 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
461 unsigned int etc_udp_entries_num;
464 #endif /* EFSYS_OPT_TUNNEL */
466 typedef struct efx_mcdi_ops_s {
467 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
468 void (*emco_send_request)(efx_nic_t *, void *, size_t,
470 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
471 boolean_t (*emco_poll_response)(efx_nic_t *);
472 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
473 void (*emco_fini)(efx_nic_t *);
474 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
475 efx_mcdi_feature_id_t, boolean_t *);
476 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
480 typedef struct efx_mcdi_s {
481 const efx_mcdi_ops_t *em_emcop;
482 const efx_mcdi_transport_t *em_emtp;
483 efx_mcdi_iface_t em_emip;
486 #endif /* EFSYS_OPT_MCDI */
490 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
491 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
493 typedef struct efx_nvram_ops_s {
495 efx_rc_t (*envo_test)(efx_nic_t *);
496 #endif /* EFSYS_OPT_DIAG */
497 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
499 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
500 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
501 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
502 unsigned int, caddr_t, size_t);
503 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
504 unsigned int, caddr_t, size_t);
505 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
506 unsigned int, size_t);
507 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
508 unsigned int, caddr_t, size_t);
509 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
511 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
512 uint32_t *, uint16_t *);
513 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
515 efx_rc_t (*envo_buffer_validate)(uint32_t,
518 #endif /* EFSYS_OPT_NVRAM */
521 typedef struct efx_vpd_ops_s {
522 efx_rc_t (*evpdo_init)(efx_nic_t *);
523 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
524 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
525 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
526 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
527 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
529 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
531 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
532 efx_vpd_value_t *, unsigned int *);
533 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
534 void (*evpdo_fini)(efx_nic_t *);
536 #endif /* EFSYS_OPT_VPD */
538 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
540 __checkReturn efx_rc_t
541 efx_mcdi_nvram_partitions(
543 __out_bcount(size) caddr_t data,
545 __out unsigned int *npartnp);
547 __checkReturn efx_rc_t
548 efx_mcdi_nvram_metadata(
551 __out uint32_t *subtypep,
552 __out_ecount(4) uint16_t version[4],
553 __out_bcount_opt(size) char *descp,
556 __checkReturn efx_rc_t
560 __out_opt size_t *sizep,
561 __out_opt uint32_t *addressp,
562 __out_opt uint32_t *erase_sizep,
563 __out_opt uint32_t *write_sizep);
565 __checkReturn efx_rc_t
566 efx_mcdi_nvram_update_start(
568 __in uint32_t partn);
570 __checkReturn efx_rc_t
574 __in uint32_t offset,
575 __out_bcount(size) caddr_t data,
579 __checkReturn efx_rc_t
580 efx_mcdi_nvram_erase(
583 __in uint32_t offset,
586 __checkReturn efx_rc_t
587 efx_mcdi_nvram_write(
590 __in uint32_t offset,
591 __in_bcount(size) caddr_t data,
594 __checkReturn efx_rc_t
595 efx_mcdi_nvram_update_finish(
598 __in boolean_t reboot,
599 __out_opt uint32_t *verify_resultp);
603 __checkReturn efx_rc_t
606 __in uint32_t partn);
608 #endif /* EFSYS_OPT_DIAG */
610 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
612 #if EFSYS_OPT_LICENSING
614 typedef struct efx_lic_ops_s {
615 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
616 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
617 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
618 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
619 size_t *, uint8_t *);
620 efx_rc_t (*elo_find_start)
621 (efx_nic_t *, caddr_t, size_t, uint32_t *);
622 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
623 uint32_t, uint32_t *);
624 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
625 uint32_t, uint32_t *, uint32_t *);
626 boolean_t (*elo_validate_key)(efx_nic_t *,
628 efx_rc_t (*elo_read_key)(efx_nic_t *,
629 caddr_t, size_t, uint32_t, uint32_t,
630 caddr_t, size_t, uint32_t *);
631 efx_rc_t (*elo_write_key)(efx_nic_t *,
632 caddr_t, size_t, uint32_t,
633 caddr_t, uint32_t, uint32_t *);
634 efx_rc_t (*elo_delete_key)(efx_nic_t *,
635 caddr_t, size_t, uint32_t,
636 uint32_t, uint32_t, uint32_t *);
637 efx_rc_t (*elo_create_partition)(efx_nic_t *,
639 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
645 typedef struct efx_drv_cfg_s {
646 uint32_t edc_min_vi_count;
647 uint32_t edc_max_vi_count;
649 uint32_t edc_max_piobuf_count;
650 uint32_t edc_pio_alloc_size;
655 efx_family_t en_family;
656 uint32_t en_features;
657 efsys_identifier_t *en_esip;
658 efsys_lock_t *en_eslp;
659 efsys_bar_t *en_esbp;
660 unsigned int en_mod_flags;
661 unsigned int en_reset_flags;
662 efx_nic_cfg_t en_nic_cfg;
663 efx_drv_cfg_t en_drv_cfg;
667 uint32_t en_ev_qcount;
668 uint32_t en_rx_qcount;
669 uint32_t en_tx_qcount;
670 const efx_nic_ops_t *en_enop;
671 const efx_ev_ops_t *en_eevop;
672 const efx_tx_ops_t *en_etxop;
673 const efx_rx_ops_t *en_erxop;
674 efx_fw_variant_t efv;
676 efx_filter_t en_filter;
677 const efx_filter_ops_t *en_efop;
678 #endif /* EFSYS_OPT_FILTER */
680 efx_tunnel_cfg_t en_tunnel_cfg;
681 const efx_tunnel_ops_t *en_etop;
682 #endif /* EFSYS_OPT_TUNNEL */
685 #endif /* EFSYS_OPT_MCDI */
687 uint32_t en_nvram_partn_locked;
688 const efx_nvram_ops_t *en_envop;
689 #endif /* EFSYS_OPT_NVRAM */
691 const efx_vpd_ops_t *en_evpdop;
692 #endif /* EFSYS_OPT_VPD */
693 #if EFSYS_OPT_RX_SCALE
694 efx_rx_hash_support_t en_hash_support;
695 efx_rx_scale_context_type_t en_rss_context_type;
696 uint32_t en_rss_context;
697 #endif /* EFSYS_OPT_RX_SCALE */
698 uint32_t en_vport_id;
699 #if EFSYS_OPT_LICENSING
700 const efx_lic_ops_t *en_elop;
701 boolean_t en_licensing_supported;
706 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
707 unsigned int enu_partn_mask;
708 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
711 size_t enu_svpd_length;
712 #endif /* EFSYS_OPT_VPD */
715 #endif /* EFSYS_OPT_SIENA */
718 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
726 size_t ena_svpd_length;
727 #endif /* EFSYS_OPT_VPD */
728 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
729 uint32_t ena_piobuf_count;
730 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
731 uint32_t ena_pio_write_vi_base;
732 /* Memory BAR mapping regions */
733 uint32_t ena_uc_mem_map_offset;
734 size_t ena_uc_mem_map_size;
735 uint32_t ena_wc_mem_map_offset;
736 size_t ena_wc_mem_map_size;
739 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
743 #define EFX_NIC_MAGIC 0x02121996
745 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
746 const efx_ev_callbacks_t *, void *);
748 typedef struct efx_evq_rxq_state_s {
749 unsigned int eers_rx_read_ptr;
750 unsigned int eers_rx_mask;
751 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
752 unsigned int eers_rx_stream_npackets;
753 boolean_t eers_rx_packed_stream;
755 #if EFSYS_OPT_RX_PACKED_STREAM
756 unsigned int eers_rx_packed_stream_credits;
758 } efx_evq_rxq_state_t;
763 unsigned int ee_index;
764 unsigned int ee_mask;
765 efsys_mem_t *ee_esmp;
767 uint32_t ee_stat[EV_NQSTATS];
768 #endif /* EFSYS_OPT_QSTATS */
770 efx_ev_handler_t ee_rx;
771 efx_ev_handler_t ee_tx;
772 efx_ev_handler_t ee_driver;
773 efx_ev_handler_t ee_global;
774 efx_ev_handler_t ee_drv_gen;
776 efx_ev_handler_t ee_mcdi;
777 #endif /* EFSYS_OPT_MCDI */
779 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
784 #define EFX_EVQ_MAGIC 0x08081997
786 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
792 unsigned int er_index;
793 unsigned int er_label;
794 unsigned int er_mask;
795 efsys_mem_t *er_esmp;
796 efx_evq_rxq_state_t *er_ev_qstate;
799 #define EFX_RXQ_MAGIC 0x15022005
804 unsigned int et_index;
805 unsigned int et_mask;
806 efsys_mem_t *et_esmp;
807 #if EFSYS_OPT_HUNTINGTON
808 uint32_t et_pio_bufnum;
809 uint32_t et_pio_blknum;
810 uint32_t et_pio_write_offset;
811 uint32_t et_pio_offset;
815 uint32_t et_stat[TX_NQSTATS];
816 #endif /* EFSYS_OPT_QSTATS */
819 #define EFX_TXQ_MAGIC 0x05092005
821 #define EFX_MAC_ADDR_COPY(_dst, _src) \
823 (_dst)[0] = (_src)[0]; \
824 (_dst)[1] = (_src)[1]; \
825 (_dst)[2] = (_src)[2]; \
826 (_dst)[3] = (_src)[3]; \
827 (_dst)[4] = (_src)[4]; \
828 (_dst)[5] = (_src)[5]; \
829 _NOTE(CONSTANTCONDITION) \
832 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
834 uint16_t *_d = (uint16_t *)(_dst); \
838 _NOTE(CONSTANTCONDITION) \
841 #if EFSYS_OPT_CHECK_REG
842 #define EFX_CHECK_REG(_enp, _reg) \
844 const char *name = #_reg; \
845 char min = name[4]; \
846 char max = name[5]; \
849 switch ((_enp)->en_family) { \
850 case EFX_FAMILY_SIENA: \
854 case EFX_FAMILY_HUNTINGTON: \
858 case EFX_FAMILY_MEDFORD: \
862 case EFX_FAMILY_MEDFORD2: \
871 EFSYS_ASSERT3S(rev, >=, min); \
872 EFSYS_ASSERT3S(rev, <=, max); \
874 _NOTE(CONSTANTCONDITION) \
877 #define EFX_CHECK_REG(_enp, _reg) do { \
878 _NOTE(CONSTANTCONDITION) \
882 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
884 EFX_CHECK_REG((_enp), (_reg)); \
885 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
887 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
888 uint32_t, _reg ## _OFST, \
889 uint32_t, (_edp)->ed_u32[0]); \
890 _NOTE(CONSTANTCONDITION) \
893 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
895 EFX_CHECK_REG((_enp), (_reg)); \
896 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
897 uint32_t, _reg ## _OFST, \
898 uint32_t, (_edp)->ed_u32[0]); \
899 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
901 _NOTE(CONSTANTCONDITION) \
904 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
906 EFX_CHECK_REG((_enp), (_reg)); \
907 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
909 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
910 uint32_t, _reg ## _OFST, \
911 uint32_t, (_eqp)->eq_u32[1], \
912 uint32_t, (_eqp)->eq_u32[0]); \
913 _NOTE(CONSTANTCONDITION) \
916 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
918 EFX_CHECK_REG((_enp), (_reg)); \
919 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
920 uint32_t, _reg ## _OFST, \
921 uint32_t, (_eqp)->eq_u32[1], \
922 uint32_t, (_eqp)->eq_u32[0]); \
923 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
925 _NOTE(CONSTANTCONDITION) \
928 #define EFX_BAR_READO(_enp, _reg, _eop) \
930 EFX_CHECK_REG((_enp), (_reg)); \
931 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
933 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
934 uint32_t, _reg ## _OFST, \
935 uint32_t, (_eop)->eo_u32[3], \
936 uint32_t, (_eop)->eo_u32[2], \
937 uint32_t, (_eop)->eo_u32[1], \
938 uint32_t, (_eop)->eo_u32[0]); \
939 _NOTE(CONSTANTCONDITION) \
942 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
944 EFX_CHECK_REG((_enp), (_reg)); \
945 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
946 uint32_t, _reg ## _OFST, \
947 uint32_t, (_eop)->eo_u32[3], \
948 uint32_t, (_eop)->eo_u32[2], \
949 uint32_t, (_eop)->eo_u32[1], \
950 uint32_t, (_eop)->eo_u32[0]); \
951 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
953 _NOTE(CONSTANTCONDITION) \
957 * Accessors for memory BAR non-VI tables.
959 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
960 * to ensure the correct runtime VI window size is used on Medford2.
962 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
965 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
967 EFX_CHECK_REG((_enp), (_reg)); \
968 EFSYS_BAR_READD((_enp)->en_esbp, \
969 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
971 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
972 uint32_t, (_index), \
973 uint32_t, _reg ## _OFST, \
974 uint32_t, (_edp)->ed_u32[0]); \
975 _NOTE(CONSTANTCONDITION) \
978 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
980 EFX_CHECK_REG((_enp), (_reg)); \
981 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
982 uint32_t, (_index), \
983 uint32_t, _reg ## _OFST, \
984 uint32_t, (_edp)->ed_u32[0]); \
985 EFSYS_BAR_WRITED((_enp)->en_esbp, \
986 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
988 _NOTE(CONSTANTCONDITION) \
991 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
993 EFX_CHECK_REG((_enp), (_reg)); \
994 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
995 uint32_t, (_index), \
996 uint32_t, _reg ## _OFST, \
997 uint32_t, (_edp)->ed_u32[0]); \
998 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1000 (3 * sizeof (efx_dword_t)) + \
1001 ((_index) * _reg ## _STEP)), \
1003 _NOTE(CONSTANTCONDITION) \
1006 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
1008 EFX_CHECK_REG((_enp), (_reg)); \
1009 EFSYS_BAR_READQ((_enp)->en_esbp, \
1010 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1012 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
1013 uint32_t, (_index), \
1014 uint32_t, _reg ## _OFST, \
1015 uint32_t, (_eqp)->eq_u32[1], \
1016 uint32_t, (_eqp)->eq_u32[0]); \
1017 _NOTE(CONSTANTCONDITION) \
1020 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1022 EFX_CHECK_REG((_enp), (_reg)); \
1023 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1024 uint32_t, (_index), \
1025 uint32_t, _reg ## _OFST, \
1026 uint32_t, (_eqp)->eq_u32[1], \
1027 uint32_t, (_eqp)->eq_u32[0]); \
1028 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1029 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1031 _NOTE(CONSTANTCONDITION) \
1034 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1036 EFX_CHECK_REG((_enp), (_reg)); \
1037 EFSYS_BAR_READO((_enp)->en_esbp, \
1038 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1040 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1041 uint32_t, (_index), \
1042 uint32_t, _reg ## _OFST, \
1043 uint32_t, (_eop)->eo_u32[3], \
1044 uint32_t, (_eop)->eo_u32[2], \
1045 uint32_t, (_eop)->eo_u32[1], \
1046 uint32_t, (_eop)->eo_u32[0]); \
1047 _NOTE(CONSTANTCONDITION) \
1050 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1052 EFX_CHECK_REG((_enp), (_reg)); \
1053 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1054 uint32_t, (_index), \
1055 uint32_t, _reg ## _OFST, \
1056 uint32_t, (_eop)->eo_u32[3], \
1057 uint32_t, (_eop)->eo_u32[2], \
1058 uint32_t, (_eop)->eo_u32[1], \
1059 uint32_t, (_eop)->eo_u32[0]); \
1060 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1061 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1063 _NOTE(CONSTANTCONDITION) \
1067 * Accessors for memory BAR per-VI registers.
1069 * The VI window size is 8KB for Medford and all earlier controllers.
1070 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1073 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1075 EFX_CHECK_REG((_enp), (_reg)); \
1076 EFSYS_BAR_READD((_enp)->en_esbp, \
1077 ((_reg ## _OFST) + \
1078 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1080 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1081 uint32_t, (_index), \
1082 uint32_t, _reg ## _OFST, \
1083 uint32_t, (_edp)->ed_u32[0]); \
1084 _NOTE(CONSTANTCONDITION) \
1087 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1089 EFX_CHECK_REG((_enp), (_reg)); \
1090 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1091 uint32_t, (_index), \
1092 uint32_t, _reg ## _OFST, \
1093 uint32_t, (_edp)->ed_u32[0]); \
1094 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1095 ((_reg ## _OFST) + \
1096 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1098 _NOTE(CONSTANTCONDITION) \
1101 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1103 EFX_CHECK_REG((_enp), (_reg)); \
1104 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1105 uint32_t, (_index), \
1106 uint32_t, _reg ## _OFST, \
1107 uint32_t, (_edp)->ed_u32[0]); \
1108 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1109 ((_reg ## _OFST) + \
1110 (2 * sizeof (efx_dword_t)) + \
1111 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1113 _NOTE(CONSTANTCONDITION) \
1117 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1118 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1119 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1120 * the need for locking in the host, and are the only ones known to be safe to
1121 * use 128-bites write with.
1123 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1125 EFX_CHECK_REG((_enp), (_reg)); \
1126 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1127 const char *, #_reg, \
1128 uint32_t, (_index), \
1129 uint32_t, _reg ## _OFST, \
1130 uint32_t, (_eop)->eo_u32[3], \
1131 uint32_t, (_eop)->eo_u32[2], \
1132 uint32_t, (_eop)->eo_u32[1], \
1133 uint32_t, (_eop)->eo_u32[0]); \
1134 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1136 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1138 _NOTE(CONSTANTCONDITION) \
1141 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1143 unsigned int _new = (_wptr); \
1144 unsigned int _old = (_owptr); \
1146 if ((_new) >= (_old)) \
1147 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1148 (_old) * sizeof (efx_desc_t), \
1149 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1152 * It is cheaper to sync entire map than sync \
1153 * two parts especially when offset/size are \
1154 * ignored and entire map is synced in any case.\
1156 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1158 (_entries) * sizeof (efx_desc_t)); \
1159 _NOTE(CONSTANTCONDITION) \
1162 extern __checkReturn efx_rc_t
1164 __in efx_nic_t *enp);
1167 efx_mac_multicast_hash_compute(
1168 __in_ecount(6*count) uint8_t const *addrs,
1170 __out efx_oword_t *hash_low,
1171 __out efx_oword_t *hash_high);
1173 extern __checkReturn efx_rc_t
1175 __in efx_nic_t *enp);
1179 __in efx_nic_t *enp);
1183 /* VPD utility functions */
1185 extern __checkReturn efx_rc_t
1186 efx_vpd_hunk_length(
1187 __in_bcount(size) caddr_t data,
1189 __out size_t *lengthp);
1191 extern __checkReturn efx_rc_t
1192 efx_vpd_hunk_verify(
1193 __in_bcount(size) caddr_t data,
1195 __out_opt boolean_t *cksummedp);
1197 extern __checkReturn efx_rc_t
1198 efx_vpd_hunk_reinit(
1199 __in_bcount(size) caddr_t data,
1201 __in boolean_t wantpid);
1203 extern __checkReturn efx_rc_t
1205 __in_bcount(size) caddr_t data,
1207 __in efx_vpd_tag_t tag,
1208 __in efx_vpd_keyword_t keyword,
1209 __out unsigned int *payloadp,
1210 __out uint8_t *paylenp);
1212 extern __checkReturn efx_rc_t
1214 __in_bcount(size) caddr_t data,
1216 __out efx_vpd_tag_t *tagp,
1217 __out efx_vpd_keyword_t *keyword,
1218 __out_opt unsigned int *payloadp,
1219 __out_opt uint8_t *paylenp,
1220 __inout unsigned int *contp);
1222 extern __checkReturn efx_rc_t
1224 __in_bcount(size) caddr_t data,
1226 __in efx_vpd_value_t *evvp);
1228 #endif /* EFSYS_OPT_VPD */
1232 extern __checkReturn efx_rc_t
1233 efx_mcdi_set_workaround(
1234 __in efx_nic_t *enp,
1236 __in boolean_t enabled,
1237 __out_opt uint32_t *flagsp);
1239 extern __checkReturn efx_rc_t
1240 efx_mcdi_get_workarounds(
1241 __in efx_nic_t *enp,
1242 __out_opt uint32_t *implementedp,
1243 __out_opt uint32_t *enabledp);
1245 #endif /* EFSYS_OPT_MCDI */
1247 #if EFSYS_OPT_MAC_STATS
1250 * Closed range of stats (i.e. the first and the last are included).
1251 * The last must be greater or equal (if the range is one item only) to
1254 struct efx_mac_stats_range {
1255 efx_mac_stat_t first;
1256 efx_mac_stat_t last;
1260 efx_mac_stats_mask_add_ranges(
1261 __inout_bcount(mask_size) uint32_t *maskp,
1262 __in size_t mask_size,
1263 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1264 __in unsigned int rng_count);
1266 #endif /* EFSYS_OPT_MAC_STATS */
1272 #endif /* _SYS_EFX_IMPL_H */