2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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34 __checkReturn efx_rc_t
38 __out efx_family_t *efp)
40 if (venid == EFX_PCI_VENID_SFC) {
43 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
45 * Hardware default for PF0 of uninitialised Siena.
46 * manftest must be able to cope with this device id.
48 *efp = EFX_FAMILY_SIENA;
51 case EFX_PCI_DEVID_BETHPAGE:
52 case EFX_PCI_DEVID_SIENA:
53 *efp = EFX_FAMILY_SIENA;
55 #endif /* EFSYS_OPT_SIENA */
57 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
63 *efp = EFX_FAMILY_INVALID;
68 #define EFX_BIU_MAGIC0 0x01234567
69 #define EFX_BIU_MAGIC1 0xfedcba98
71 __checkReturn efx_rc_t
79 * Write magic values to scratch registers 0 and 1, then
80 * verify that the values were written correctly. Interleave
81 * the accesses to ensure that the BIU is not just reading
82 * back the cached value that was last written.
84 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
85 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
87 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
88 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
90 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
91 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
96 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
97 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
103 * Perform the same test, with the values swapped. This
104 * ensures that subsequent tests don't start with the correct
105 * values already written into the scratch registers.
107 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
108 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
110 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
111 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
113 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
114 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
119 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
120 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
134 EFSYS_PROBE1(fail1, efx_rc_t, rc);
141 static const efx_nic_ops_t __efx_nic_siena_ops = {
142 siena_nic_probe, /* eno_probe */
143 NULL, /* eno_board_cfg */
144 NULL, /* eno_set_drv_limits */
145 siena_nic_reset, /* eno_reset */
146 siena_nic_init, /* eno_init */
147 NULL, /* eno_get_vi_pool */
148 NULL, /* eno_get_bar_region */
149 siena_nic_fini, /* eno_fini */
150 siena_nic_unprobe, /* eno_unprobe */
153 #endif /* EFSYS_OPT_SIENA */
156 __checkReturn efx_rc_t
158 __in efx_family_t family,
159 __in efsys_identifier_t *esip,
160 __in efsys_bar_t *esbp,
161 __in efsys_lock_t *eslp,
162 __deref_out efx_nic_t **enpp)
167 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
168 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
170 /* Allocate a NIC object */
171 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
178 enp->en_magic = EFX_NIC_MAGIC;
182 case EFX_FAMILY_SIENA:
183 enp->en_enop = &__efx_nic_siena_ops;
186 EFX_FEATURE_LFSR_HASH_INSERT |
187 EFX_FEATURE_LINK_EVENTS |
188 EFX_FEATURE_PERIODIC_MAC_STATS |
190 EFX_FEATURE_LOOKAHEAD_SPLIT |
191 EFX_FEATURE_MAC_HEADER_FILTERS |
192 EFX_FEATURE_TX_SRC_FILTERS;
194 #endif /* EFSYS_OPT_SIENA */
201 enp->en_family = family;
215 /* Free the NIC object */
216 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
219 EFSYS_PROBE1(fail1, efx_rc_t, rc);
224 __checkReturn efx_rc_t
228 const efx_nic_ops_t *enop;
231 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
233 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
234 #endif /* EFSYS_OPT_MCDI */
235 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
238 if ((rc = enop->eno_probe(enp)) != 0)
241 if ((rc = efx_phy_probe(enp)) != 0)
244 enp->en_mod_flags |= EFX_MOD_PROBE;
251 enop->eno_unprobe(enp);
254 EFSYS_PROBE1(fail1, efx_rc_t, rc);
259 __checkReturn efx_rc_t
260 efx_nic_set_drv_limits(
261 __inout efx_nic_t *enp,
262 __in efx_drv_limits_t *edlp)
264 const efx_nic_ops_t *enop = enp->en_enop;
267 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
268 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
270 if (enop->eno_set_drv_limits != NULL) {
271 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
278 EFSYS_PROBE1(fail1, efx_rc_t, rc);
283 __checkReturn efx_rc_t
284 efx_nic_get_bar_region(
286 __in efx_nic_region_t region,
287 __out uint32_t *offsetp,
290 const efx_nic_ops_t *enop = enp->en_enop;
293 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
294 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
295 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
297 if (enop->eno_get_bar_region == NULL) {
301 if ((rc = (enop->eno_get_bar_region)(enp,
302 region, offsetp, sizep)) != 0) {
312 EFSYS_PROBE1(fail1, efx_rc_t, rc);
318 __checkReturn efx_rc_t
321 __out uint32_t *evq_countp,
322 __out uint32_t *rxq_countp,
323 __out uint32_t *txq_countp)
325 const efx_nic_ops_t *enop = enp->en_enop;
326 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
329 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
330 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
331 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
333 if (enop->eno_get_vi_pool != NULL) {
334 uint32_t vi_count = 0;
336 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
339 *evq_countp = vi_count;
340 *rxq_countp = vi_count;
341 *txq_countp = vi_count;
343 /* Use NIC limits as default value */
344 *evq_countp = encp->enc_evq_limit;
345 *rxq_countp = encp->enc_rxq_limit;
346 *txq_countp = encp->enc_txq_limit;
352 EFSYS_PROBE1(fail1, efx_rc_t, rc);
358 __checkReturn efx_rc_t
362 const efx_nic_ops_t *enop = enp->en_enop;
365 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
366 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
368 if (enp->en_mod_flags & EFX_MOD_NIC) {
373 if ((rc = enop->eno_init(enp)) != 0)
376 enp->en_mod_flags |= EFX_MOD_NIC;
383 EFSYS_PROBE1(fail1, efx_rc_t, rc);
392 const efx_nic_ops_t *enop = enp->en_enop;
394 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
395 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
396 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
397 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
398 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
399 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
400 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
404 enp->en_mod_flags &= ~EFX_MOD_NIC;
411 const efx_nic_ops_t *enop = enp->en_enop;
413 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
415 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
416 #endif /* EFSYS_OPT_MCDI */
417 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
418 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
419 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
420 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
421 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
422 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
424 efx_phy_unprobe(enp);
426 enop->eno_unprobe(enp);
428 enp->en_mod_flags &= ~EFX_MOD_PROBE;
435 efsys_identifier_t *esip = enp->en_esip;
437 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
438 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
440 enp->en_family = EFX_FAMILY_INVALID;
449 /* Free the NIC object */
450 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
453 __checkReturn efx_rc_t
457 const efx_nic_ops_t *enop = enp->en_enop;
458 unsigned int mod_flags;
461 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
462 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
464 * All modules except the MCDI, PROBE, NVRAM, VPD, MON
465 * (which we do not reset here) must have been shut down or never
468 * A rule of thumb here is: If the controller or MC reboots, is *any*
469 * state lost. If it's lost and needs reapplying, then the module
470 * *must* not be initialised during the reset.
472 mod_flags = enp->en_mod_flags;
473 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
474 EFX_MOD_VPD | EFX_MOD_MON);
475 EFSYS_ASSERT3U(mod_flags, ==, 0);
476 if (mod_flags != 0) {
481 if ((rc = enop->eno_reset(enp)) != 0)
489 EFSYS_PROBE1(fail1, efx_rc_t, rc);
494 const efx_nic_cfg_t *
498 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
500 return (&(enp->en_nic_cfg));
503 __checkReturn efx_rc_t
504 efx_nic_calculate_pcie_link_bandwidth(
505 __in uint32_t pcie_link_width,
506 __in uint32_t pcie_link_gen,
507 __out uint32_t *bandwidth_mbpsp)
509 uint32_t lane_bandwidth;
510 uint32_t total_bandwidth;
513 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
514 !ISP2(pcie_link_width)) {
519 switch (pcie_link_gen) {
520 case EFX_PCIE_LINK_SPEED_GEN1:
521 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
522 lane_bandwidth = 2000;
524 case EFX_PCIE_LINK_SPEED_GEN2:
525 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
526 lane_bandwidth = 4000;
528 case EFX_PCIE_LINK_SPEED_GEN3:
529 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
530 lane_bandwidth = 7877;
537 total_bandwidth = lane_bandwidth * pcie_link_width;
538 *bandwidth_mbpsp = total_bandwidth;
545 EFSYS_PROBE1(fail1, efx_rc_t, rc);
551 __checkReturn efx_rc_t
552 efx_nic_check_pcie_link_speed(
554 __in uint32_t pcie_link_width,
555 __in uint32_t pcie_link_gen,
556 __out efx_pcie_link_performance_t *resultp)
558 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
560 efx_pcie_link_performance_t result;
563 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
564 (pcie_link_width == 0) || (pcie_link_width == 32) ||
565 (pcie_link_gen == 0)) {
567 * No usable info on what is required and/or in use. In virtual
568 * machines, sometimes the PCIe link width is reported as 0 or
569 * 32, or the speed as 0.
571 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
575 /* Calculate the available bandwidth in megabits per second */
576 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
577 pcie_link_gen, &bandwidth);
581 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
582 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
583 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
584 /* The link provides enough bandwidth but not optimal latency */
585 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
587 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
596 EFSYS_PROBE1(fail1, efx_rc_t, rc);