1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_EF10_REGS_H
8 #define _SYS_EFX_EF10_REGS_H
14 /**************************************************************************
15 * NOTE: the line below marks the start of the autogenerated section
16 * EF10 registers and descriptors
18 **************************************************************************
22 * BIU_HW_REV_ID_REG(32bit):
26 #define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000
27 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
28 #define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face
31 #define ERF_DZ_HW_REV_ID_LBN 0
32 #define ERF_DZ_HW_REV_ID_WIDTH 32
36 * BIU_MC_SFT_STATUS_REG(32bit):
40 #define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010
41 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
42 #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4
43 #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8
44 #define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face
47 #define ERF_DZ_MC_SFT_STATUS_LBN 0
48 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32
52 * BIU_INT_ISR_REG(32bit):
56 #define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090
57 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
58 #define ER_DZ_BIU_INT_ISR_REG_RESET 0x0
61 #define ERF_DZ_ISR_REG_LBN 0
62 #define ERF_DZ_ISR_REG_WIDTH 32
66 * MC_DB_LWRD_REG(32bit):
70 #define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200
71 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
72 #define ER_DZ_MC_DB_LWRD_REG_RESET 0x0
75 #define ERF_DZ_MC_DOORBELL_L_LBN 0
76 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32
80 * MC_DB_HWRD_REG(32bit):
84 #define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204
85 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
86 #define ER_DZ_MC_DB_HWRD_REG_RESET 0x0
89 #define ERF_DZ_MC_DOORBELL_H_LBN 0
90 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32
94 * EVQ_RPTR_REG(32bit):
98 #define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400
99 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
100 #define ER_DZ_EVQ_RPTR_REG_STEP 8192
101 #define ER_DZ_EVQ_RPTR_REG_ROWS 2048
102 #define ER_DZ_EVQ_RPTR_REG_RESET 0x0
105 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15
106 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
107 #define ERF_DZ_EVQ_RPTR_LBN 0
108 #define ERF_DZ_EVQ_RPTR_WIDTH 15
112 * EVQ_RPTR_REG_64K(32bit):
116 #define ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400
117 /* medford2a0=pf_dbell_bar */
118 #define ER_FZ_EVQ_RPTR_REG_64K_STEP 65536
119 #define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048
120 #define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0
123 #define ERF_FZ_EVQ_RPTR_VLD_LBN 15
124 #define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1
125 #define ERF_FZ_EVQ_RPTR_LBN 0
126 #define ERF_FZ_EVQ_RPTR_WIDTH 15
130 * EVQ_RPTR_REG_16K(32bit):
134 #define ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400
135 /* medford2a0=pf_dbell_bar */
136 #define ER_FZ_EVQ_RPTR_REG_16K_STEP 16384
137 #define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048
138 #define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0
141 /* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */
142 /* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */
143 /* defined as ERF_FZ_EVQ_RPTR_LBN 0; */
144 /* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */
148 * EVQ_TMR_REG_64K(32bit):
152 #define ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420
153 /* medford2a0=pf_dbell_bar */
154 #define ER_FZ_EVQ_TMR_REG_64K_STEP 65536
155 #define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048
156 #define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0
159 #define ERF_FZ_TC_TIMER_MODE_LBN 14
160 #define ERF_FZ_TC_TIMER_MODE_WIDTH 2
161 #define ERF_FZ_TC_TIMER_VAL_LBN 0
162 #define ERF_FZ_TC_TIMER_VAL_WIDTH 14
166 * EVQ_TMR_REG_16K(32bit):
170 #define ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420
171 /* medford2a0=pf_dbell_bar */
172 #define ER_FZ_EVQ_TMR_REG_16K_STEP 16384
173 #define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048
174 #define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0
177 /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */
178 /* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */
179 /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */
180 /* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */
184 * EVQ_TMR_REG(32bit):
188 #define ER_DZ_EVQ_TMR_REG_OFST 0x00000420
189 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
190 #define ER_DZ_EVQ_TMR_REG_STEP 8192
191 #define ER_DZ_EVQ_TMR_REG_ROWS 2048
192 #define ER_DZ_EVQ_TMR_REG_RESET 0x0
195 #define ERF_DZ_TC_TIMER_MODE_LBN 14
196 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2
197 #define ERF_DZ_TC_TIMER_VAL_LBN 0
198 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14
202 * RX_DESC_UPD_REG_16K(32bit):
206 #define ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830
207 /* medford2a0=pf_dbell_bar */
208 #define ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384
209 #define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048
210 #define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0
213 #define ERF_FZ_RX_DESC_WPTR_LBN 0
214 #define ERF_FZ_RX_DESC_WPTR_WIDTH 12
218 * RX_DESC_UPD_REG(32bit):
222 #define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830
223 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
224 #define ER_DZ_RX_DESC_UPD_REG_STEP 8192
225 #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048
226 #define ER_DZ_RX_DESC_UPD_REG_RESET 0x0
229 #define ERF_DZ_RX_DESC_WPTR_LBN 0
230 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12
234 * RX_DESC_UPD_REG_64K(32bit):
238 #define ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830
239 /* medford2a0=pf_dbell_bar */
240 #define ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536
241 #define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048
242 #define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0
245 /* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */
246 /* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */
250 * TX_DESC_UPD_REG_64K(96bit):
254 #define ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10
255 /* medford2a0=pf_dbell_bar */
256 #define ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536
257 #define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048
258 #define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0
261 #define ERF_FZ_RSVD_LBN 76
262 #define ERF_FZ_RSVD_WIDTH 20
263 #define ERF_FZ_TX_DESC_WPTR_LBN 64
264 #define ERF_FZ_TX_DESC_WPTR_WIDTH 12
265 #define ERF_FZ_TX_DESC_HWORD_LBN 32
266 #define ERF_FZ_TX_DESC_HWORD_WIDTH 32
267 #define ERF_FZ_TX_DESC_LWORD_LBN 0
268 #define ERF_FZ_TX_DESC_LWORD_WIDTH 32
272 * TX_DESC_UPD_REG_16K(96bit):
276 #define ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10
277 /* medford2a0=pf_dbell_bar */
278 #define ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384
279 #define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048
280 #define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0
283 /* defined as ERF_FZ_RSVD_LBN 76; */
284 /* defined as ERF_FZ_RSVD_WIDTH 20 */
285 /* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */
286 /* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */
287 /* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */
288 /* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */
289 /* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */
290 /* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */
294 * TX_DESC_UPD_REG(96bit):
298 #define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10
299 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
300 #define ER_DZ_TX_DESC_UPD_REG_STEP 8192
301 #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048
302 #define ER_DZ_TX_DESC_UPD_REG_RESET 0x0
305 #define ERF_DZ_RSVD_LBN 76
306 #define ERF_DZ_RSVD_WIDTH 20
307 #define ERF_DZ_TX_DESC_WPTR_LBN 64
308 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12
309 #define ERF_DZ_TX_DESC_HWORD_LBN 32
310 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32
311 #define ERF_DZ_TX_DESC_LWORD_LBN 0
312 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32
316 #define ESF_DZ_DRV_CODE_LBN 60
317 #define ESF_DZ_DRV_CODE_WIDTH 4
318 #define ESF_DZ_DRV_SUB_CODE_LBN 56
319 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4
320 #define ESE_DZ_DRV_TIMER_EV 3
321 #define ESE_DZ_DRV_START_UP_EV 2
322 #define ESE_DZ_DRV_WAKE_UP_EV 1
323 #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0
324 #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32
325 #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32
326 #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24
327 #define ESF_DZ_DRV_SUB_DATA_LBN 0
328 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56
329 #define ESF_DZ_DRV_EVQ_ID_LBN 0
330 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14
331 #define ESF_DZ_DRV_TMR_ID_LBN 0
332 #define ESF_DZ_DRV_TMR_ID_WIDTH 14
336 #define ESF_DZ_EV_CODE_LBN 60
337 #define ESF_DZ_EV_CODE_WIDTH 4
338 #define ESE_DZ_EV_CODE_MCDI_EV 12
339 #define ESE_DZ_EV_CODE_DRIVER_EV 5
340 #define ESE_DZ_EV_CODE_TX_EV 2
341 #define ESE_DZ_EV_CODE_RX_EV 0
342 #define ESE_DZ_OTHER other
343 #define ESF_DZ_EV_DATA_DW0_LBN 0
344 #define ESF_DZ_EV_DATA_DW0_WIDTH 32
345 #define ESF_DZ_EV_DATA_DW1_LBN 32
346 #define ESF_DZ_EV_DATA_DW1_WIDTH 28
347 #define ESF_DZ_EV_DATA_LBN 0
348 #define ESF_DZ_EV_DATA_WIDTH 60
352 #define ESF_DZ_MC_CODE_LBN 60
353 #define ESF_DZ_MC_CODE_WIDTH 4
354 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59
355 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1
356 #define ESF_DZ_MC_DROP_EVENT_LBN 58
357 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1
358 #define ESF_DZ_MC_SOFT_DW0_LBN 0
359 #define ESF_DZ_MC_SOFT_DW0_WIDTH 32
360 #define ESF_DZ_MC_SOFT_DW1_LBN 32
361 #define ESF_DZ_MC_SOFT_DW1_WIDTH 26
362 #define ESF_DZ_MC_SOFT_LBN 0
363 #define ESF_DZ_MC_SOFT_WIDTH 58
367 #define ESF_DZ_RX_CODE_LBN 60
368 #define ESF_DZ_RX_CODE_WIDTH 4
369 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59
370 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1
371 #define ESF_DZ_RX_DROP_EVENT_LBN 58
372 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1
373 #define ESF_DD_RX_EV_RSVD2_LBN 54
374 #define ESF_DD_RX_EV_RSVD2_WIDTH 4
375 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57
376 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1
377 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56
378 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1
379 #define ESF_EZ_RX_EV_RSVD2_LBN 54
380 #define ESF_EZ_RX_EV_RSVD2_WIDTH 2
381 #define ESF_DZ_RX_EV_SOFT2_LBN 52
382 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2
383 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
384 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
385 #define ESF_DE_RX_L4_CLASS_LBN 45
386 #define ESF_DE_RX_L4_CLASS_WIDTH 3
387 #define ESE_DE_L4_CLASS_RSVD7 7
388 #define ESE_DE_L4_CLASS_RSVD6 6
389 #define ESE_DE_L4_CLASS_RSVD5 5
390 #define ESE_DE_L4_CLASS_RSVD4 4
391 #define ESE_DE_L4_CLASS_RSVD3 3
392 #define ESE_DE_L4_CLASS_UDP 2
393 #define ESE_DE_L4_CLASS_TCP 1
394 #define ESE_DE_L4_CLASS_UNKNOWN 0
395 #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47
396 #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1
397 #define ESF_FZ_RX_L4_CLASS_LBN 45
398 #define ESF_FZ_RX_L4_CLASS_WIDTH 2
399 #define ESE_FZ_L4_CLASS_RSVD3 3
400 #define ESE_FZ_L4_CLASS_UDP 2
401 #define ESE_FZ_L4_CLASS_TCP 1
402 #define ESE_FZ_L4_CLASS_UNKNOWN 0
403 #define ESF_DZ_RX_L3_CLASS_LBN 42
404 #define ESF_DZ_RX_L3_CLASS_WIDTH 3
405 #define ESE_DZ_L3_CLASS_RSVD7 7
406 #define ESE_DZ_L3_CLASS_IP6_FRAG 6
407 #define ESE_DZ_L3_CLASS_ARP 5
408 #define ESE_DZ_L3_CLASS_IP4_FRAG 4
409 #define ESE_DZ_L3_CLASS_FCOE 3
410 #define ESE_DZ_L3_CLASS_IP6 2
411 #define ESE_DZ_L3_CLASS_IP4 1
412 #define ESE_DZ_L3_CLASS_UNKNOWN 0
413 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39
414 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3
415 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7
416 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6
417 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5
418 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4
419 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3
420 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2
421 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1
422 #define ESE_DZ_ETH_TAG_CLASS_NONE 0
423 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36
424 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3
425 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2
426 #define ESE_DZ_ETH_BASE_CLASS_LLC 1
427 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0
428 #define ESF_DZ_RX_MAC_CLASS_LBN 35
429 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1
430 #define ESE_DZ_MAC_CLASS_MCAST 1
431 #define ESE_DZ_MAC_CLASS_UCAST 0
432 #define ESF_DD_RX_EV_SOFT1_LBN 32
433 #define ESF_DD_RX_EV_SOFT1_WIDTH 3
434 #define ESF_EZ_RX_EV_SOFT1_LBN 34
435 #define ESF_EZ_RX_EV_SOFT1_WIDTH 1
436 #define ESF_EZ_RX_ENCAP_HDR_LBN 32
437 #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2
438 #define ESE_EZ_ENCAP_HDR_GRE 2
439 #define ESE_EZ_ENCAP_HDR_VXLAN 1
440 #define ESE_EZ_ENCAP_HDR_NONE 0
441 #define ESF_DD_RX_EV_RSVD1_LBN 30
442 #define ESF_DD_RX_EV_RSVD1_WIDTH 2
443 #define ESF_EZ_RX_EV_RSVD1_LBN 31
444 #define ESF_EZ_RX_EV_RSVD1_WIDTH 1
445 #define ESF_EZ_RX_ABORT_LBN 30
446 #define ESF_EZ_RX_ABORT_WIDTH 1
447 #define ESF_DZ_RX_ECC_ERR_LBN 29
448 #define ESF_DZ_RX_ECC_ERR_WIDTH 1
449 #define ESF_DZ_RX_CRC1_ERR_LBN 28
450 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1
451 #define ESF_DZ_RX_CRC0_ERR_LBN 27
452 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1
453 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26
454 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1
455 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25
456 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1
457 #define ESF_DZ_RX_ECRC_ERR_LBN 24
458 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1
459 #define ESF_DZ_RX_QLABEL_LBN 16
460 #define ESF_DZ_RX_QLABEL_WIDTH 5
461 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15
462 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1
463 #define ESF_DZ_RX_CONT_LBN 14
464 #define ESF_DZ_RX_CONT_WIDTH 1
465 #define ESF_DZ_RX_BYTES_LBN 0
466 #define ESF_DZ_RX_BYTES_WIDTH 14
470 #define ESF_DZ_RX_KER_RESERVED_LBN 62
471 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2
472 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48
473 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14
474 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0
475 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32
476 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32
477 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16
478 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0
479 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48
482 /* ES_TX_CSUM_TSTAMP_DESC */
483 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
484 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
485 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
486 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
487 #define ESE_DZ_TX_OPTION_DESC_TSO 7
488 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
489 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
490 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8
491 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1
492 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7
493 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1
494 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6
495 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1
496 #define ESF_DZ_TX_TIMESTAMP_LBN 5
497 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1
498 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
499 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
500 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
501 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
502 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
503 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
504 #define ESE_DZ_TX_OPTION_CRC_FCOE 1
505 #define ESE_DZ_TX_OPTION_CRC_OFF 0
506 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
507 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
508 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
509 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
513 #define ESF_DZ_TX_CODE_LBN 60
514 #define ESF_DZ_TX_CODE_WIDTH 4
515 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59
516 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1
517 #define ESF_DZ_TX_DROP_EVENT_LBN 58
518 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1
519 #define ESF_DD_TX_EV_RSVD_LBN 48
520 #define ESF_DD_TX_EV_RSVD_WIDTH 10
521 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57
522 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1
523 #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56
524 #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1
525 #define ESF_EZ_TX_EV_RSVD_LBN 48
526 #define ESF_EZ_TX_EV_RSVD_WIDTH 8
527 #define ESF_DZ_TX_SOFT2_LBN 32
528 #define ESF_DZ_TX_SOFT2_WIDTH 16
529 #define ESF_DD_TX_SOFT1_LBN 24
530 #define ESF_DD_TX_SOFT1_WIDTH 8
531 #define ESF_EZ_TX_CAN_MERGE_LBN 31
532 #define ESF_EZ_TX_CAN_MERGE_WIDTH 1
533 #define ESF_EZ_TX_SOFT1_LBN 24
534 #define ESF_EZ_TX_SOFT1_WIDTH 7
535 #define ESF_DZ_TX_QLABEL_LBN 16
536 #define ESF_DZ_TX_QLABEL_WIDTH 5
537 #define ESF_DZ_TX_DESCR_INDX_LBN 0
538 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16
542 #define ESF_DZ_TX_KER_TYPE_LBN 63
543 #define ESF_DZ_TX_KER_TYPE_WIDTH 1
544 #define ESF_DZ_TX_KER_CONT_LBN 62
545 #define ESF_DZ_TX_KER_CONT_WIDTH 1
546 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48
547 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14
548 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0
549 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32
550 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32
551 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16
552 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0
553 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
557 #define ESF_DZ_TX_PIO_TYPE_LBN 63
558 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1
559 #define ESF_DZ_TX_PIO_OPT_LBN 60
560 #define ESF_DZ_TX_PIO_OPT_WIDTH 3
561 #define ESF_DZ_TX_PIO_CONT_LBN 59
562 #define ESF_DZ_TX_PIO_CONT_WIDTH 1
563 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32
564 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12
565 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
566 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
570 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
571 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
572 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
573 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
574 #define ESE_DZ_TX_OPTION_DESC_TSO 7
575 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
576 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
577 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
578 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
579 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
580 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
581 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
582 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
583 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
584 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8
585 #define ESF_DZ_TX_TSO_IP_ID_LBN 32
586 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16
587 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
588 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
591 /* ES_TX_TSO_V2_DESC_A */
592 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
593 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
594 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
595 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
596 #define ESE_DZ_TX_OPTION_DESC_TSO 7
597 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
598 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
599 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
600 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
601 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
602 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
603 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
604 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
605 #define ESF_DZ_TX_TSO_IP_ID_LBN 32
606 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16
607 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
608 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
611 /* ES_TX_TSO_V2_DESC_B */
612 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
613 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
614 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
615 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
616 #define ESE_DZ_TX_OPTION_DESC_TSO 7
617 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
618 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
619 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
620 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
621 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
622 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
623 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
624 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
625 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32
626 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16
627 #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0
628 #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16
631 /* ES_TX_VLAN_DESC */
632 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63
633 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
634 #define ESF_DZ_TX_OPTION_TYPE_LBN 60
635 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
636 #define ESE_DZ_TX_OPTION_DESC_TSO 7
637 #define ESE_DZ_TX_OPTION_DESC_VLAN 6
638 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
639 #define ESF_DZ_TX_VLAN_OP_LBN 32
640 #define ESF_DZ_TX_VLAN_OP_WIDTH 2
641 #define ESF_DZ_TX_VLAN_TAG2_LBN 16
642 #define ESF_DZ_TX_VLAN_TAG2_WIDTH 16
643 #define ESF_DZ_TX_VLAN_TAG1_LBN 0
644 #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16
647 /*************************************************************************
648 * NOTE: the comment line above marks the end of the autogenerated section
652 * The workaround for bug 35388 requires multiplexing writes through
653 * the ERF_DZ_TX_DESC_WPTR address.
654 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost)
655 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits)
656 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost)
658 #define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4)
659 #define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP
660 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8
661 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4
662 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8
663 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9
664 #define ERF_DD_EVQ_IND_RPTR_LBN 0
665 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8
666 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10
667 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2
668 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3
669 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8
670 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2
671 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0
672 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8
674 /* Packed stream magic doorbell command */
675 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_LBN 11
676 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_WIDTH 1
678 #define ERF_DZ_RX_DESC_MAGIC_CMD_LBN 8
679 #define ERF_DZ_RX_DESC_MAGIC_CMD_WIDTH 3
680 #define ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS 0
682 #define ERF_DZ_RX_DESC_MAGIC_DATA_LBN 0
683 #define ERF_DZ_RX_DESC_MAGIC_DATA_WIDTH 8
685 /* Packed stream RX packet prefix */
686 #define ES_DZ_PS_RX_PREFIX_TSTAMP_LBN 0
687 #define ES_DZ_PS_RX_PREFIX_TSTAMP_WIDTH 32
688 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_LBN 32
689 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_WIDTH 16
690 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_LBN 48
691 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_WIDTH 16
694 * An extra flag for the packed stream mode,
695 * signalling the start of a new buffer
697 #define ESF_DZ_RX_EV_ROTATE_LBN 53
698 #define ESF_DZ_RX_EV_ROTATE_WIDTH 1
704 #endif /* _SYS_EFX_EF10_REGS_H */