4 * Copyright (c) 2016 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "efx_types.h"
40 #include "efx_regs_ef10.h"
42 #include "sfc_dp_tx.h"
43 #include "sfc_tweak.h"
44 #include "sfc_kvargs.h"
47 #define sfc_ef10_tx_err(dpq, ...) \
48 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
50 /** Maximum length of the DMA descriptor data */
51 #define SFC_EF10_TX_DMA_DESC_LEN_MAX \
52 ((1u << ESF_DZ_TX_KER_BYTE_CNT_WIDTH) - 1)
55 * Maximum number of descriptors/buffers in the Tx ring.
56 * It should guarantee that corresponding event queue never overfill.
57 * EF10 native datapath uses event queue of the same size as Tx queue.
58 * Maximum number of events on datapath can be estimated as number of
59 * Tx queue entries (one event per Tx buffer in the worst case) plus
60 * Tx error and flush events.
62 #define SFC_EF10_TXQ_LIMIT(_ndesc) \
63 ((_ndesc) - 1 /* head must not step on tail */ - \
64 (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
65 1 /* Rx error */ - 1 /* flush */)
67 struct sfc_ef10_tx_sw_desc {
68 struct rte_mbuf *mbuf;
73 #define SFC_EF10_TXQ_STARTED 0x1
74 #define SFC_EF10_TXQ_NOT_RUNNING 0x2
75 #define SFC_EF10_TXQ_EXCEPTION 0x4
77 unsigned int ptr_mask;
79 unsigned int completed;
80 unsigned int free_thresh;
81 unsigned int evq_read_ptr;
82 struct sfc_ef10_tx_sw_desc *sw_ring;
83 efx_qword_t *txq_hw_ring;
84 volatile void *doorbell;
85 efx_qword_t *evq_hw_ring;
87 /* Datapath transmit queue anchor */
91 static inline struct sfc_ef10_txq *
92 sfc_ef10_txq_by_dp_txq(struct sfc_dp_txq *dp_txq)
94 return container_of(dp_txq, struct sfc_ef10_txq, dp);
98 sfc_ef10_tx_get_event(struct sfc_ef10_txq *txq, efx_qword_t *tx_ev)
100 volatile efx_qword_t *evq_hw_ring = txq->evq_hw_ring;
103 * Exception flag is set when reap is done.
104 * It is never done twice per packet burst get and absence of
105 * the flag is checked on burst get entry.
107 SFC_ASSERT((txq->flags & SFC_EF10_TXQ_EXCEPTION) == 0);
109 *tx_ev = evq_hw_ring[txq->evq_read_ptr & txq->ptr_mask];
111 if (!sfc_ef10_ev_present(*tx_ev))
114 if (unlikely(EFX_QWORD_FIELD(*tx_ev, FSF_AZ_EV_CODE) !=
115 FSE_AZ_EV_CODE_TX_EV)) {
117 * Do not move read_ptr to keep the event for exception
118 * handling by the control path.
120 txq->flags |= SFC_EF10_TXQ_EXCEPTION;
121 sfc_ef10_tx_err(&txq->dp.dpq,
122 "TxQ exception at EvQ read ptr %#x",
132 sfc_ef10_tx_reap(struct sfc_ef10_txq *txq)
134 const unsigned int old_read_ptr = txq->evq_read_ptr;
135 const unsigned int ptr_mask = txq->ptr_mask;
136 unsigned int completed = txq->completed;
137 unsigned int pending = completed;
138 const unsigned int curr_done = pending - 1;
139 unsigned int anew_done = curr_done;
142 while (sfc_ef10_tx_get_event(txq, &tx_ev)) {
144 * DROP_EVENT is an internal to the NIC, software should
145 * never see it and, therefore, may ignore it.
148 /* Update the latest done descriptor */
149 anew_done = EFX_QWORD_FIELD(tx_ev, ESF_DZ_TX_DESCR_INDX);
151 pending += (anew_done - curr_done) & ptr_mask;
153 if (pending != completed) {
155 struct sfc_ef10_tx_sw_desc *txd;
157 txd = &txq->sw_ring[completed & ptr_mask];
159 if (txd->mbuf != NULL) {
160 rte_pktmbuf_free(txd->mbuf);
163 } while (++completed != pending);
165 txq->completed = completed;
168 sfc_ef10_ev_qclear(txq->evq_hw_ring, ptr_mask, old_read_ptr,
173 sfc_ef10_tx_qdesc_dma_create(phys_addr_t addr, uint16_t size, bool eop,
176 EFX_POPULATE_QWORD_4(*edp,
177 ESF_DZ_TX_KER_TYPE, 0,
178 ESF_DZ_TX_KER_CONT, !eop,
179 ESF_DZ_TX_KER_BYTE_CNT, size,
180 ESF_DZ_TX_KER_BUF_ADDR, addr);
184 sfc_ef10_tx_qpush(struct sfc_ef10_txq *txq, unsigned int added,
191 * This improves performance by pushing a TX descriptor at the same
192 * time as the doorbell. The descriptor must be added to the TXQ,
193 * so that can be used if the hardware decides not to use the pushed
196 desc.eq_u64[0] = txq->txq_hw_ring[pushed & txq->ptr_mask].eq_u64[0];
197 EFX_POPULATE_OWORD_3(oword,
198 ERF_DZ_TX_DESC_WPTR, added & txq->ptr_mask,
199 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
200 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
202 /* DMA sync to device is not required */
205 * rte_io_wmb() which guarantees that the STORE operations
206 * (i.e. Tx and event descriptor updates) that precede
207 * the rte_io_wmb() call are visible to NIC before the STORE
208 * operations that follow it (i.e. doorbell write).
212 *(volatile __m128i *)txq->doorbell = oword.eo_u128[0];
216 sfc_ef10_tx_pkt_descs_max(const struct rte_mbuf *m)
218 unsigned int extra_descs_per_seg;
219 unsigned int extra_descs_per_pkt;
222 * VLAN offload is not supported yet, so no extra descriptors
223 * are required for VLAN option descriptor.
226 /** Maximum length of the mbuf segment data */
227 #define SFC_MBUF_SEG_LEN_MAX UINT16_MAX
228 RTE_BUILD_BUG_ON(sizeof(m->data_len) != 2);
231 * Each segment is already counted once below. So, calculate
232 * how many extra DMA descriptors may be required per segment in
233 * the worst case because of maximum DMA descriptor length limit.
234 * If maximum segment length is less or equal to maximum DMA
235 * descriptor length, no extra DMA descriptors are required.
237 extra_descs_per_seg =
238 (SFC_MBUF_SEG_LEN_MAX - 1) / SFC_EF10_TX_DMA_DESC_LEN_MAX;
240 /** Maximum length of the packet */
241 #define SFC_MBUF_PKT_LEN_MAX UINT32_MAX
242 RTE_BUILD_BUG_ON(sizeof(m->pkt_len) != 4);
245 * One more limitation on maximum number of extra DMA descriptors
246 * comes from slicing entire packet because of DMA descriptor length
247 * limit taking into account that there is at least one segment
248 * which is already counted below (so division of the maximum
249 * packet length minus one with round down).
250 * TSO is not supported yet, so packet length is limited by
253 extra_descs_per_pkt =
254 (RTE_MIN((unsigned int)EFX_MAC_PDU_MAX,
255 SFC_MBUF_PKT_LEN_MAX) - 1) /
256 SFC_EF10_TX_DMA_DESC_LEN_MAX;
258 return m->nb_segs + RTE_MIN(m->nb_segs * extra_descs_per_seg,
259 extra_descs_per_pkt);
263 sfc_ef10_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
265 struct sfc_ef10_txq * const txq = sfc_ef10_txq_by_dp_txq(tx_queue);
266 unsigned int ptr_mask;
268 unsigned int dma_desc_space;
270 struct rte_mbuf **pktp;
271 struct rte_mbuf **pktp_end;
273 if (unlikely(txq->flags &
274 (SFC_EF10_TXQ_NOT_RUNNING | SFC_EF10_TXQ_EXCEPTION)))
277 ptr_mask = txq->ptr_mask;
279 dma_desc_space = SFC_EF10_TXQ_LIMIT(ptr_mask + 1) -
280 (added - txq->completed);
282 reap_done = (dma_desc_space < txq->free_thresh);
284 sfc_ef10_tx_reap(txq);
285 dma_desc_space = SFC_EF10_TXQ_LIMIT(ptr_mask + 1) -
286 (added - txq->completed);
289 for (pktp = &tx_pkts[0], pktp_end = &tx_pkts[nb_pkts];
292 struct rte_mbuf *m_seg = *pktp;
293 unsigned int pkt_start = added;
296 if (likely(pktp + 1 != pktp_end))
297 rte_mbuf_prefetch_part1(pktp[1]);
299 if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space) {
303 /* Push already prepared descriptors before polling */
304 if (added != txq->added) {
305 sfc_ef10_tx_qpush(txq, added, txq->added);
309 sfc_ef10_tx_reap(txq);
311 dma_desc_space = SFC_EF10_TXQ_LIMIT(ptr_mask + 1) -
312 (added - txq->completed);
313 if (sfc_ef10_tx_pkt_descs_max(m_seg) > dma_desc_space)
317 pkt_len = m_seg->pkt_len;
319 phys_addr_t seg_addr = rte_mbuf_data_dma_addr(m_seg);
320 unsigned int seg_len = rte_pktmbuf_data_len(m_seg);
322 SFC_ASSERT(seg_len <= SFC_EF10_TX_DMA_DESC_LEN_MAX);
326 sfc_ef10_tx_qdesc_dma_create(seg_addr,
327 seg_len, (pkt_len == 0),
328 &txq->txq_hw_ring[added & ptr_mask]);
331 } while ((m_seg = m_seg->next) != 0);
333 dma_desc_space -= (added - pkt_start);
335 /* Assign mbuf to the last used desc */
336 txq->sw_ring[(added - 1) & ptr_mask].mbuf = *pktp;
339 if (likely(added != txq->added)) {
340 sfc_ef10_tx_qpush(txq, added, txq->added);
344 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
346 sfc_ef10_tx_reap(txq);
349 return pktp - &tx_pkts[0];
353 sfc_ef10_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
356 struct sfc_ef10_txq * const txq = sfc_ef10_txq_by_dp_txq(tx_queue);
357 unsigned int ptr_mask;
359 unsigned int dma_desc_space;
361 struct rte_mbuf **pktp;
362 struct rte_mbuf **pktp_end;
364 if (unlikely(txq->flags &
365 (SFC_EF10_TXQ_NOT_RUNNING | SFC_EF10_TXQ_EXCEPTION)))
368 ptr_mask = txq->ptr_mask;
370 dma_desc_space = SFC_EF10_TXQ_LIMIT(ptr_mask + 1) -
371 (added - txq->completed);
373 reap_done = (dma_desc_space < RTE_MAX(txq->free_thresh, nb_pkts));
375 sfc_ef10_tx_reap(txq);
376 dma_desc_space = SFC_EF10_TXQ_LIMIT(ptr_mask + 1) -
377 (added - txq->completed);
380 pktp_end = &tx_pkts[MIN(nb_pkts, dma_desc_space)];
381 for (pktp = &tx_pkts[0]; pktp != pktp_end; ++pktp) {
382 struct rte_mbuf *pkt = *pktp;
383 unsigned int id = added & ptr_mask;
385 SFC_ASSERT(rte_pktmbuf_data_len(pkt) <=
386 SFC_EF10_TX_DMA_DESC_LEN_MAX);
388 sfc_ef10_tx_qdesc_dma_create(rte_mbuf_data_dma_addr(pkt),
389 rte_pktmbuf_data_len(pkt),
390 true, &txq->txq_hw_ring[id]);
392 txq->sw_ring[id].mbuf = pkt;
397 if (likely(added != txq->added)) {
398 sfc_ef10_tx_qpush(txq, added, txq->added);
402 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
404 sfc_ef10_tx_reap(txq);
407 return pktp - &tx_pkts[0];
411 static sfc_dp_tx_qcreate_t sfc_ef10_tx_qcreate;
413 sfc_ef10_tx_qcreate(uint16_t port_id, uint16_t queue_id,
414 const struct rte_pci_addr *pci_addr, int socket_id,
415 const struct sfc_dp_tx_qcreate_info *info,
416 struct sfc_dp_txq **dp_txqp)
418 struct sfc_ef10_txq *txq;
422 if (info->txq_entries != info->evq_entries)
426 txq = rte_zmalloc_socket("sfc-ef10-txq", sizeof(*txq),
427 RTE_CACHE_LINE_SIZE, socket_id);
431 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
434 txq->sw_ring = rte_calloc_socket("sfc-ef10-txq-sw_ring",
436 sizeof(*txq->sw_ring),
437 RTE_CACHE_LINE_SIZE, socket_id);
438 if (txq->sw_ring == NULL)
439 goto fail_sw_ring_alloc;
441 txq->flags = SFC_EF10_TXQ_NOT_RUNNING;
442 txq->ptr_mask = info->txq_entries - 1;
443 txq->free_thresh = info->free_thresh;
444 txq->txq_hw_ring = info->txq_hw_ring;
445 txq->doorbell = (volatile uint8_t *)info->mem_bar +
446 ER_DZ_TX_DESC_UPD_REG_OFST +
447 info->hw_index * ER_DZ_TX_DESC_UPD_REG_STEP;
448 txq->evq_hw_ring = info->evq_hw_ring;
461 static sfc_dp_tx_qdestroy_t sfc_ef10_tx_qdestroy;
463 sfc_ef10_tx_qdestroy(struct sfc_dp_txq *dp_txq)
465 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
467 rte_free(txq->sw_ring);
471 static sfc_dp_tx_qstart_t sfc_ef10_tx_qstart;
473 sfc_ef10_tx_qstart(struct sfc_dp_txq *dp_txq, unsigned int evq_read_ptr,
474 unsigned int txq_desc_index)
476 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
478 txq->evq_read_ptr = evq_read_ptr;
479 txq->added = txq->completed = txq_desc_index;
481 txq->flags |= SFC_EF10_TXQ_STARTED;
482 txq->flags &= ~(SFC_EF10_TXQ_NOT_RUNNING | SFC_EF10_TXQ_EXCEPTION);
487 static sfc_dp_tx_qstop_t sfc_ef10_tx_qstop;
489 sfc_ef10_tx_qstop(struct sfc_dp_txq *dp_txq, unsigned int *evq_read_ptr)
491 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
493 txq->flags |= SFC_EF10_TXQ_NOT_RUNNING;
495 *evq_read_ptr = txq->evq_read_ptr;
498 static sfc_dp_tx_qtx_ev_t sfc_ef10_tx_qtx_ev;
500 sfc_ef10_tx_qtx_ev(struct sfc_dp_txq *dp_txq, __rte_unused unsigned int id)
502 __rte_unused struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
504 SFC_ASSERT(txq->flags & SFC_EF10_TXQ_NOT_RUNNING);
507 * It is safe to ignore Tx event since we reap all mbufs on
508 * queue purge anyway.
514 static sfc_dp_tx_qreap_t sfc_ef10_tx_qreap;
516 sfc_ef10_tx_qreap(struct sfc_dp_txq *dp_txq)
518 struct sfc_ef10_txq *txq = sfc_ef10_txq_by_dp_txq(dp_txq);
521 for (txds = 0; txds <= txq->ptr_mask; ++txds) {
522 if (txq->sw_ring[txds].mbuf != NULL) {
523 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
524 txq->sw_ring[txds].mbuf = NULL;
528 txq->flags &= ~SFC_EF10_TXQ_STARTED;
531 struct sfc_dp_tx sfc_ef10_tx = {
533 .name = SFC_KVARG_DATAPATH_EF10,
535 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF10,
537 .features = SFC_DP_TX_FEAT_MULTI_SEG |
538 SFC_DP_TX_FEAT_MULTI_PROCESS,
539 .qcreate = sfc_ef10_tx_qcreate,
540 .qdestroy = sfc_ef10_tx_qdestroy,
541 .qstart = sfc_ef10_tx_qstart,
542 .qtx_ev = sfc_ef10_tx_qtx_ev,
543 .qstop = sfc_ef10_tx_qstop,
544 .qreap = sfc_ef10_tx_qreap,
545 .pkt_burst = sfc_ef10_xmit_pkts,
548 struct sfc_dp_tx sfc_ef10_simple_tx = {
550 .name = SFC_KVARG_DATAPATH_EF10_SIMPLE,
553 .features = SFC_DP_TX_FEAT_MULTI_PROCESS,
554 .qcreate = sfc_ef10_tx_qcreate,
555 .qdestroy = sfc_ef10_tx_qdestroy,
556 .qstart = sfc_ef10_tx_qstart,
557 .qtx_ev = sfc_ef10_tx_qtx_ev,
558 .qstop = sfc_ef10_tx_qstop,
559 .qreap = sfc_ef10_tx_qreap,
560 .pkt_burst = sfc_ef10_simple_xmit_pkts,