4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "sfc_debug.h"
37 #include "sfc_tweak.h"
38 #include "sfc_kvargs.h"
41 * Maximum number of TX queue flush attempts in case of
42 * failure or flush timeout
44 #define SFC_TX_QFLUSH_ATTEMPTS (3)
47 * Time to wait between event queue polling attempts when waiting for TX
48 * queue flush done or flush failed events
50 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
53 * Maximum number of event queue polling attempts when waiting for TX queue
54 * flush done or flush failed events; it defines TX queue flush attempt timeout
55 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
57 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
60 sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc,
61 const struct rte_eth_txconf *tx_conf)
63 unsigned int flags = tx_conf->txq_flags;
64 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
67 if (tx_conf->tx_rs_thresh != 0) {
68 sfc_err(sa, "RS bit in transmit descriptor is not supported");
72 if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) {
74 "TxQ free threshold too large: %u vs maximum %u",
75 tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc));
79 if (tx_conf->tx_thresh.pthresh != 0 ||
80 tx_conf->tx_thresh.hthresh != 0 ||
81 tx_conf->tx_thresh.wthresh != 0) {
83 "prefetch/host/writeback thresholds are not supported");
87 if (((flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) &&
88 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)) {
89 sfc_err(sa, "Multi-segment is not supported by %s datapath",
94 if ((flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
95 if (!encp->enc_hw_tx_insert_vlan_enabled) {
96 sfc_err(sa, "VLAN offload is not supported");
98 } else if (~sa->dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) {
100 "VLAN offload is not supported by %s datapath",
106 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
107 sfc_err(sa, "SCTP offload is not supported");
111 /* We either perform both TCP and UDP offload, or no offload at all */
112 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
113 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
114 sfc_err(sa, "TCP and UDP offloads can't be set independently");
122 sfc_tx_qflush_done(struct sfc_txq *txq)
124 txq->state |= SFC_TXQ_FLUSHED;
125 txq->state &= ~SFC_TXQ_FLUSHING;
129 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
130 uint16_t nb_tx_desc, unsigned int socket_id,
131 const struct rte_eth_txconf *tx_conf)
133 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
134 struct sfc_txq_info *txq_info;
137 unsigned int evq_index = sfc_evq_index_by_txq_sw_index(sa, sw_index);
139 struct sfc_dp_tx_qcreate_info info;
141 sfc_log_init(sa, "TxQ = %u", sw_index);
143 rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf);
147 SFC_ASSERT(sw_index < sa->txq_count);
148 txq_info = &sa->txq_info[sw_index];
150 SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries);
151 txq_info->entries = nb_tx_desc;
153 rc = sfc_ev_qinit(sa, evq_index, txq_info->entries, socket_id);
157 evq = sa->evq_info[evq_index].evq;
160 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
166 txq->hw_index = sw_index;
169 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
170 SFC_TX_DEFAULT_FREE_THRESH;
171 txq->flags = tx_conf->txq_flags;
173 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
174 socket_id, &txq->mem);
178 memset(&info, 0, sizeof(info));
179 info.free_thresh = txq->free_thresh;
180 info.flags = tx_conf->txq_flags;
181 info.txq_entries = txq_info->entries;
182 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
183 info.txq_hw_ring = txq->mem.esm_base;
184 info.evq_entries = txq_info->entries;
185 info.evq_hw_ring = evq->mem.esm_base;
186 info.hw_index = txq->hw_index;
187 info.mem_bar = sa->mem_bar.esb_base;
189 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
190 &SFC_DEV_TO_PCI(sa->eth_dev)->addr,
191 socket_id, &info, &txq->dp);
193 goto fail_dp_tx_qinit;
195 evq->dp_txq = txq->dp;
197 txq->state = SFC_TXQ_INITIALIZED;
199 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
204 sfc_dma_free(sa, &txq->mem);
207 txq_info->txq = NULL;
211 sfc_ev_qfini(sa, evq_index);
214 txq_info->entries = 0;
217 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
222 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
224 struct sfc_txq_info *txq_info;
227 sfc_log_init(sa, "TxQ = %u", sw_index);
229 SFC_ASSERT(sw_index < sa->txq_count);
230 txq_info = &sa->txq_info[sw_index];
233 SFC_ASSERT(txq != NULL);
234 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
236 sa->dp_tx->qdestroy(txq->dp);
239 txq_info->txq = NULL;
240 txq_info->entries = 0;
242 sfc_dma_free(sa, &txq->mem);
245 sfc_ev_qfini(sa, sfc_evq_index_by_txq_sw_index(sa, sw_index));
249 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
251 sfc_log_init(sa, "TxQ = %u", sw_index);
257 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
261 switch (txmode->mq_mode) {
265 sfc_err(sa, "Tx multi-queue mode %u not supported",
271 * These features are claimed to be i40e-specific,
272 * but it does make sense to double-check their absence
274 if (txmode->hw_vlan_reject_tagged) {
275 sfc_err(sa, "Rejecting tagged packets not supported");
279 if (txmode->hw_vlan_reject_untagged) {
280 sfc_err(sa, "Rejecting untagged packets not supported");
284 if (txmode->hw_vlan_insert_pvid) {
285 sfc_err(sa, "Port-based VLAN insertion not supported");
293 sfc_tx_init(struct sfc_adapter *sa)
295 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
296 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
297 unsigned int sw_index;
301 * The datapath implementation assumes absence of boundary
302 * limits on Tx DMA descriptors. Addition of these checks on
303 * datapath would simply make the datapath slower.
305 if (encp->enc_tx_dma_desc_boundary != 0) {
307 goto fail_tx_dma_desc_boundary;
310 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
312 goto fail_check_mode;
314 sa->txq_count = sa->eth_dev->data->nb_tx_queues;
316 sa->txq_info = rte_calloc_socket("sfc-txqs", sa->txq_count,
317 sizeof(sa->txq_info[0]), 0,
319 if (sa->txq_info == NULL)
320 goto fail_txqs_alloc;
322 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
323 rc = sfc_tx_qinit_info(sa, sw_index);
325 goto fail_tx_qinit_info;
331 rte_free(sa->txq_info);
338 fail_tx_dma_desc_boundary:
339 sfc_log_init(sa, "failed (rc = %d)", rc);
344 sfc_tx_fini(struct sfc_adapter *sa)
348 sw_index = sa->txq_count;
349 while (--sw_index >= 0) {
350 if (sa->txq_info[sw_index].txq != NULL)
351 sfc_tx_qfini(sa, sw_index);
354 rte_free(sa->txq_info);
360 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
362 struct rte_eth_dev_data *dev_data;
363 struct sfc_txq_info *txq_info;
367 unsigned int desc_index;
370 sfc_log_init(sa, "TxQ = %u", sw_index);
372 SFC_ASSERT(sw_index < sa->txq_count);
373 txq_info = &sa->txq_info[sw_index];
377 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
381 rc = sfc_ev_qstart(sa, evq->evq_index);
386 * It seems that DPDK has no controls regarding IPv4 offloads,
387 * hence, we always enable it here
389 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
390 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
391 flags = EFX_TXQ_CKSUM_IPV4;
393 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
396 flags |= EFX_TXQ_FATSOV2;
399 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
400 txq_info->entries, 0 /* not used on EF10 */,
402 &txq->common, &desc_index);
404 if (sa->tso && (rc == ENOSPC))
405 sfc_err(sa, "ran out of TSO contexts");
407 goto fail_tx_qcreate;
410 efx_tx_qenable(txq->common);
412 txq->state |= SFC_TXQ_STARTED;
414 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index);
419 * It seems to be used by DPDK for debug purposes only ('rte_ether')
421 dev_data = sa->eth_dev->data;
422 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
427 txq->state = SFC_TXQ_INITIALIZED;
428 efx_tx_qdestroy(txq->common);
431 sfc_ev_qstop(sa, evq->evq_index);
438 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
440 struct rte_eth_dev_data *dev_data;
441 struct sfc_txq_info *txq_info;
443 unsigned int retry_count;
444 unsigned int wait_count;
446 sfc_log_init(sa, "TxQ = %u", sw_index);
448 SFC_ASSERT(sw_index < sa->txq_count);
449 txq_info = &sa->txq_info[sw_index];
453 if (txq->state == SFC_TXQ_INITIALIZED)
456 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
458 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr);
461 * Retry TX queue flushing in case of flush failed or
462 * timeout; in the worst case it can delay for 6 seconds
464 for (retry_count = 0;
465 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
466 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
468 if (efx_tx_qflush(txq->common) != 0) {
469 txq->state |= SFC_TXQ_FLUSHING;
474 * Wait for TX queue flush done or flush failed event at least
475 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
476 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
477 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
481 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
482 sfc_ev_qpoll(txq->evq);
483 } while ((txq->state & SFC_TXQ_FLUSHING) &&
484 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
486 if (txq->state & SFC_TXQ_FLUSHING)
487 sfc_err(sa, "TxQ %u flush timed out", sw_index);
489 if (txq->state & SFC_TXQ_FLUSHED)
490 sfc_info(sa, "TxQ %u flushed", sw_index);
493 sa->dp_tx->qreap(txq->dp);
495 txq->state = SFC_TXQ_INITIALIZED;
497 efx_tx_qdestroy(txq->common);
499 sfc_ev_qstop(sa, txq->evq->evq_index);
502 * It seems to be used by DPDK for debug purposes only ('rte_ether')
504 dev_data = sa->eth_dev->data;
505 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
509 sfc_tx_start(struct sfc_adapter *sa)
511 unsigned int sw_index;
514 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
517 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
518 sfc_warn(sa, "TSO support was unable to be restored");
523 rc = efx_tx_init(sa->nic);
525 goto fail_efx_tx_init;
527 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
528 if (!(sa->txq_info[sw_index].deferred_start) ||
529 sa->txq_info[sw_index].deferred_started) {
530 rc = sfc_tx_qstart(sa, sw_index);
539 while (sw_index-- > 0)
540 sfc_tx_qstop(sa, sw_index);
542 efx_tx_fini(sa->nic);
545 sfc_log_init(sa, "failed (rc = %d)", rc);
550 sfc_tx_stop(struct sfc_adapter *sa)
552 unsigned int sw_index;
554 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
556 sw_index = sa->txq_count;
557 while (sw_index-- > 0) {
558 if (sa->txq_info[sw_index].txq != NULL)
559 sfc_tx_qstop(sa, sw_index);
562 efx_tx_fini(sa->nic);
566 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
568 unsigned int completed;
570 sfc_ev_qpoll(txq->evq);
572 for (completed = txq->completed;
573 completed != txq->pending; completed++) {
574 struct sfc_efx_tx_sw_desc *txd;
576 txd = &txq->sw_ring[completed & txq->ptr_mask];
578 if (txd->mbuf != NULL) {
579 rte_pktmbuf_free(txd->mbuf);
584 txq->completed = completed;
588 * The function is used to insert or update VLAN tag;
589 * the firmware has state of the firmware tag to insert per TxQ
590 * (controlled by option descriptors), hence, if the tag of the
591 * packet to be sent is different from one remembered by the firmware,
592 * the function will update it
595 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
598 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
601 if (this_tag == txq->hw_vlan_tci)
605 * The expression inside SFC_ASSERT() is not desired to be checked in
606 * a non-debug build because it might be too expensive on the data path
608 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
610 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
613 txq->hw_vlan_tci = this_tag;
619 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
621 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
622 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
623 unsigned int added = txq->added;
624 unsigned int pushed = added;
625 unsigned int pkts_sent = 0;
626 efx_desc_t *pend = &txq->pend_desc[0];
627 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
628 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
629 unsigned int fill_level = added - txq->completed;
632 struct rte_mbuf **pktp;
634 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
638 * If insufficient space for a single packet is present,
639 * we should reap; otherwise, we shouldn't do that all the time
640 * to avoid latency increase
642 reap_done = (fill_level > soft_max_fill);
645 sfc_efx_tx_reap(txq);
647 * Recalculate fill level since 'txq->completed'
648 * might have changed on reap
650 fill_level = added - txq->completed;
653 for (pkts_sent = 0, pktp = &tx_pkts[0];
654 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
655 pkts_sent++, pktp++) {
656 struct rte_mbuf *m_seg = *pktp;
657 size_t pkt_len = m_seg->pkt_len;
658 unsigned int pkt_descs = 0;
662 * Here VLAN TCI is expected to be zero in case if no
663 * DEV_TX_VLAN_OFFLOAD capability is advertised;
664 * if the calling app ignores the absence of
665 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
666 * TX_ERROR will occur
668 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
670 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
672 * We expect correct 'pkt->l[2, 3, 4]_len' values
673 * to be set correctly by the caller
675 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
676 &pkt_descs, &pkt_len) != 0) {
677 /* We may have reached this place for
678 * one of the following reasons:
680 * 1) Packet header length is greater
681 * than SFC_TSOH_STD_LEN
682 * 2) TCP header starts at more then
683 * 208 bytes into the frame
685 * We will deceive RTE saying that we have sent
686 * the packet, but we will actually drop it.
687 * Hence, we should revert 'pend' to the
688 * previous state (in case we have added
689 * VLAN descriptor) and start processing
690 * another one packet. But the original
691 * mbuf shouldn't be orphaned
695 rte_pktmbuf_free(*pktp);
701 * We've only added 2 FATSOv2 option descriptors
702 * and 1 descriptor for the linearized packet header.
703 * The outstanding work will be done in the same manner
704 * as for the usual non-TSO path
708 for (; m_seg != NULL; m_seg = m_seg->next) {
709 efsys_dma_addr_t next_frag;
712 seg_len = m_seg->data_len;
713 next_frag = rte_mbuf_data_dma_addr(m_seg);
716 * If we've started TSO transaction few steps earlier,
717 * we'll skip packet header using an offset in the
718 * current segment (which has been set to the
719 * first one containing payload)
726 efsys_dma_addr_t frag_addr = next_frag;
730 * It is assumed here that there is no
731 * limitation on address boundary
732 * crossing by DMA descriptor.
734 frag_len = MIN(seg_len, txq->dma_desc_size_max);
735 next_frag += frag_len;
739 efx_tx_qdesc_dma_create(txq->common,
745 } while (seg_len != 0);
750 fill_level += pkt_descs;
751 if (unlikely(fill_level > hard_max_fill)) {
753 * Our estimation for maximum number of descriptors
754 * required to send a packet seems to be wrong.
755 * Try to reap (if we haven't yet).
758 sfc_efx_tx_reap(txq);
760 fill_level = added - txq->completed;
761 if (fill_level > hard_max_fill) {
771 /* Assign mbuf to the last used desc */
772 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
775 if (likely(pkts_sent > 0)) {
776 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
777 pend - &txq->pend_desc[0],
778 txq->completed, &txq->added);
781 if (likely(pushed != txq->added))
782 efx_tx_qpush(txq->common, txq->added, pushed);
785 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
787 sfc_efx_tx_reap(txq);
795 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
797 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
798 struct rte_eth_dev *eth_dev;
799 struct sfc_adapter *sa;
802 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
803 eth_dev = &rte_eth_devices[dpq->port_id];
805 sa = eth_dev->data->dev_private;
807 SFC_ASSERT(dpq->queue_id < sa->txq_count);
808 txq = sa->txq_info[dpq->queue_id].txq;
810 SFC_ASSERT(txq != NULL);
814 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
816 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
817 const struct rte_pci_addr *pci_addr,
819 const struct sfc_dp_tx_qcreate_info *info,
820 struct sfc_dp_txq **dp_txqp)
822 struct sfc_efx_txq *txq;
823 struct sfc_txq *ctrl_txq;
827 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
828 RTE_CACHE_LINE_SIZE, socket_id);
832 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
835 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
836 EFX_TXQ_LIMIT(info->txq_entries),
837 sizeof(*txq->pend_desc), 0,
839 if (txq->pend_desc == NULL)
840 goto fail_pend_desc_alloc;
843 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
845 sizeof(*txq->sw_ring),
846 RTE_CACHE_LINE_SIZE, socket_id);
847 if (txq->sw_ring == NULL)
848 goto fail_sw_ring_alloc;
850 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
851 if (ctrl_txq->evq->sa->tso) {
852 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
853 info->txq_entries, socket_id);
855 goto fail_alloc_tsoh_objs;
858 txq->evq = ctrl_txq->evq;
859 txq->ptr_mask = info->txq_entries - 1;
860 txq->free_thresh = info->free_thresh;
861 txq->dma_desc_size_max = info->dma_desc_size_max;
866 fail_alloc_tsoh_objs:
867 rte_free(txq->sw_ring);
870 rte_free(txq->pend_desc);
872 fail_pend_desc_alloc:
879 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
881 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
883 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
885 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
886 rte_free(txq->sw_ring);
887 rte_free(txq->pend_desc);
891 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
893 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
894 __rte_unused unsigned int evq_read_ptr,
895 unsigned int txq_desc_index)
897 /* libefx-based datapath is specific to libefx-based PMD */
898 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
899 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
901 txq->common = ctrl_txq->common;
903 txq->pending = txq->completed = txq->added = txq_desc_index;
904 txq->hw_vlan_tci = 0;
906 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
911 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
913 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
914 __rte_unused unsigned int *evq_read_ptr)
916 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
918 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
921 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
923 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
925 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
928 sfc_efx_tx_reap(txq);
930 for (txds = 0; txds <= txq->ptr_mask; txds++) {
931 if (txq->sw_ring[txds].mbuf != NULL) {
932 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
933 txq->sw_ring[txds].mbuf = NULL;
937 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
940 struct sfc_dp_tx sfc_efx_tx = {
942 .name = SFC_KVARG_DATAPATH_EFX,
946 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
948 SFC_DP_TX_FEAT_MULTI_SEG,
949 .qcreate = sfc_efx_tx_qcreate,
950 .qdestroy = sfc_efx_tx_qdestroy,
951 .qstart = sfc_efx_tx_qstart,
952 .qstop = sfc_efx_tx_qstop,
953 .qreap = sfc_efx_tx_qreap,
954 .pkt_burst = sfc_efx_xmit_pkts,