2 * Copyright (c) 2016 Solarflare Communications Inc.
5 * This software was jointly developed between OKTET Labs (under contract
6 * for Solarflare) and Solarflare Communications, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "sfc_debug.h"
35 #include "sfc_tweak.h"
38 * Maximum number of TX queue flush attempts in case of
39 * failure or flush timeout
41 #define SFC_TX_QFLUSH_ATTEMPTS (3)
44 * Time to wait between event queue polling attempts when waiting for TX
45 * queue flush done or flush failed events
47 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
50 * Maximum number of event queue polling attempts when waiting for TX queue
51 * flush done or flush failed events; it defines TX queue flush attempt timeout
52 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
54 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
57 sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc,
58 const struct rte_eth_txconf *tx_conf)
60 unsigned int flags = tx_conf->txq_flags;
61 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
64 if (tx_conf->tx_rs_thresh != 0) {
65 sfc_err(sa, "RS bit in transmit descriptor is not supported");
69 if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) {
71 "TxQ free threshold too large: %u vs maximum %u",
72 tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc));
76 if (tx_conf->tx_thresh.pthresh != 0 ||
77 tx_conf->tx_thresh.hthresh != 0 ||
78 tx_conf->tx_thresh.wthresh != 0) {
80 "prefetch/host/writeback thresholds are not supported");
84 if (!encp->enc_hw_tx_insert_vlan_enabled &&
85 (flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
86 sfc_err(sa, "VLAN offload is not supported");
90 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
91 sfc_err(sa, "SCTP offload is not supported");
95 /* We either perform both TCP and UDP offload, or no offload at all */
96 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
97 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
98 sfc_err(sa, "TCP and UDP offloads can't be set independently");
106 sfc_tx_qflush_done(struct sfc_txq *txq)
108 txq->state |= SFC_TXQ_FLUSHED;
109 txq->state &= ~SFC_TXQ_FLUSHING;
113 sfc_tx_reap(struct sfc_txq *txq)
115 unsigned int completed;
118 sfc_ev_qpoll(txq->evq);
120 for (completed = txq->completed;
121 completed != txq->pending; completed++) {
122 struct sfc_tx_sw_desc *txd;
124 txd = &txq->sw_ring[completed & txq->ptr_mask];
126 if (txd->mbuf != NULL) {
127 rte_pktmbuf_free(txd->mbuf);
132 txq->completed = completed;
136 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
137 uint16_t nb_tx_desc, unsigned int socket_id,
138 const struct rte_eth_txconf *tx_conf)
140 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
141 struct sfc_txq_info *txq_info;
144 unsigned int evq_index = sfc_evq_index_by_txq_sw_index(sa, sw_index);
147 sfc_log_init(sa, "TxQ = %u", sw_index);
149 rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf);
153 SFC_ASSERT(sw_index < sa->txq_count);
154 txq_info = &sa->txq_info[sw_index];
156 SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries);
157 txq_info->entries = nb_tx_desc;
159 rc = sfc_ev_qinit(sa, evq_index, txq_info->entries, socket_id);
163 evq = sa->evq_info[evq_index].evq;
166 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
170 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
171 socket_id, &txq->mem);
176 txq->pend_desc = rte_calloc_socket("sfc-txq-pend-desc",
177 EFX_TXQ_LIMIT(txq_info->entries),
178 sizeof(efx_desc_t), 0, socket_id);
179 if (txq->pend_desc == NULL)
180 goto fail_pend_desc_alloc;
183 txq->sw_ring = rte_calloc_socket("sfc-txq-desc", txq_info->entries,
184 sizeof(*txq->sw_ring), 0, socket_id);
185 if (txq->sw_ring == NULL)
186 goto fail_desc_alloc;
189 rc = sfc_tso_alloc_tsoh_objs(txq->sw_ring, txq_info->entries,
192 goto fail_alloc_tsoh_objs;
195 txq->state = SFC_TXQ_INITIALIZED;
196 txq->ptr_mask = txq_info->entries - 1;
197 txq->free_thresh = (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
198 SFC_TX_DEFAULT_FREE_THRESH;
199 txq->dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
200 txq->hw_index = sw_index;
201 txq->flags = tx_conf->txq_flags;
207 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
211 fail_alloc_tsoh_objs:
212 rte_free(txq->sw_ring);
215 rte_free(txq->pend_desc);
217 fail_pend_desc_alloc:
218 sfc_dma_free(sa, &txq->mem);
224 sfc_ev_qfini(sa, evq_index);
227 txq_info->entries = 0;
230 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
235 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
237 struct sfc_txq_info *txq_info;
240 sfc_log_init(sa, "TxQ = %u", sw_index);
242 SFC_ASSERT(sw_index < sa->txq_count);
243 txq_info = &sa->txq_info[sw_index];
246 SFC_ASSERT(txq != NULL);
247 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
249 sfc_tso_free_tsoh_objs(txq->sw_ring, txq_info->entries);
251 txq_info->txq = NULL;
252 txq_info->entries = 0;
254 rte_free(txq->sw_ring);
255 rte_free(txq->pend_desc);
256 sfc_dma_free(sa, &txq->mem);
261 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
263 sfc_log_init(sa, "TxQ = %u", sw_index);
269 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
273 switch (txmode->mq_mode) {
277 sfc_err(sa, "Tx multi-queue mode %u not supported",
283 * These features are claimed to be i40e-specific,
284 * but it does make sense to double-check their absence
286 if (txmode->hw_vlan_reject_tagged) {
287 sfc_err(sa, "Rejecting tagged packets not supported");
291 if (txmode->hw_vlan_reject_untagged) {
292 sfc_err(sa, "Rejecting untagged packets not supported");
296 if (txmode->hw_vlan_insert_pvid) {
297 sfc_err(sa, "Port-based VLAN insertion not supported");
305 sfc_tx_init(struct sfc_adapter *sa)
307 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
308 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
309 unsigned int sw_index;
313 * The datapath implementation assumes absence of boundary
314 * limits on Tx DMA descriptors. Addition of these checks on
315 * datapath would simply make the datapath slower.
317 if (encp->enc_tx_dma_desc_boundary != 0) {
319 goto fail_tx_dma_desc_boundary;
322 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
324 goto fail_check_mode;
326 sa->txq_count = sa->eth_dev->data->nb_tx_queues;
328 sa->txq_info = rte_calloc_socket("sfc-txqs", sa->txq_count,
329 sizeof(sa->txq_info[0]), 0,
331 if (sa->txq_info == NULL)
332 goto fail_txqs_alloc;
334 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
335 rc = sfc_tx_qinit_info(sa, sw_index);
337 goto fail_tx_qinit_info;
343 rte_free(sa->txq_info);
350 fail_tx_dma_desc_boundary:
351 sfc_log_init(sa, "failed (rc = %d)", rc);
356 sfc_tx_fini(struct sfc_adapter *sa)
360 sw_index = sa->txq_count;
361 while (--sw_index >= 0) {
362 if (sa->txq_info[sw_index].txq != NULL)
363 sfc_tx_qfini(sa, sw_index);
366 rte_free(sa->txq_info);
372 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
374 struct rte_eth_dev_data *dev_data;
375 struct sfc_txq_info *txq_info;
379 unsigned int desc_index;
382 sfc_log_init(sa, "TxQ = %u", sw_index);
384 SFC_ASSERT(sw_index < sa->txq_count);
385 txq_info = &sa->txq_info[sw_index];
389 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
393 rc = sfc_ev_qstart(sa, evq->evq_index);
398 * It seems that DPDK has no controls regarding IPv4 offloads,
399 * hence, we always enable it here
401 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
402 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
403 flags = EFX_TXQ_CKSUM_IPV4;
405 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
408 flags |= EFX_TXQ_FATSOV2;
411 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
412 txq_info->entries, 0 /* not used on EF10 */,
414 &txq->common, &desc_index);
416 if (sa->tso && (rc == ENOSPC))
417 sfc_err(sa, "ran out of TSO contexts");
419 goto fail_tx_qcreate;
422 txq->added = txq->pending = txq->completed = desc_index;
423 txq->hw_vlan_tci = 0;
425 efx_tx_qenable(txq->common);
427 txq->state |= (SFC_TXQ_STARTED | SFC_TXQ_RUNNING);
430 * It seems to be used by DPDK for debug purposes only ('rte_ether')
432 dev_data = sa->eth_dev->data;
433 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
438 sfc_ev_qstop(sa, evq->evq_index);
445 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
447 struct rte_eth_dev_data *dev_data;
448 struct sfc_txq_info *txq_info;
450 unsigned int retry_count;
451 unsigned int wait_count;
454 sfc_log_init(sa, "TxQ = %u", sw_index);
456 SFC_ASSERT(sw_index < sa->txq_count);
457 txq_info = &sa->txq_info[sw_index];
461 if (txq->state == SFC_TXQ_INITIALIZED)
464 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
466 txq->state &= ~SFC_TXQ_RUNNING;
469 * Retry TX queue flushing in case of flush failed or
470 * timeout; in the worst case it can delay for 6 seconds
472 for (retry_count = 0;
473 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
474 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
476 if (efx_tx_qflush(txq->common) != 0) {
477 txq->state |= SFC_TXQ_FLUSHING;
482 * Wait for TX queue flush done or flush failed event at least
483 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
484 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
485 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
489 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
490 sfc_ev_qpoll(txq->evq);
491 } while ((txq->state & SFC_TXQ_FLUSHING) &&
492 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
494 if (txq->state & SFC_TXQ_FLUSHING)
495 sfc_err(sa, "TxQ %u flush timed out", sw_index);
497 if (txq->state & SFC_TXQ_FLUSHED)
498 sfc_info(sa, "TxQ %u flushed", sw_index);
503 for (txds = 0; txds < txq_info->entries; txds++) {
504 if (txq->sw_ring[txds].mbuf != NULL) {
505 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
506 txq->sw_ring[txds].mbuf = NULL;
510 txq->state = SFC_TXQ_INITIALIZED;
512 efx_tx_qdestroy(txq->common);
514 sfc_ev_qstop(sa, txq->evq->evq_index);
517 * It seems to be used by DPDK for debug purposes only ('rte_ether')
519 dev_data = sa->eth_dev->data;
520 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
524 sfc_tx_start(struct sfc_adapter *sa)
526 unsigned int sw_index;
529 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
532 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
533 sfc_warn(sa, "TSO support was unable to be restored");
538 rc = efx_tx_init(sa->nic);
540 goto fail_efx_tx_init;
542 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
543 if (!(sa->txq_info[sw_index].deferred_start) ||
544 sa->txq_info[sw_index].deferred_started) {
545 rc = sfc_tx_qstart(sa, sw_index);
554 while (sw_index-- > 0)
555 sfc_tx_qstop(sa, sw_index);
557 efx_tx_fini(sa->nic);
560 sfc_log_init(sa, "failed (rc = %d)", rc);
565 sfc_tx_stop(struct sfc_adapter *sa)
567 unsigned int sw_index;
569 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
571 sw_index = sa->txq_count;
572 while (sw_index-- > 0) {
573 if (sa->txq_info[sw_index].txq != NULL)
574 sfc_tx_qstop(sa, sw_index);
577 efx_tx_fini(sa->nic);
581 * The function is used to insert or update VLAN tag;
582 * the firmware has state of the firmware tag to insert per TxQ
583 * (controlled by option descriptors), hence, if the tag of the
584 * packet to be sent is different from one remembered by the firmware,
585 * the function will update it
588 sfc_tx_maybe_insert_tag(struct sfc_txq *txq, struct rte_mbuf *m,
591 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
594 if (this_tag == txq->hw_vlan_tci)
598 * The expression inside SFC_ASSERT() is not desired to be checked in
599 * a non-debug build because it might be too expensive on the data path
601 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
603 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
606 txq->hw_vlan_tci = this_tag;
612 sfc_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
614 struct sfc_txq *txq = (struct sfc_txq *)tx_queue;
615 unsigned int added = txq->added;
616 unsigned int pushed = added;
617 unsigned int pkts_sent = 0;
618 efx_desc_t *pend = &txq->pend_desc[0];
619 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
620 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
621 unsigned int fill_level = added - txq->completed;
624 struct rte_mbuf **pktp;
626 if (unlikely((txq->state & SFC_TXQ_RUNNING) == 0))
630 * If insufficient space for a single packet is present,
631 * we should reap; otherwise, we shouldn't do that all the time
632 * to avoid latency increase
634 reap_done = (fill_level > soft_max_fill);
639 * Recalculate fill level since 'txq->completed'
640 * might have changed on reap
642 fill_level = added - txq->completed;
645 for (pkts_sent = 0, pktp = &tx_pkts[0];
646 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
647 pkts_sent++, pktp++) {
648 struct rte_mbuf *m_seg = *pktp;
649 size_t pkt_len = m_seg->pkt_len;
650 unsigned int pkt_descs = 0;
654 * Here VLAN TCI is expected to be zero in case if no
655 * DEV_TX_VLAN_OFFLOAD capability is advertised;
656 * if the calling app ignores the absence of
657 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
658 * TX_ERROR will occur
660 pkt_descs += sfc_tx_maybe_insert_tag(txq, m_seg, &pend);
662 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
664 * We expect correct 'pkt->l[2, 3, 4]_len' values
665 * to be set correctly by the caller
667 if (sfc_tso_do(txq, added, &m_seg, &in_off, &pend,
668 &pkt_descs, &pkt_len) != 0) {
669 /* We may have reached this place for
670 * one of the following reasons:
672 * 1) Packet header length is greater
673 * than SFC_TSOH_STD_LEN
674 * 2) TCP header starts at more then
675 * 208 bytes into the frame
677 * We will deceive RTE saying that we have sent
678 * the packet, but we will actually drop it.
679 * Hence, we should revert 'pend' to the
680 * previous state (in case we have added
681 * VLAN descriptor) and start processing
682 * another one packet. But the original
683 * mbuf shouldn't be orphaned
687 rte_pktmbuf_free(*pktp);
693 * We've only added 2 FATSOv2 option descriptors
694 * and 1 descriptor for the linearized packet header.
695 * The outstanding work will be done in the same manner
696 * as for the usual non-TSO path
700 for (; m_seg != NULL; m_seg = m_seg->next) {
701 efsys_dma_addr_t next_frag;
704 seg_len = m_seg->data_len;
705 next_frag = rte_mbuf_data_dma_addr(m_seg);
708 * If we've started TSO transaction few steps earlier,
709 * we'll skip packet header using an offset in the
710 * current segment (which has been set to the
711 * first one containing payload)
718 efsys_dma_addr_t frag_addr = next_frag;
722 * It is assumed here that there is no
723 * limitation on address boundary
724 * crossing by DMA descriptor.
726 frag_len = MIN(seg_len, txq->dma_desc_size_max);
727 next_frag += frag_len;
731 efx_tx_qdesc_dma_create(txq->common,
737 } while (seg_len != 0);
742 fill_level += pkt_descs;
743 if (unlikely(fill_level > hard_max_fill)) {
745 * Our estimation for maximum number of descriptors
746 * required to send a packet seems to be wrong.
747 * Try to reap (if we haven't yet).
752 fill_level = added - txq->completed;
753 if (fill_level > hard_max_fill) {
763 /* Assign mbuf to the last used desc */
764 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
767 if (likely(pkts_sent > 0)) {
768 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
769 pend - &txq->pend_desc[0],
770 txq->completed, &txq->added);
773 if (likely(pushed != txq->added))
774 efx_tx_qpush(txq->common, txq->added, pushed);
777 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE