4 * Copyright (c) 2016-2017 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "sfc_debug.h"
37 #include "sfc_tweak.h"
38 #include "sfc_kvargs.h"
41 * Maximum number of TX queue flush attempts in case of
42 * failure or flush timeout
44 #define SFC_TX_QFLUSH_ATTEMPTS (3)
47 * Time to wait between event queue polling attempts when waiting for TX
48 * queue flush done or flush failed events
50 #define SFC_TX_QFLUSH_POLL_WAIT_MS (1)
53 * Maximum number of event queue polling attempts when waiting for TX queue
54 * flush done or flush failed events; it defines TX queue flush attempt timeout
55 * together with SFC_TX_QFLUSH_POLL_WAIT_MS
57 #define SFC_TX_QFLUSH_POLL_ATTEMPTS (2000)
60 sfc_tx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_tx_desc,
61 const struct rte_eth_txconf *tx_conf)
63 unsigned int flags = tx_conf->txq_flags;
64 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
67 if (tx_conf->tx_rs_thresh != 0) {
68 sfc_err(sa, "RS bit in transmit descriptor is not supported");
72 if (tx_conf->tx_free_thresh > EFX_TXQ_LIMIT(nb_tx_desc)) {
74 "TxQ free threshold too large: %u vs maximum %u",
75 tx_conf->tx_free_thresh, EFX_TXQ_LIMIT(nb_tx_desc));
79 if (tx_conf->tx_thresh.pthresh != 0 ||
80 tx_conf->tx_thresh.hthresh != 0 ||
81 tx_conf->tx_thresh.wthresh != 0) {
83 "prefetch/host/writeback thresholds are not supported");
87 if (((flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) &&
88 (~sa->dp_tx->features & SFC_DP_TX_FEAT_MULTI_SEG)) {
89 sfc_err(sa, "Multi-segment is not supported by %s datapath",
94 if ((flags & ETH_TXQ_FLAGS_NOVLANOFFL) == 0) {
95 if (!encp->enc_hw_tx_insert_vlan_enabled) {
96 sfc_err(sa, "VLAN offload is not supported");
98 } else if (~sa->dp_tx->features & SFC_DP_TX_FEAT_VLAN_INSERT) {
100 "VLAN offload is not supported by %s datapath",
106 if ((flags & ETH_TXQ_FLAGS_NOXSUMSCTP) == 0) {
107 sfc_err(sa, "SCTP offload is not supported");
111 /* We either perform both TCP and UDP offload, or no offload at all */
112 if (((flags & ETH_TXQ_FLAGS_NOXSUMTCP) == 0) !=
113 ((flags & ETH_TXQ_FLAGS_NOXSUMUDP) == 0)) {
114 sfc_err(sa, "TCP and UDP offloads can't be set independently");
122 sfc_tx_qflush_done(struct sfc_txq *txq)
124 txq->state |= SFC_TXQ_FLUSHED;
125 txq->state &= ~SFC_TXQ_FLUSHING;
129 sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
130 uint16_t nb_tx_desc, unsigned int socket_id,
131 const struct rte_eth_txconf *tx_conf)
133 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
134 struct sfc_txq_info *txq_info;
137 unsigned int evq_index = sfc_evq_index_by_txq_sw_index(sa, sw_index);
139 struct sfc_dp_tx_qcreate_info info;
141 sfc_log_init(sa, "TxQ = %u", sw_index);
143 rc = sfc_tx_qcheck_conf(sa, nb_tx_desc, tx_conf);
147 SFC_ASSERT(sw_index < sa->txq_count);
148 txq_info = &sa->txq_info[sw_index];
150 SFC_ASSERT(nb_tx_desc <= sa->txq_max_entries);
151 txq_info->entries = nb_tx_desc;
153 rc = sfc_ev_qinit(sa, evq_index, txq_info->entries, socket_id);
157 evq = sa->evq_info[evq_index].evq;
160 txq = rte_zmalloc_socket("sfc-txq", sizeof(*txq), 0, socket_id);
166 txq->hw_index = sw_index;
169 (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
170 SFC_TX_DEFAULT_FREE_THRESH;
171 txq->flags = tx_conf->txq_flags;
173 rc = sfc_dma_alloc(sa, "txq", sw_index, EFX_TXQ_SIZE(txq_info->entries),
174 socket_id, &txq->mem);
178 memset(&info, 0, sizeof(info));
179 info.free_thresh = txq->free_thresh;
180 info.flags = tx_conf->txq_flags;
181 info.txq_entries = txq_info->entries;
182 info.dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
183 info.txq_hw_ring = txq->mem.esm_base;
184 info.evq_entries = txq_info->entries;
185 info.evq_hw_ring = evq->mem.esm_base;
186 info.hw_index = txq->hw_index;
187 info.mem_bar = sa->mem_bar.esb_base;
189 rc = sa->dp_tx->qcreate(sa->eth_dev->data->port_id, sw_index,
190 &SFC_DEV_TO_PCI(sa->eth_dev)->addr,
191 socket_id, &info, &txq->dp);
193 goto fail_dp_tx_qinit;
195 evq->dp_txq = txq->dp;
197 txq->state = SFC_TXQ_INITIALIZED;
199 txq_info->deferred_start = (tx_conf->tx_deferred_start != 0);
204 sfc_dma_free(sa, &txq->mem);
207 txq_info->txq = NULL;
211 sfc_ev_qfini(sa, evq_index);
214 txq_info->entries = 0;
217 sfc_log_init(sa, "failed (TxQ = %u, rc = %d)", sw_index, rc);
222 sfc_tx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
224 struct sfc_txq_info *txq_info;
227 sfc_log_init(sa, "TxQ = %u", sw_index);
229 SFC_ASSERT(sw_index < sa->txq_count);
230 txq_info = &sa->txq_info[sw_index];
233 SFC_ASSERT(txq != NULL);
234 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
236 sa->dp_tx->qdestroy(txq->dp);
239 txq_info->txq = NULL;
240 txq_info->entries = 0;
242 sfc_dma_free(sa, &txq->mem);
247 sfc_tx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
249 sfc_log_init(sa, "TxQ = %u", sw_index);
255 sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
259 switch (txmode->mq_mode) {
263 sfc_err(sa, "Tx multi-queue mode %u not supported",
269 * These features are claimed to be i40e-specific,
270 * but it does make sense to double-check their absence
272 if (txmode->hw_vlan_reject_tagged) {
273 sfc_err(sa, "Rejecting tagged packets not supported");
277 if (txmode->hw_vlan_reject_untagged) {
278 sfc_err(sa, "Rejecting untagged packets not supported");
282 if (txmode->hw_vlan_insert_pvid) {
283 sfc_err(sa, "Port-based VLAN insertion not supported");
291 sfc_tx_init(struct sfc_adapter *sa)
293 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
294 const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
295 unsigned int sw_index;
299 * The datapath implementation assumes absence of boundary
300 * limits on Tx DMA descriptors. Addition of these checks on
301 * datapath would simply make the datapath slower.
303 if (encp->enc_tx_dma_desc_boundary != 0) {
305 goto fail_tx_dma_desc_boundary;
308 if (~sa->dp_tx->features & SFC_DP_TX_FEAT_TSO)
311 rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
313 goto fail_check_mode;
315 sa->txq_count = sa->eth_dev->data->nb_tx_queues;
317 sa->txq_info = rte_calloc_socket("sfc-txqs", sa->txq_count,
318 sizeof(sa->txq_info[0]), 0,
320 if (sa->txq_info == NULL)
321 goto fail_txqs_alloc;
323 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
324 rc = sfc_tx_qinit_info(sa, sw_index);
326 goto fail_tx_qinit_info;
332 rte_free(sa->txq_info);
339 fail_tx_dma_desc_boundary:
340 sfc_log_init(sa, "failed (rc = %d)", rc);
345 sfc_tx_fini(struct sfc_adapter *sa)
349 sw_index = sa->txq_count;
350 while (--sw_index >= 0) {
351 if (sa->txq_info[sw_index].txq != NULL)
352 sfc_tx_qfini(sa, sw_index);
355 rte_free(sa->txq_info);
361 sfc_tx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
363 struct rte_eth_dev_data *dev_data;
364 struct sfc_txq_info *txq_info;
368 unsigned int desc_index;
371 sfc_log_init(sa, "TxQ = %u", sw_index);
373 SFC_ASSERT(sw_index < sa->txq_count);
374 txq_info = &sa->txq_info[sw_index];
378 SFC_ASSERT(txq->state == SFC_TXQ_INITIALIZED);
382 rc = sfc_ev_qstart(sa, evq->evq_index);
387 * It seems that DPDK has no controls regarding IPv4 offloads,
388 * hence, we always enable it here
390 if ((txq->flags & ETH_TXQ_FLAGS_NOXSUMTCP) ||
391 (txq->flags & ETH_TXQ_FLAGS_NOXSUMUDP)) {
392 flags = EFX_TXQ_CKSUM_IPV4;
394 flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP;
397 flags |= EFX_TXQ_FATSOV2;
400 rc = efx_tx_qcreate(sa->nic, sw_index, 0, &txq->mem,
401 txq_info->entries, 0 /* not used on EF10 */,
403 &txq->common, &desc_index);
405 if (sa->tso && (rc == ENOSPC))
406 sfc_err(sa, "ran out of TSO contexts");
408 goto fail_tx_qcreate;
411 efx_tx_qenable(txq->common);
413 txq->state |= SFC_TXQ_STARTED;
415 rc = sa->dp_tx->qstart(txq->dp, evq->read_ptr, desc_index);
420 * It seems to be used by DPDK for debug purposes only ('rte_ether')
422 dev_data = sa->eth_dev->data;
423 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STARTED;
428 txq->state = SFC_TXQ_INITIALIZED;
429 efx_tx_qdestroy(txq->common);
432 sfc_ev_qstop(sa, evq->evq_index);
439 sfc_tx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
441 struct rte_eth_dev_data *dev_data;
442 struct sfc_txq_info *txq_info;
444 unsigned int retry_count;
445 unsigned int wait_count;
447 sfc_log_init(sa, "TxQ = %u", sw_index);
449 SFC_ASSERT(sw_index < sa->txq_count);
450 txq_info = &sa->txq_info[sw_index];
454 if (txq->state == SFC_TXQ_INITIALIZED)
457 SFC_ASSERT(txq->state & SFC_TXQ_STARTED);
459 sa->dp_tx->qstop(txq->dp, &txq->evq->read_ptr);
462 * Retry TX queue flushing in case of flush failed or
463 * timeout; in the worst case it can delay for 6 seconds
465 for (retry_count = 0;
466 ((txq->state & SFC_TXQ_FLUSHED) == 0) &&
467 (retry_count < SFC_TX_QFLUSH_ATTEMPTS);
469 if (efx_tx_qflush(txq->common) != 0) {
470 txq->state |= SFC_TXQ_FLUSHING;
475 * Wait for TX queue flush done or flush failed event at least
476 * SFC_TX_QFLUSH_POLL_WAIT_MS milliseconds and not more
477 * than 2 seconds (SFC_TX_QFLUSH_POLL_WAIT_MS multiplied
478 * by SFC_TX_QFLUSH_POLL_ATTEMPTS)
482 rte_delay_ms(SFC_TX_QFLUSH_POLL_WAIT_MS);
483 sfc_ev_qpoll(txq->evq);
484 } while ((txq->state & SFC_TXQ_FLUSHING) &&
485 wait_count++ < SFC_TX_QFLUSH_POLL_ATTEMPTS);
487 if (txq->state & SFC_TXQ_FLUSHING)
488 sfc_err(sa, "TxQ %u flush timed out", sw_index);
490 if (txq->state & SFC_TXQ_FLUSHED)
491 sfc_info(sa, "TxQ %u flushed", sw_index);
494 sa->dp_tx->qreap(txq->dp);
496 txq->state = SFC_TXQ_INITIALIZED;
498 efx_tx_qdestroy(txq->common);
500 sfc_ev_qstop(sa, txq->evq->evq_index);
503 * It seems to be used by DPDK for debug purposes only ('rte_ether')
505 dev_data = sa->eth_dev->data;
506 dev_data->tx_queue_state[sw_index] = RTE_ETH_QUEUE_STATE_STOPPED;
510 sfc_tx_start(struct sfc_adapter *sa)
512 unsigned int sw_index;
515 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
518 if (!efx_nic_cfg_get(sa->nic)->enc_fw_assisted_tso_v2_enabled) {
519 sfc_warn(sa, "TSO support was unable to be restored");
524 rc = efx_tx_init(sa->nic);
526 goto fail_efx_tx_init;
528 for (sw_index = 0; sw_index < sa->txq_count; ++sw_index) {
529 if (!(sa->txq_info[sw_index].deferred_start) ||
530 sa->txq_info[sw_index].deferred_started) {
531 rc = sfc_tx_qstart(sa, sw_index);
540 while (sw_index-- > 0)
541 sfc_tx_qstop(sa, sw_index);
543 efx_tx_fini(sa->nic);
546 sfc_log_init(sa, "failed (rc = %d)", rc);
551 sfc_tx_stop(struct sfc_adapter *sa)
553 unsigned int sw_index;
555 sfc_log_init(sa, "txq_count = %u", sa->txq_count);
557 sw_index = sa->txq_count;
558 while (sw_index-- > 0) {
559 if (sa->txq_info[sw_index].txq != NULL)
560 sfc_tx_qstop(sa, sw_index);
563 efx_tx_fini(sa->nic);
567 sfc_efx_tx_reap(struct sfc_efx_txq *txq)
569 unsigned int completed;
571 sfc_ev_qpoll(txq->evq);
573 for (completed = txq->completed;
574 completed != txq->pending; completed++) {
575 struct sfc_efx_tx_sw_desc *txd;
577 txd = &txq->sw_ring[completed & txq->ptr_mask];
579 if (txd->mbuf != NULL) {
580 rte_pktmbuf_free(txd->mbuf);
585 txq->completed = completed;
589 * The function is used to insert or update VLAN tag;
590 * the firmware has state of the firmware tag to insert per TxQ
591 * (controlled by option descriptors), hence, if the tag of the
592 * packet to be sent is different from one remembered by the firmware,
593 * the function will update it
596 sfc_efx_tx_maybe_insert_tag(struct sfc_efx_txq *txq, struct rte_mbuf *m,
599 uint16_t this_tag = ((m->ol_flags & PKT_TX_VLAN_PKT) ?
602 if (this_tag == txq->hw_vlan_tci)
606 * The expression inside SFC_ASSERT() is not desired to be checked in
607 * a non-debug build because it might be too expensive on the data path
609 SFC_ASSERT(efx_nic_cfg_get(txq->evq->sa->nic)->enc_hw_tx_insert_vlan_enabled);
611 efx_tx_qdesc_vlantci_create(txq->common, rte_cpu_to_be_16(this_tag),
614 txq->hw_vlan_tci = this_tag;
620 sfc_efx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
622 struct sfc_dp_txq *dp_txq = (struct sfc_dp_txq *)tx_queue;
623 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
624 unsigned int added = txq->added;
625 unsigned int pushed = added;
626 unsigned int pkts_sent = 0;
627 efx_desc_t *pend = &txq->pend_desc[0];
628 const unsigned int hard_max_fill = EFX_TXQ_LIMIT(txq->ptr_mask + 1);
629 const unsigned int soft_max_fill = hard_max_fill - txq->free_thresh;
630 unsigned int fill_level = added - txq->completed;
633 struct rte_mbuf **pktp;
635 if (unlikely((txq->flags & SFC_EFX_TXQ_FLAG_RUNNING) == 0))
639 * If insufficient space for a single packet is present,
640 * we should reap; otherwise, we shouldn't do that all the time
641 * to avoid latency increase
643 reap_done = (fill_level > soft_max_fill);
646 sfc_efx_tx_reap(txq);
648 * Recalculate fill level since 'txq->completed'
649 * might have changed on reap
651 fill_level = added - txq->completed;
654 for (pkts_sent = 0, pktp = &tx_pkts[0];
655 (pkts_sent < nb_pkts) && (fill_level <= soft_max_fill);
656 pkts_sent++, pktp++) {
657 struct rte_mbuf *m_seg = *pktp;
658 size_t pkt_len = m_seg->pkt_len;
659 unsigned int pkt_descs = 0;
663 * Here VLAN TCI is expected to be zero in case if no
664 * DEV_TX_VLAN_OFFLOAD capability is advertised;
665 * if the calling app ignores the absence of
666 * DEV_TX_VLAN_OFFLOAD and pushes VLAN TCI, then
667 * TX_ERROR will occur
669 pkt_descs += sfc_efx_tx_maybe_insert_tag(txq, m_seg, &pend);
671 if (m_seg->ol_flags & PKT_TX_TCP_SEG) {
673 * We expect correct 'pkt->l[2, 3, 4]_len' values
674 * to be set correctly by the caller
676 if (sfc_efx_tso_do(txq, added, &m_seg, &in_off, &pend,
677 &pkt_descs, &pkt_len) != 0) {
678 /* We may have reached this place for
679 * one of the following reasons:
681 * 1) Packet header length is greater
682 * than SFC_TSOH_STD_LEN
683 * 2) TCP header starts at more then
684 * 208 bytes into the frame
686 * We will deceive RTE saying that we have sent
687 * the packet, but we will actually drop it.
688 * Hence, we should revert 'pend' to the
689 * previous state (in case we have added
690 * VLAN descriptor) and start processing
691 * another one packet. But the original
692 * mbuf shouldn't be orphaned
696 rte_pktmbuf_free(*pktp);
702 * We've only added 2 FATSOv2 option descriptors
703 * and 1 descriptor for the linearized packet header.
704 * The outstanding work will be done in the same manner
705 * as for the usual non-TSO path
709 for (; m_seg != NULL; m_seg = m_seg->next) {
710 efsys_dma_addr_t next_frag;
713 seg_len = m_seg->data_len;
714 next_frag = rte_mbuf_data_dma_addr(m_seg);
717 * If we've started TSO transaction few steps earlier,
718 * we'll skip packet header using an offset in the
719 * current segment (which has been set to the
720 * first one containing payload)
727 efsys_dma_addr_t frag_addr = next_frag;
731 * It is assumed here that there is no
732 * limitation on address boundary
733 * crossing by DMA descriptor.
735 frag_len = MIN(seg_len, txq->dma_desc_size_max);
736 next_frag += frag_len;
740 efx_tx_qdesc_dma_create(txq->common,
746 } while (seg_len != 0);
751 fill_level += pkt_descs;
752 if (unlikely(fill_level > hard_max_fill)) {
754 * Our estimation for maximum number of descriptors
755 * required to send a packet seems to be wrong.
756 * Try to reap (if we haven't yet).
759 sfc_efx_tx_reap(txq);
761 fill_level = added - txq->completed;
762 if (fill_level > hard_max_fill) {
772 /* Assign mbuf to the last used desc */
773 txq->sw_ring[(added - 1) & txq->ptr_mask].mbuf = *pktp;
776 if (likely(pkts_sent > 0)) {
777 rc = efx_tx_qdesc_post(txq->common, txq->pend_desc,
778 pend - &txq->pend_desc[0],
779 txq->completed, &txq->added);
782 if (likely(pushed != txq->added))
783 efx_tx_qpush(txq->common, txq->added, pushed);
786 #if SFC_TX_XMIT_PKTS_REAP_AT_LEAST_ONCE
788 sfc_efx_tx_reap(txq);
796 sfc_txq_by_dp_txq(const struct sfc_dp_txq *dp_txq)
798 const struct sfc_dp_queue *dpq = &dp_txq->dpq;
799 struct rte_eth_dev *eth_dev;
800 struct sfc_adapter *sa;
803 SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
804 eth_dev = &rte_eth_devices[dpq->port_id];
806 sa = eth_dev->data->dev_private;
808 SFC_ASSERT(dpq->queue_id < sa->txq_count);
809 txq = sa->txq_info[dpq->queue_id].txq;
811 SFC_ASSERT(txq != NULL);
815 static sfc_dp_tx_qcreate_t sfc_efx_tx_qcreate;
817 sfc_efx_tx_qcreate(uint16_t port_id, uint16_t queue_id,
818 const struct rte_pci_addr *pci_addr,
820 const struct sfc_dp_tx_qcreate_info *info,
821 struct sfc_dp_txq **dp_txqp)
823 struct sfc_efx_txq *txq;
824 struct sfc_txq *ctrl_txq;
828 txq = rte_zmalloc_socket("sfc-efx-txq", sizeof(*txq),
829 RTE_CACHE_LINE_SIZE, socket_id);
833 sfc_dp_queue_init(&txq->dp.dpq, port_id, queue_id, pci_addr);
836 txq->pend_desc = rte_calloc_socket("sfc-efx-txq-pend-desc",
837 EFX_TXQ_LIMIT(info->txq_entries),
838 sizeof(*txq->pend_desc), 0,
840 if (txq->pend_desc == NULL)
841 goto fail_pend_desc_alloc;
844 txq->sw_ring = rte_calloc_socket("sfc-efx-txq-sw_ring",
846 sizeof(*txq->sw_ring),
847 RTE_CACHE_LINE_SIZE, socket_id);
848 if (txq->sw_ring == NULL)
849 goto fail_sw_ring_alloc;
851 ctrl_txq = sfc_txq_by_dp_txq(&txq->dp);
852 if (ctrl_txq->evq->sa->tso) {
853 rc = sfc_efx_tso_alloc_tsoh_objs(txq->sw_ring,
854 info->txq_entries, socket_id);
856 goto fail_alloc_tsoh_objs;
859 txq->evq = ctrl_txq->evq;
860 txq->ptr_mask = info->txq_entries - 1;
861 txq->free_thresh = info->free_thresh;
862 txq->dma_desc_size_max = info->dma_desc_size_max;
867 fail_alloc_tsoh_objs:
868 rte_free(txq->sw_ring);
871 rte_free(txq->pend_desc);
873 fail_pend_desc_alloc:
880 static sfc_dp_tx_qdestroy_t sfc_efx_tx_qdestroy;
882 sfc_efx_tx_qdestroy(struct sfc_dp_txq *dp_txq)
884 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
886 sfc_efx_tso_free_tsoh_objs(txq->sw_ring, txq->ptr_mask + 1);
887 rte_free(txq->sw_ring);
888 rte_free(txq->pend_desc);
892 static sfc_dp_tx_qstart_t sfc_efx_tx_qstart;
894 sfc_efx_tx_qstart(struct sfc_dp_txq *dp_txq,
895 __rte_unused unsigned int evq_read_ptr,
896 unsigned int txq_desc_index)
898 /* libefx-based datapath is specific to libefx-based PMD */
899 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
900 struct sfc_txq *ctrl_txq = sfc_txq_by_dp_txq(dp_txq);
902 txq->common = ctrl_txq->common;
904 txq->pending = txq->completed = txq->added = txq_desc_index;
905 txq->hw_vlan_tci = 0;
907 txq->flags |= (SFC_EFX_TXQ_FLAG_STARTED | SFC_EFX_TXQ_FLAG_RUNNING);
912 static sfc_dp_tx_qstop_t sfc_efx_tx_qstop;
914 sfc_efx_tx_qstop(struct sfc_dp_txq *dp_txq,
915 __rte_unused unsigned int *evq_read_ptr)
917 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
919 txq->flags &= ~SFC_EFX_TXQ_FLAG_RUNNING;
922 static sfc_dp_tx_qreap_t sfc_efx_tx_qreap;
924 sfc_efx_tx_qreap(struct sfc_dp_txq *dp_txq)
926 struct sfc_efx_txq *txq = sfc_efx_txq_by_dp_txq(dp_txq);
929 sfc_efx_tx_reap(txq);
931 for (txds = 0; txds <= txq->ptr_mask; txds++) {
932 if (txq->sw_ring[txds].mbuf != NULL) {
933 rte_pktmbuf_free(txq->sw_ring[txds].mbuf);
934 txq->sw_ring[txds].mbuf = NULL;
938 txq->flags &= ~SFC_EFX_TXQ_FLAG_STARTED;
941 struct sfc_dp_tx sfc_efx_tx = {
943 .name = SFC_KVARG_DATAPATH_EFX,
947 .features = SFC_DP_TX_FEAT_VLAN_INSERT |
949 SFC_DP_TX_FEAT_MULTI_SEG,
950 .qcreate = sfc_efx_tx_qcreate,
951 .qdestroy = sfc_efx_tx_qdestroy,
952 .qstart = sfc_efx_tx_qstart,
953 .qstop = sfc_efx_tx_qstop,
954 .qreap = sfc_efx_tx_qreap,
955 .pkt_burst = sfc_efx_xmit_pkts,