1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
5 #ifndef _OPAE_INTEL_MAX10_H_
6 #define _OPAE_INTEL_MAX10_H_
8 #include "opae_osdep.h"
11 struct max10_compatible_id {
15 #define MAX10_PAC "intel,max10"
16 #define MAX10_PAC_N3000 "intel,max10-pac-n3000"
17 #define MAX10_PAC_END "intel,end"
19 /* max10 capability flags */
20 #define MAX10_FLAGS_NO_I2C2 BIT(0)
21 #define MAX10_FLAGS_NO_BMCIMG_FLASH BIT(1)
22 #define MAX10_FLAGS_DEVICE_TABLE BIT(2)
23 #define MAX10_FLAGS_SPI BIT(3)
24 #define MAX10_FLGAS_NIOS_SPI BIT(4)
25 #define MAX10_FLAGS_PKVL BIT(5)
27 struct intel_max10_device {
28 unsigned int flags; /*max10 hardware capability*/
29 struct altera_spi_device *spi_master;
30 struct spi_transaction_dev *spi_tran_dev;
31 struct max10_compatible_id *id; /*max10 compatible*/
48 struct opae_retimer_info {
49 unsigned int nums_retimer;
50 unsigned int ports_per_retimer;
51 unsigned int nums_fvl;
52 unsigned int ports_per_fvl;
53 enum retimer_speed support_speed;
57 struct opae_retimer_status {
58 enum retimer_speed speed;
60 * retimer line link status bitmap:
61 * bit 0: Retimer0 Port0 link status
62 * bit 1: Retimer0 Port1 link status
63 * bit 2: Retimer0 Port2 link status
64 * bit 3: Retimer0 Port3 link status
66 * bit 4: Retimer1 Port0 link status
67 * bit 5: Retimer1 Port1 link status
68 * bit 6: Retimer1 Port2 link status
69 * bit 7: Retimer1 Port3 link status
71 unsigned int line_link_bitmap;
74 #define FLASH_BASE 0x10000000
75 #define FLASH_OPTION_BITS 0x10000
77 #define NIOS2_FW_VERSION_OFF 0x300400
78 #define RSU_REG_OFF 0x30042c
79 #define FPGA_RP_LOAD BIT(3)
80 #define NIOS2_PRERESET BIT(4)
81 #define NIOS2_HANG BIT(5)
82 #define RSU_ENABLE BIT(6)
83 #define NIOS2_RESET BIT(7)
84 #define NIOS2_I2C2_POLL_STOP BIT(13)
85 #define FPGA_RECONF_REG_OFF 0x300430
86 #define COUNTDOWN_START BIT(18)
87 #define MAX10_BUILD_VER_OFF 0x300468
88 #define PCB_INFO GENMASK(31, 24)
89 #define MAX10_BUILD_VERION GENMASK(23, 0)
90 #define FPGA_PAGE_INFO_OFF 0x30046c
91 #define DT_AVAIL_REG_OFF 0x300490
92 #define DT_AVAIL BIT(0)
93 #define DT_BASE_ADDR_REG_OFF 0x300494
94 #define PKVL_POLLING_CTRL 0x300480
95 #define PKVL_LINK_STATUS 0x300564
97 #define DFT_MAX_SIZE 0x7e0000
99 int max10_reg_read(unsigned int reg, unsigned int *val);
100 int max10_reg_write(unsigned int reg, unsigned int val);
101 struct intel_max10_device *
102 intel_max10_device_probe(struct altera_spi_device *spi,
104 int intel_max10_device_remove(struct intel_max10_device *dev);
106 /** List of opae sensors */
107 TAILQ_HEAD(opae_sensor_list, opae_sensor_info);
109 #define SENSOR_REG_VALUE 0x0
110 #define SENSOR_REG_HIGH_WARN 0x1
111 #define SENSOR_REG_HIGH_FATAL 0x2
112 #define SENSOR_REG_LOW_WARN 0x3
113 #define SENSOR_REG_LOW_FATAL 0x4
114 #define SENSOR_REG_HYSTERESIS 0x5
115 #define SENSOR_REG_MAX 0x6
117 static const char * const sensor_reg_name[] = {
131 struct raw_sensor_info {
135 unsigned int multiplier;
136 struct sensor_reg regs[SENSOR_REG_MAX];
139 #define OPAE_SENSOR_VALID 0x1
140 #define OPAE_SENSOR_HIGH_WARN_VALID 0x2
141 #define OPAE_SENSOR_HIGH_FATAL_VALID 0x4
142 #define OPAE_SENSOR_LOW_WARN_VALID 0x8
143 #define OPAE_SENSOR_LOW_FATAL_VALID 0x10
144 #define OPAE_SENSOR_HYSTERESIS_VALID 0x20
146 struct opae_sensor_info {
147 TAILQ_ENTRY(opae_sensor_info) node;
151 unsigned int high_fatal;
152 unsigned int high_warn;
153 unsigned int low_fatal;
154 unsigned int low_warn;
155 unsigned int hysteresis;
156 unsigned int multiplier;
159 unsigned int value_reg;