1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
8 #include <rte_regexdev.h>
10 #include <infiniband/verbs.h>
11 #include <infiniband/mlx5dv.h>
13 #include <mlx5_common.h>
17 struct mlx5_regex_sq {
18 uint16_t log_nb_desc; /* Log 2 number of desc for this object. */
19 struct mlx5_devx_obj *obj; /* The SQ DevX object. */
20 int64_t dbr_offset; /* Door bell record offset. */
21 uint32_t dbr_umem; /* Door bell record umem id. */
22 uint8_t *wqe; /* The SQ ring buffer. */
23 struct mlx5dv_devx_umem *wqe_umem; /* SQ buffer umem. */
30 struct mlx5_regex_cq {
31 uint32_t log_nb_desc; /* Log 2 number of desc for this object. */
32 struct mlx5_devx_obj *obj; /* The CQ DevX object. */
33 int64_t dbr_offset; /* Door bell record offset. */
34 uint32_t dbr_umem; /* Door bell record umem id. */
35 volatile struct mlx5_cqe *cqe; /* The CQ ring buffer. */
36 struct mlx5dv_devx_umem *cqe_umem; /* CQ buffer umem. */
41 struct mlx5_regex_qp {
42 uint32_t flags; /* QP user flags. */
43 uint32_t nb_desc; /* Total number of desc for this qp. */
44 struct mlx5_regex_sq *sqs; /* Pointer to sq array. */
45 uint16_t nb_obj; /* Number of sq objects. */
46 struct mlx5_regex_cq cq; /* CQ struct. */
48 struct mlx5_regex_job *jobs;
49 struct ibv_mr *metadata;
50 struct ibv_mr *inputs;
51 struct ibv_mr *outputs;
55 struct mlx5_regex_db {
56 void *ptr; /* Pointer to the db memory. */
57 uint32_t len; /* The memory len. */
58 bool active; /* Active flag. */
59 uint8_t db_assigned_to_eng_num;
60 /**< To which engine the db is connected. */
61 struct mlx5_regex_umem umem;
62 /**< The umem struct. */
65 struct mlx5_regex_priv {
66 TAILQ_ENTRY(mlx5_regex_priv) next;
67 struct ibv_context *ctx; /* Device context. */
68 struct rte_pci_device *pci_dev;
69 struct rte_regexdev *regexdev; /* Pointer to the RegEx dev. */
70 uint16_t nb_queues; /* Number of queues. */
71 struct mlx5_regex_qp *qps; /* Pointer to the qp array. */
72 uint16_t nb_max_matches; /* Max number of matches. */
73 enum mlx5_rxp_program_mode prog_mode;
74 struct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES +
76 uint32_t nb_engines; /* Number of RegEx engines. */
77 uint32_t eqn; /* EQ number. */
78 struct mlx5dv_devx_uar *uar; /* UAR object. */
80 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
84 int mlx5_regex_start(struct rte_regexdev *dev);
85 int mlx5_regex_stop(struct rte_regexdev *dev);
86 int mlx5_regex_close(struct rte_regexdev *dev);
89 int mlx5_regex_info_get(struct rte_regexdev *dev,
90 struct rte_regexdev_info *info);
91 int mlx5_regex_configure(struct rte_regexdev *dev,
92 const struct rte_regexdev_config *cfg);
93 int mlx5_regex_rules_db_import(struct rte_regexdev *dev,
94 const char *rule_db, uint32_t rule_db_len);
96 /* mlx5_regex_devx.c */
97 int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
98 uint32_t addr, uint32_t data);
99 int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
100 uint32_t addr, uint32_t *data);
101 int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine);
102 int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine);
103 int mlx5_devx_regex_database_program(void *ctx, uint8_t engine,
104 uint32_t umem_id, uint64_t umem_offset);
106 /* mlx5_regex_control.c */
107 int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
108 const struct rte_regexdev_qp_conf *cfg);
110 /* mlx5_regex_fastpath.c */
111 int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id);
112 uint16_t mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,
113 struct rte_regex_ops **ops, uint16_t nb_ops);
114 uint16_t mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id,
115 struct rte_regex_ops **ops, uint16_t nb_ops);
117 #endif /* MLX5_REGEX_H */