1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #ifndef _MLX5_RXP_CSRS_H_
6 #define _MLX5_RXP_CSRS_H_
9 * Common to all RXP implementations
11 #define MLX5_RXP_CSR_BASE_ADDRESS 0x0000ul
12 #define MLX5_RXP_RTRU_CSR_BASE_ADDRESS 0x0100ul
13 #define MLX5_RXP_STATS_CSR_BASE_ADDRESS 0x0200ul
14 #define MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS 0x0600ul
16 #define MLX5_RXP_CSR_WIDTH 4
18 /* This is the identifier we expect to see in the first RXP CSR */
19 #define MLX5_RXP_IDENTIFIER 0x5254
21 /* Hyperion specific BAR0 offsets */
22 #define MLX5_RXP_FPGA_BASE_ADDRESS 0x0000ul
23 #define MLX5_RXP_PCIE_BASE_ADDRESS 0x1000ul
24 #define MLX5_RXP_IDMA_BASE_ADDRESS 0x2000ul
25 #define MLX5_RXP_EDMA_BASE_ADDRESS 0x3000ul
26 #define MLX5_RXP_SYSMON_BASE_ADDRESS 0xf300ul
27 #define MLX5_RXP_ISP_CSR_BASE_ADDRESS 0xf400ul
29 /* Offset to the RXP common 4K CSR space */
30 #define MLX5_RXP_PCIE_CSR_BASE_ADDRESS 0xf000ul
34 #define MLX5_RXP_FPGA_VERSION (MLX5_RXP_FPGA_BASE_ADDRESS + \
35 MLX5_RXP_CSR_WIDTH * 0)
38 #define MLX5_RXP_PCIE_INIT_ISR (MLX5_RXP_PCIE_BASE_ADDRESS + \
39 MLX5_RXP_CSR_WIDTH * 0)
40 #define MLX5_RXP_PCIE_INIT_IMR (MLX5_RXP_PCIE_BASE_ADDRESS + \
41 MLX5_RXP_CSR_WIDTH * 1)
42 #define MLX5_RXP_PCIE_INIT_CFG_STAT (MLX5_RXP_PCIE_BASE_ADDRESS + \
43 MLX5_RXP_CSR_WIDTH * 2)
44 #define MLX5_RXP_PCIE_INIT_FLR (MLX5_RXP_PCIE_BASE_ADDRESS + \
45 MLX5_RXP_CSR_WIDTH * 3)
46 #define MLX5_RXP_PCIE_INIT_CTRL (MLX5_RXP_PCIE_BASE_ADDRESS + \
47 MLX5_RXP_CSR_WIDTH * 4)
50 #define MLX5_RXP_IDMA_ISR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
51 #define MLX5_RXP_IDMA_IMR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
52 #define MLX5_RXP_IDMA_CSR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
53 #define MLX5_RXP_IDMA_CSR_RST_MSK 0x0001
54 #define MLX5_RXP_IDMA_CSR_PDONE_MSK 0x0002
55 #define MLX5_RXP_IDMA_CSR_INIT_MSK 0x0004
56 #define MLX5_RXP_IDMA_CSR_EN_MSK 0x0008
57 #define MLX5_RXP_IDMA_QCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
58 #define MLX5_RXP_IDMA_QCR_QAVAIL_MSK 0x00FF
59 #define MLX5_RXP_IDMA_QCR_QEN_MSK 0xFF00
60 #define MLX5_RXP_IDMA_DCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
61 #define MLX5_RXP_IDMA_DWCTR (MLX5_RXP_IDMA_BASE_ADDRESS + \
62 MLX5_RXP_CSR_WIDTH * 7)
63 #define MLX5_RXP_IDMA_DWTOR (MLX5_RXP_IDMA_BASE_ADDRESS + \
64 MLX5_RXP_CSR_WIDTH * 8)
65 #define MLX5_RXP_IDMA_PADCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
66 MLX5_RXP_CSR_WIDTH * 9)
67 #define MLX5_RXP_IDMA_DFCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
68 MLX5_RXP_CSR_WIDTH * 10)
69 #define MLX5_RXP_IDMA_FOFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
70 MLX5_RXP_CSR_WIDTH * 16)
71 #define MLX5_RXP_IDMA_FOFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
72 MLX5_RXP_CSR_WIDTH * 17)
73 #define MLX5_RXP_IDMA_FOFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
74 MLX5_RXP_CSR_WIDTH * 18)
75 #define MLX5_RXP_IDMA_FUFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
76 MLX5_RXP_CSR_WIDTH * 24)
77 #define MLX5_RXP_IDMA_FUFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
78 MLX5_RXP_CSR_WIDTH * 25)
79 #define MLX5_RXP_IDMA_FUFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
80 MLX5_RXP_CSR_WIDTH * 26)
82 #define MLX5_RXP_IDMA_QCSR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
83 MLX5_RXP_CSR_WIDTH * 128)
84 #define MLX5_RXP_IDMA_QCSR_RST_MSK 0x0001
85 #define MLX5_RXP_IDMA_QCSR_PDONE_MSK 0x0002
86 #define MLX5_RXP_IDMA_QCSR_INIT_MSK 0x0004
87 #define MLX5_RXP_IDMA_QCSR_EN_MSK 0x0008
88 #define MLX5_RXP_IDMA_QDPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
89 MLX5_RXP_CSR_WIDTH * 192)
90 #define MLX5_RXP_IDMA_QTPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
91 MLX5_RXP_CSR_WIDTH * 256)
92 #define MLX5_RXP_IDMA_QDRPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
93 MLX5_RXP_CSR_WIDTH * 320)
94 #define MLX5_RXP_IDMA_QDRALR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
95 MLX5_RXP_CSR_WIDTH * 384)
96 #define MLX5_RXP_IDMA_QDRAHR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
97 MLX5_RXP_CSR_WIDTH * 385)
100 #define MLX5_RXP_EDMA_ISR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
101 #define MLX5_RXP_EDMA_IMR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
102 #define MLX5_RXP_EDMA_CSR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
103 #define MLX5_RXP_EDMA_CSR_RST_MSK 0x0001
104 #define MLX5_RXP_EDMA_CSR_PDONE_MSK 0x0002
105 #define MLX5_RXP_EDMA_CSR_INIT_MSK 0x0004
106 #define MLX5_RXP_EDMA_CSR_EN_MSK 0x0008
107 #define MLX5_RXP_EDMA_QCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
108 #define MLX5_RXP_EDMA_QCR_QAVAIL_MSK 0x00FF
109 #define MLX5_RXP_EDMA_QCR_QEN_MSK 0xFF00
110 #define MLX5_RXP_EDMA_DCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
111 #define MLX5_RXP_EDMA_DWCTR (MLX5_RXP_EDMA_BASE_ADDRESS + \
112 MLX5_RXP_CSR_WIDTH * 7)
113 #define MLX5_RXP_EDMA_DWTOR (MLX5_RXP_EDMA_BASE_ADDRESS + \
114 MLX5_RXP_CSR_WIDTH * 8)
115 #define MLX5_RXP_EDMA_DFCR (MLX5_RXP_EDMA_BASE_ADDRESS + \
116 MLX5_RXP_CSR_WIDTH * 10)
117 #define MLX5_RXP_EDMA_FOFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
118 MLX5_RXP_CSR_WIDTH * 16)
119 #define MLX5_RXP_EDMA_FOFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS + \
120 MLX5_RXP_CSR_WIDTH * 17)
121 #define MLX5_RXP_EDMA_FOFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
122 MLX5_RXP_CSR_WIDTH * 18)
123 #define MLX5_RXP_EDMA_FUFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
124 MLX5_RXP_CSR_WIDTH * 24)
125 #define MLX5_RXP_EDMA_FUFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS +\
126 MLX5_RXP_CSR_WIDTH * 25)
127 #define MLX5_RXP_EDMA_FUFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
128 MLX5_RXP_CSR_WIDTH * 26)
130 #define MLX5_RXP_EDMA_QCSR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
131 MLX5_RXP_CSR_WIDTH * 128)
132 #define MLX5_RXP_EDMA_QCSR_RST_MSK 0x0001
133 #define MLX5_RXP_EDMA_QCSR_PDONE_MSK 0x0002
134 #define MLX5_RXP_EDMA_QCSR_INIT_MSK 0x0004
135 #define MLX5_RXP_EDMA_QCSR_EN_MSK 0x0008
136 #define MLX5_RXP_EDMA_QTPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
137 MLX5_RXP_CSR_WIDTH * 256)
138 #define MLX5_RXP_EDMA_QDRPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
139 MLX5_RXP_CSR_WIDTH * 320)
140 #define MLX5_RXP_EDMA_QDRALR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
141 MLX5_RXP_CSR_WIDTH * 384)
142 #define MLX5_RXP_EDMA_QDRAHR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
143 MLX5_RXP_CSR_WIDTH * 385)
146 #define MLX5_RXP_CSR_IDENTIFIER (MLX5_RXP_CSR_BASE_ADDRESS + \
147 MLX5_RXP_CSR_WIDTH * 0)
148 #define MLX5_RXP_CSR_REVISION (MLX5_RXP_CSR_BASE_ADDRESS + \
149 MLX5_RXP_CSR_WIDTH * 1)
150 #define MLX5_RXP_CSR_CAPABILITY_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
151 MLX5_RXP_CSR_WIDTH * 2)
152 #define MLX5_RXP_CSR_CAPABILITY_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
153 MLX5_RXP_CSR_WIDTH * 3)
154 #define MLX5_RXP_CSR_CAPABILITY_2 (MLX5_RXP_CSR_BASE_ADDRESS + \
155 MLX5_RXP_CSR_WIDTH * 4)
156 #define MLX5_RXP_CSR_CAPABILITY_3 (MLX5_RXP_CSR_BASE_ADDRESS + \
157 MLX5_RXP_CSR_WIDTH * 5)
158 #define MLX5_RXP_CSR_CAPABILITY_4 (MLX5_RXP_CSR_BASE_ADDRESS + \
159 MLX5_RXP_CSR_WIDTH * 6)
160 #define MLX5_RXP_CSR_CAPABILITY_5 (MLX5_RXP_CSR_BASE_ADDRESS + \
161 MLX5_RXP_CSR_WIDTH * 7)
162 #define MLX5_RXP_CSR_CAPABILITY_6 (MLX5_RXP_CSR_BASE_ADDRESS + \
163 MLX5_RXP_CSR_WIDTH * 8)
164 #define MLX5_RXP_CSR_CAPABILITY_7 (MLX5_RXP_CSR_BASE_ADDRESS + \
165 MLX5_RXP_CSR_WIDTH * 9)
166 #define MLX5_RXP_CSR_STATUS (MLX5_RXP_CSR_BASE_ADDRESS + \
167 MLX5_RXP_CSR_WIDTH * 10)
168 #define MLX5_RXP_CSR_STATUS_INIT_DONE 0x0001
169 #define MLX5_RXP_CSR_STATUS_GOING 0x0008
170 #define MLX5_RXP_CSR_STATUS_IDLE 0x0040
171 #define MLX5_RXP_CSR_STATUS_TRACKER_OK 0x0080
172 #define MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT 0x0100
173 #define MLX5_RXP_CSR_FIFO_STATUS_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
174 MLX5_RXP_CSR_WIDTH * 11)
175 #define MLX5_RXP_CSR_FIFO_STATUS_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
176 MLX5_RXP_CSR_WIDTH * 12)
177 #define MLX5_RXP_CSR_JOB_DDOS_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
178 MLX5_RXP_CSR_WIDTH * 13)
179 /* 14 + 15 reserved */
180 #define MLX5_RXP_CSR_CORE_CLK_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
181 MLX5_RXP_CSR_WIDTH * 16)
182 #define MLX5_RXP_CSR_WRITE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
183 MLX5_RXP_CSR_WIDTH * 17)
184 #define MLX5_RXP_CSR_JOB_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
185 MLX5_RXP_CSR_WIDTH * 18)
186 #define MLX5_RXP_CSR_JOB_ERROR_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
187 MLX5_RXP_CSR_WIDTH * 19)
188 #define MLX5_RXP_CSR_JOB_BYTE_COUNT0 (MLX5_RXP_CSR_BASE_ADDRESS + \
189 MLX5_RXP_CSR_WIDTH * 20)
190 #define MLX5_RXP_CSR_JOB_BYTE_COUNT1 (MLX5_RXP_CSR_BASE_ADDRESS + \
191 MLX5_RXP_CSR_WIDTH * 21)
192 #define MLX5_RXP_CSR_RESPONSE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
193 MLX5_RXP_CSR_WIDTH * 22)
194 #define MLX5_RXP_CSR_MATCH_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
195 MLX5_RXP_CSR_WIDTH * 23)
196 #define MLX5_RXP_CSR_CTRL (MLX5_RXP_CSR_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 24)
197 #define MLX5_RXP_CSR_CTRL_INIT 0x0001
198 #define MLX5_RXP_CSR_CTRL_GO 0x0008
199 #define MLX5_RXP_CSR_MAX_MATCH (MLX5_RXP_CSR_BASE_ADDRESS + \
200 MLX5_RXP_CSR_WIDTH * 25)
201 #define MLX5_RXP_CSR_MAX_PREFIX (MLX5_RXP_CSR_BASE_ADDRESS + \
202 MLX5_RXP_CSR_WIDTH * 26)
203 #define MLX5_RXP_CSR_MAX_PRI_THREAD (MLX5_RXP_CSR_BASE_ADDRESS + \
204 MLX5_RXP_CSR_WIDTH * 27)
205 #define MLX5_RXP_CSR_MAX_LATENCY (MLX5_RXP_CSR_BASE_ADDRESS + \
206 MLX5_RXP_CSR_WIDTH * 28)
207 #define MLX5_RXP_CSR_SCRATCH_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
208 MLX5_RXP_CSR_WIDTH * 29)
209 #define MLX5_RXP_CSR_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
210 MLX5_RXP_CSR_WIDTH * 30)
211 #define MLX5_RXP_CSR_INTRA_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
212 MLX5_RXP_CSR_WIDTH * 31)
214 /* Runtime Rule Update CSRs */
216 #define MLX5_RXP_RTRU_CSR_CAPABILITY (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
217 MLX5_RXP_CSR_WIDTH * 2)
219 #define MLX5_RXP_RTRU_CSR_STATUS (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
220 MLX5_RXP_CSR_WIDTH * 10)
221 #define MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE 0x0002
222 #define MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE 0x0010
223 #define MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE 0x0020
224 #define MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE 0x0040
225 #define MLX5_RXP_RTRU_CSR_STATUS_EM_INIT_DONE 0x0080
226 #define MLX5_RXP_RTRU_CSR_FIFO_STAT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
227 MLX5_RXP_CSR_WIDTH * 11)
229 #define MLX5_RXP_RTRU_CSR_CHECKSUM_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
230 MLX5_RXP_CSR_WIDTH * 16)
231 #define MLX5_RXP_RTRU_CSR_CHECKSUM_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
232 MLX5_RXP_CSR_WIDTH * 17)
233 #define MLX5_RXP_RTRU_CSR_CHECKSUM_2 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
234 MLX5_RXP_CSR_WIDTH * 18)
235 /* 19 + 20 reserved */
236 #define MLX5_RXP_RTRU_CSR_RTRU_COUNT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
237 MLX5_RXP_CSR_WIDTH * 21)
238 #define MLX5_RXP_RTRU_CSR_ROF_REV (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
239 MLX5_RXP_CSR_WIDTH * 22)
241 #define MLX5_RXP_RTRU_CSR_CTRL (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
242 MLX5_RXP_CSR_WIDTH * 24)
243 #define MLX5_RXP_RTRU_CSR_CTRL_INIT 0x0001
244 #define MLX5_RXP_RTRU_CSR_CTRL_GO 0x0002
245 #define MLX5_RXP_RTRU_CSR_CTRL_SIP 0x0004
246 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK (3 << 4)
247 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2_EM (0 << 4)
248 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2 (1 << 4)
249 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2 (2 << 4)
250 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_EM (3 << 4)
251 #define MLX5_RXP_RTRU_CSR_ADDR (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
252 MLX5_RXP_CSR_WIDTH * 25)
253 #define MLX5_RXP_RTRU_CSR_DATA_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
254 MLX5_RXP_CSR_WIDTH * 26)
255 #define MLX5_RXP_RTRU_CSR_DATA_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
256 MLX5_RXP_CSR_WIDTH * 27)
259 /* Statistics CSRs */
260 #define MLX5_RXP_STATS_CSR_CLUSTER (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
261 MLX5_RXP_CSR_WIDTH * 0)
262 #define MLX5_RXP_STATS_CSR_L2_CACHE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
263 MLX5_RXP_CSR_WIDTH * 24)
264 #define MLX5_RXP_STATS_CSR_MPFE_FIFO (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
265 MLX5_RXP_CSR_WIDTH * 25)
266 #define MLX5_RXP_STATS_CSR_PE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
267 MLX5_RXP_CSR_WIDTH * 28)
268 #define MLX5_RXP_STATS_CSR_CP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
269 MLX5_RXP_CSR_WIDTH * 30)
270 #define MLX5_RXP_STATS_CSR_DP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
271 MLX5_RXP_CSR_WIDTH * 31)
273 /* Sysmon Stats CSRs */
274 #define MLX5_RXP_SYSMON_CSR_T_FPGA (MLX5_RXP_SYSMON_BASE_ADDRESS + \
275 MLX5_RXP_CSR_WIDTH * 0)
276 #define MLX5_RXP_SYSMON_CSR_V_VCCINT (MLX5_RXP_SYSMON_BASE_ADDRESS + \
277 MLX5_RXP_CSR_WIDTH * 1)
278 #define MLX5_RXP_SYSMON_CSR_V_VCCAUX (MLX5_RXP_SYSMON_BASE_ADDRESS + \
279 MLX5_RXP_CSR_WIDTH * 2)
280 #define MLX5_RXP_SYSMON_CSR_T_U1 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
281 MLX5_RXP_CSR_WIDTH * 20)
282 #define MLX5_RXP_SYSMON_CSR_I_EDG12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
283 MLX5_RXP_CSR_WIDTH * 21)
284 #define MLX5_RXP_SYSMON_CSR_I_VCC3V3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
285 MLX5_RXP_CSR_WIDTH * 22)
286 #define MLX5_RXP_SYSMON_CSR_I_VCC2V5 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
287 MLX5_RXP_CSR_WIDTH * 23)
288 #define MLX5_RXP_SYSMON_CSR_T_U2 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
289 MLX5_RXP_CSR_WIDTH * 28)
290 #define MLX5_RXP_SYSMON_CSR_I_AUX12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
291 MLX5_RXP_CSR_WIDTH * 29)
292 #define MLX5_RXP_SYSMON_CSR_I_VCC1V8 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
293 MLX5_RXP_CSR_WIDTH * 30)
294 #define MLX5_RXP_SYSMON_CSR_I_VDDR3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
295 MLX5_RXP_CSR_WIDTH * 31)
297 /* In Service Programming CSRs */
299 /* RXP-F1 and RXP-ZYNQ specific CSRs */
300 #define MLX5_RXP_MQ_CP_BASE (0x0500ul)
301 #define MLX5_RXP_MQ_CP_CAPABILITY_BASE (MLX5_RXP_MQ_CP_BASE + \
302 2 * MLX5_RXP_CSR_WIDTH)
303 #define MLX5_RXP_MQ_CP_CAPABILITY_0 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
304 0 * MLX5_RXP_CSR_WIDTH)
305 #define MLX5_RXP_MQ_CP_CAPABILITY_1 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
306 1 * MLX5_RXP_CSR_WIDTH)
307 #define MLX5_RXP_MQ_CP_CAPABILITY_2 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
308 2 * MLX5_RXP_CSR_WIDTH)
309 #define MLX5_RXP_MQ_CP_CAPABILITY_3 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
310 3 * MLX5_RXP_CSR_WIDTH)
311 #define MLX5_RXP_MQ_CP_FIFO_STATUS_BASE (MLX5_RXP_MQ_CP_BASE + \
312 11 * MLX5_RXP_CSR_WIDTH)
313 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C0 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
314 0 * MLX5_RXP_CSR_WIDTH)
315 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C1 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
316 1 * MLX5_RXP_CSR_WIDTH)
317 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C2 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
318 2 * MLX5_RXP_CSR_WIDTH)
319 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C3 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
320 3 * MLX5_RXP_CSR_WIDTH)
322 /* Royalty tracker / licensing related CSRs */
323 #define MLX5_RXPL__CSR_IDENT (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
324 0 * MLX5_RXP_CSR_WIDTH)
325 #define MLX5_RXPL__IDENTIFIER 0x4c505852 /* MLX5_RXPL_ */
326 #define MLX5_RXPL__CSR_CAPABILITY (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
327 2 * MLX5_RXP_CSR_WIDTH)
328 #define MLX5_RXPL__TYPE_MASK 0xFF
329 #define MLX5_RXPL__TYPE_NONE 0
330 #define MLX5_RXPL__TYPE_MAXIM 1
331 #define MLX5_RXPL__TYPE_XILINX_DNA 2
332 #define MLX5_RXPL__CSR_STATUS (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
333 10 * MLX5_RXP_CSR_WIDTH)
334 #define MLX5_RXPL__CSR_IDENT_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
335 16 * MLX5_RXP_CSR_WIDTH)
336 #define MLX5_RXPL__CSR_KEY_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
337 24 * MLX5_RXP_CSR_WIDTH)
339 #endif /* _MLX5_RXP_CSRS_H_ */