1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
8 #include <rte_malloc.h>
10 #include <rte_lcore.h>
11 #include <rte_atomic.h>
12 #include <rte_common.h>
15 #include <mlx5_common.h>
17 #include "mlx5_vdpa_utils.h"
18 #include "mlx5_vdpa.h"
22 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
25 mlx5_glue->devx_free_uar(priv->uar);
29 mlx5_glue->devx_destroy_event_channel(priv->eventc);
35 /* Prepare all the global resources for all the event objects.*/
37 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
43 lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
44 if (mlx5_glue->devx_query_eqn(priv->ctx, lcore, &priv->eqn)) {
46 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
49 priv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,
50 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
53 DRV_LOG(ERR, "Failed to create event channel %d.",
57 priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
60 DRV_LOG(ERR, "Failed to allocate UAR.");
65 mlx5_vdpa_event_qp_global_release(priv);
70 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
73 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
75 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
77 rte_free((void *)(uintptr_t)cq->umem_buf);
78 memset(cq, 0, sizeof(*cq));
82 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
84 const unsigned int cqe_mask = (1 << cq->log_desc_n) - 1;
85 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
86 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK & cqe_mask;
87 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
88 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
89 uint64_t db_be = rte_cpu_to_be_64(doorbell);
90 uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
93 cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
96 *(uint64_t *)addr = db_be;
98 *(uint32_t *)addr = db_be;
100 *((uint32_t *)addr + 1) = db_be >> 32;
106 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
107 int callfd, struct mlx5_vdpa_cq *cq)
109 struct mlx5_devx_cq_attr attr;
110 size_t pgsize = sysconf(_SC_PAGESIZE);
113 uint16_t event_nums[1] = {0};
115 cq->log_desc_n = log_desc_n;
116 umem_size = sizeof(struct mlx5_cqe) * (1 << log_desc_n) +
117 sizeof(*cq->db_rec) * 2;
118 cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
120 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
124 cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
125 (void *)(uintptr_t)cq->umem_buf,
127 IBV_ACCESS_LOCAL_WRITE);
129 DRV_LOG(ERR, "Failed to register umem for CQ.");
132 attr.q_umem_valid = 1;
133 attr.db_umem_valid = 1;
134 attr.use_first_only = 0;
135 attr.overrun_ignore = 0;
136 attr.uar_page_id = priv->uar->page_id;
137 attr.q_umem_id = cq->umem_obj->umem_id;
138 attr.q_umem_offset = 0;
139 attr.db_umem_id = cq->umem_obj->umem_id;
140 attr.db_umem_offset = sizeof(struct mlx5_cqe) * (1 << log_desc_n);
141 attr.eqn = priv->eqn;
142 attr.log_cq_size = log_desc_n;
143 attr.log_page_size = rte_log2_u32(pgsize);
144 cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
147 cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
149 rte_spinlock_init(&cq->sl);
150 /* Subscribe CQ event to the event channel controlled by the driver. */
151 ret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
154 (uint64_t)(uintptr_t)cq);
156 DRV_LOG(ERR, "Failed to subscribe CQE event.");
160 /* Subscribe CQ event to the guest FD only if it is not in poll mode. */
162 ret = mlx5_glue->devx_subscribe_devx_event_fd(priv->eventc,
166 DRV_LOG(ERR, "Failed to subscribe CQE event fd.");
172 mlx5_vdpa_cq_arm(priv, cq);
175 mlx5_vdpa_cq_destroy(cq);
179 static inline void __rte_unused
180 mlx5_vdpa_cq_poll(struct mlx5_vdpa_priv *priv __rte_unused,
181 struct mlx5_vdpa_cq *cq)
183 struct mlx5_vdpa_event_qp *eqp =
184 container_of(cq, struct mlx5_vdpa_event_qp, cq);
185 const unsigned int cqe_size = 1 << cq->log_desc_n;
186 const unsigned int cqe_mask = cqe_size - 1;
190 volatile struct mlx5_cqe *cqe = cq->cqes + (cq->cq_ci &
193 ret = check_cqe(cqe, cqe_size, cq->cq_ci);
195 case MLX5_CQE_STATUS_ERR:
198 case MLX5_CQE_STATUS_SW_OWN:
201 case MLX5_CQE_STATUS_HW_OWN:
205 } while (ret != MLX5_CQE_STATUS_HW_OWN);
207 /* Ring CQ doorbell record. */
208 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
210 /* Ring SW QP doorbell record. */
211 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cqe_size);
215 mlx5_vdpa_interrupt_handler(void *cb_arg)
217 #ifndef HAVE_IBV_DEVX_EVENT
221 struct mlx5_vdpa_priv *priv = cb_arg;
223 struct mlx5dv_devx_async_event_hdr event_resp;
224 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
227 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
229 (ssize_t)sizeof(out.event_resp.cookie)) {
230 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
231 (uintptr_t)out.event_resp.cookie;
232 rte_spinlock_lock(&cq->sl);
233 mlx5_vdpa_cq_poll(priv, cq);
234 mlx5_vdpa_cq_arm(priv, cq);
235 rte_spinlock_unlock(&cq->sl);
236 DRV_LOG(DEBUG, "CQ %d event: new cq_ci = %u.", cq->cq->id,
239 #endif /* HAVE_IBV_DEVX_ASYNC */
243 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
245 int flags = fcntl(priv->eventc->fd, F_GETFL);
246 int ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
248 DRV_LOG(ERR, "Failed to change event channel FD.");
252 priv->intr_handle.fd = priv->eventc->fd;
253 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
254 if (rte_intr_callback_register(&priv->intr_handle,
255 mlx5_vdpa_interrupt_handler, priv)) {
256 priv->intr_handle.fd = 0;
257 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
264 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
266 int retries = MLX5_VDPA_INTR_RETRIES;
269 if (priv->intr_handle.fd) {
270 while (retries-- && ret == -EAGAIN) {
271 ret = rte_intr_callback_unregister(&priv->intr_handle,
272 mlx5_vdpa_interrupt_handler,
274 if (ret == -EAGAIN) {
275 DRV_LOG(DEBUG, "Try again to unregister fd %d "
276 "of CQ interrupt, retries = %d.",
277 priv->intr_handle.fd, retries);
278 usleep(MLX5_VDPA_INTR_RETRIES_USEC);
281 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
286 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
289 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
291 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
293 rte_free(eqp->umem_buf);
295 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
296 mlx5_vdpa_cq_destroy(&eqp->cq);
297 memset(eqp, 0, sizeof(*eqp));
301 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
303 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
305 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
309 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
311 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
315 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
317 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
321 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
323 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
327 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
329 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
333 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
335 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
343 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
344 int callfd, struct mlx5_vdpa_event_qp *eqp)
346 struct mlx5_devx_qp_attr attr = {0};
347 uint16_t log_desc_n = rte_log2_u32(desc_n);
348 uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
349 sizeof(*eqp->db_rec) * 2;
351 if (mlx5_vdpa_event_qp_global_prepare(priv))
353 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
356 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
358 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
361 eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
362 if (!eqp->umem_buf) {
363 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
367 eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
368 (void *)(uintptr_t)eqp->umem_buf,
370 IBV_ACCESS_LOCAL_WRITE);
371 if (!eqp->umem_obj) {
372 DRV_LOG(ERR, "Failed to register umem for SW QP.");
375 attr.uar_index = priv->uar->page_id;
376 attr.cqn = eqp->cq.cq->id;
377 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
378 attr.rq_size = 1 << log_desc_n;
379 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
380 attr.sq_size = 0; /* No need SQ. */
381 attr.dbr_umem_valid = 1;
382 attr.wq_umem_id = eqp->umem_obj->umem_id;
383 attr.wq_umem_offset = 0;
384 attr.dbr_umem_id = eqp->umem_obj->umem_id;
385 attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
386 eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
388 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
391 eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
392 if (mlx5_vdpa_qps2rts(eqp))
395 rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
398 mlx5_vdpa_event_qp_destroy(eqp);