2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER1_AVAILABLE
88 #define TIMER1A_AVAILABLE
89 #define TIMER1B_AVAILABLE
90 #define TIMER2_AVAILABLE
92 /* overflow interrupt number */
93 #define SIG_OVERFLOW0_NUM 0
94 #define SIG_OVERFLOW1_NUM 1
95 #define SIG_OVERFLOW2_NUM 2
96 #define SIG_OVERFLOW_TOTAL_NUM 3
98 /* output compare interrupt number */
99 #define SIG_OUTPUT_COMPARE0_NUM 0
100 #define SIG_OUTPUT_COMPARE1A_NUM 1
101 #define SIG_OUTPUT_COMPARE1B_NUM 2
102 #define SIG_OUTPUT_COMPARE2_NUM 3
103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
110 #define PWM_TOTAL_NUM 4
112 /* input capture interrupt number */
113 #define SIG_INPUT_CAPTURE1_NUM 0
114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
118 #define SPDR0_REG SPDR
119 #define SPDR1_REG SPDR
120 #define SPDR2_REG SPDR
121 #define SPDR3_REG SPDR
122 #define SPDR4_REG SPDR
123 #define SPDR5_REG SPDR
124 #define SPDR6_REG SPDR
125 #define SPDR7_REG SPDR
128 #define CLKPS0_REG CLKPR
129 #define CLKPS1_REG CLKPR
130 #define CLKPS2_REG CLKPR
131 #define CLKPS3_REG CLKPR
132 #define CLKPCE_REG CLKPR
135 #define WDP0_REG WDTCR
136 #define WDP1_REG WDTCR
137 #define WDP2_REG WDTCR
138 #define WDE_REG WDTCR
139 #define WDTOE_REG WDTCR
142 #define ICR1H0_REG ICR1H
143 #define ICR1H1_REG ICR1H
144 #define ICR1H2_REG ICR1H
145 #define ICR1H3_REG ICR1H
146 #define ICR1H4_REG ICR1H
147 #define ICR1H5_REG ICR1H
148 #define ICR1H6_REG ICR1H
149 #define ICR1H7_REG ICR1H
152 #define TXB81_REG UCSR1B
153 #define RXB81_REG UCSR1B
154 #define UCSZ12_REG UCSR1B
155 #define TXEN1_REG UCSR1B
156 #define RXEN1_REG UCSR1B
157 #define UDRIE1_REG UCSR1B
158 #define TXCIE1_REG UCSR1B
159 #define RXCIE1_REG UCSR1B
162 #define UCPOL1_REG UCSR1C
163 #define UCSZ10_REG UCSR1C
164 #define UCSZ11_REG UCSR1C
165 #define USBS1_REG UCSR1C
166 #define UPM10_REG UCSR1C
167 #define UPM11_REG UCSR1C
168 #define UMSEL1_REG UCSR1C
169 #define URSEL1_REG UCSR1C
172 #define MPCM1_REG UCSR1A
173 #define U2X1_REG UCSR1A
174 #define UPE1_REG UCSR1A
175 #define DOR1_REG UCSR1A
176 #define FE1_REG UCSR1A
177 #define UDRE1_REG UCSR1A
178 #define TXC1_REG UCSR1A
179 #define RXC1_REG UCSR1A
182 #define CS00_REG TCCR0
183 #define CS01_REG TCCR0
184 #define CS02_REG TCCR0
185 #define WGM01_REG TCCR0
186 #define COM00_REG TCCR0
187 #define COM01_REG TCCR0
188 #define WGM00_REG TCCR0
189 #define FOC0_REG TCCR0
202 #define DDB0_REG DDRB
203 #define DDB1_REG DDRB
204 #define DDB2_REG DDRB
205 #define DDB3_REG DDRB
206 #define DDB4_REG DDRB
207 #define DDB5_REG DDRB
208 #define DDB6_REG DDRB
209 #define DDB7_REG DDRB
212 #define IVCE_REG GICR
213 #define IVSEL_REG GICR
214 #define PCIE0_REG GICR
215 #define PCIE1_REG GICR
216 #define INT2_REG GICR
217 #define INT0_REG GICR
218 #define INT1_REG GICR
221 #define SPI2X_REG SPSR
222 #define WCOL_REG SPSR
223 #define SPIF_REG SPSR
226 #define EEDR0_REG EEDR
227 #define EEDR1_REG EEDR
228 #define EEDR2_REG EEDR
229 #define EEDR3_REG EEDR
230 #define EEDR4_REG EEDR
231 #define EEDR5_REG EEDR
232 #define EEDR6_REG EEDR
233 #define EEDR7_REG EEDR
236 #define DDC0_REG DDRC
237 #define DDC1_REG DDRC
238 #define DDC2_REG DDRC
239 #define DDC3_REG DDRC
240 #define DDC4_REG DDRC
241 #define DDC5_REG DDRC
242 #define DDC6_REG DDRC
243 #define DDC7_REG DDRC
246 #define DDA0_REG DDRA
247 #define DDA1_REG DDRA
248 #define DDA2_REG DDRA
249 #define DDA3_REG DDRA
250 #define DDA4_REG DDRA
251 #define DDA5_REG DDRA
252 #define DDA6_REG DDRA
253 #define DDA7_REG DDRA
256 #define WGM10_REG TCCR1A
257 #define WGM11_REG TCCR1A
258 #define FOC1B_REG TCCR1A
259 #define FOC1A_REG TCCR1A
260 #define COM1B0_REG TCCR1A
261 #define COM1B1_REG TCCR1A
262 #define COM1A0_REG TCCR1A
263 #define COM1A1_REG TCCR1A
266 #define DDD0_REG DDRD
267 #define DDD1_REG DDRD
268 #define DDD2_REG DDRD
269 #define DDD3_REG DDRD
270 #define DDD4_REG DDRD
271 #define DDD5_REG DDRD
272 #define DDD6_REG DDRD
273 #define DDD7_REG DDRD
276 #define CS10_REG TCCR1B
277 #define CS11_REG TCCR1B
278 #define CS12_REG TCCR1B
279 #define CTC1_REG TCCR1B
280 #define ICES1_REG TCCR1B
281 #define ICNC1_REG TCCR1B
284 #define PCIF0_REG GIFR
285 #define PCIF1_REG GIFR
286 #define INTF2_REG GIFR
287 #define INTF0_REG GIFR
288 #define INTF1_REG GIFR
291 #define OCIE0_REG TIMSK
292 #define TOIE0_REG TIMSK
293 #define TICIE1_REG TIMSK
294 #define OCIE1B_REG TIMSK
295 #define OCIE1A_REG TIMSK
296 #define TOIE1_REG TIMSK
297 #define TOIE2_REG TIMSK
298 #define OCIE2_REG TIMSK
301 /* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
302 /* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
303 /* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
304 /* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
305 /* #define URSEL0_REG UBRR0H */ /* dup in UCSR0C */
308 /* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
309 /* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
310 /* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
311 /* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
314 #define ICR1L0_REG ICR1L
315 #define ICR1L1_REG ICR1L
316 #define ICR1L2_REG ICR1L
317 #define ICR1L3_REG ICR1L
318 #define ICR1L4_REG ICR1L
319 #define ICR1L5_REG ICR1L
320 #define ICR1L6_REG ICR1L
321 #define ICR1L7_REG ICR1L
324 #define PSR10_REG SFIOR
325 #define PSR310_REG SFIOR
326 #define PSR2_REG SFIOR
327 #define PUD_REG SFIOR
328 #define XMM0_REG SFIOR
329 #define XMM1_REG SFIOR
330 #define XMM2_REG SFIOR
331 #define XMBK_REG SFIOR
332 #define TSM_REG SFIOR
335 #define UDR0_0_REG UDR0
336 #define UDR0_1_REG UDR0
337 #define UDR0_2_REG UDR0
338 #define UDR0_3_REG UDR0
339 #define UDR0_4_REG UDR0
340 #define UDR0_5_REG UDR0
341 #define UDR0_6_REG UDR0
342 #define UDR0_7_REG UDR0
355 #define OCR1BL0_REG OCR1BL
356 #define OCR1BL1_REG OCR1BL
357 #define OCR1BL2_REG OCR1BL
358 #define OCR1BL3_REG OCR1BL
359 #define OCR1BL4_REG OCR1BL
360 #define OCR1BL5_REG OCR1BL
361 #define OCR1BL6_REG OCR1BL
362 #define OCR1BL7_REG OCR1BL
365 #define ISC2_REG EMCUCR
366 #define SRW11_REG EMCUCR
367 #define SRW00_REG EMCUCR
368 #define SRW01_REG EMCUCR
369 #define SRL0_REG EMCUCR
370 #define SRL1_REG EMCUCR
371 #define SRL2_REG EMCUCR
372 #define SM0_REG EMCUCR
385 #define OCR1BH0_REG OCR1BH
386 #define OCR1BH1_REG OCR1BH
387 #define OCR1BH2_REG OCR1BH
388 #define OCR1BH3_REG OCR1BH
389 #define OCR1BH4_REG OCR1BH
390 #define OCR1BH5_REG OCR1BH
391 #define OCR1BH6_REG OCR1BH
392 #define OCR1BH7_REG OCR1BH
395 #define PIND0_REG PIND
396 #define PIND1_REG PIND
397 #define PIND2_REG PIND
398 #define PIND3_REG PIND
399 #define PIND4_REG PIND
400 #define PIND5_REG PIND
401 #define PIND6_REG PIND
402 #define PIND7_REG PIND
405 #define SPMEN_REG SPMCR
406 #define PGERS_REG SPMCR
407 #define PGWRT_REG SPMCR
408 #define BLBSET_REG SPMCR
409 #define RWWSRE_REG SPMCR
410 #define RWWSB_REG SPMCR
411 #define SPMIE_REG SPMCR
414 #define DDE0_REG DDRE
415 #define DDE1_REG DDRE
416 #define DDE2_REG DDRE
419 #define PORTD0_REG PORTD
420 #define PORTD1_REG PORTD
421 #define PORTD2_REG PORTD
422 #define PORTD3_REG PORTD
423 #define PORTD4_REG PORTD
424 #define PORTD5_REG PORTD
425 #define PORTD6_REG PORTD
426 #define PORTD7_REG PORTD
429 #define ACIS0_REG ACSR
430 #define ACIS1_REG ACSR
431 #define ACIC_REG ACSR
432 #define ACIE_REG ACSR
435 #define ACBG_REG ACSR
439 #define EERE_REG EECR
440 #define EEWE_REG EECR
441 #define EEMWE_REG EECR
442 #define EERIE_REG EECR
445 #define PORTE0_REG PORTE
446 #define PORTE1_REG PORTE
447 #define PORTE2_REG PORTE
450 #define CAL0_REG OSCCAL
451 #define CAL1_REG OSCCAL
452 #define CAL2_REG OSCCAL
453 #define CAL3_REG OSCCAL
454 #define CAL4_REG OSCCAL
455 #define CAL5_REG OSCCAL
456 #define CAL6_REG OSCCAL
459 #define TCNT1L0_REG TCNT1L
460 #define TCNT1L1_REG TCNT1L
461 #define TCNT1L2_REG TCNT1L
462 #define TCNT1L3_REG TCNT1L
463 #define TCNT1L4_REG TCNT1L
464 #define TCNT1L5_REG TCNT1L
465 #define TCNT1L6_REG TCNT1L
466 #define TCNT1L7_REG TCNT1L
469 #define PORTB0_REG PORTB
470 #define PORTB1_REG PORTB
471 #define PORTB2_REG PORTB
472 #define PORTB3_REG PORTB
473 #define PORTB4_REG PORTB
474 #define PORTB5_REG PORTB
475 #define PORTB6_REG PORTB
476 #define PORTB7_REG PORTB
479 #define UCPOL0_REG UCSR0C
480 #define UCSZ00_REG UCSR0C
481 #define UCSZ01_REG UCSR0C
482 #define USBS0_REG UCSR0C
483 #define UPM00_REG UCSR0C
484 #define UPM01_REG UCSR0C
485 #define UMSEL0_REG UCSR0C
486 /* #define URSEL0_REG UCSR0C */ /* dup in UBRR0H */
489 #define TXB80_REG UCSR0B
490 #define RXB80_REG UCSR0B
491 #define UCSZ02_REG UCSR0B
492 #define TXEN0_REG UCSR0B
493 #define RXEN0_REG UCSR0B
494 #define UDRIE0_REG UCSR0B
495 #define TXCIE0_REG UCSR0B
496 #define RXCIE0_REG UCSR0B
499 #define TCNT1H0_REG TCNT1H
500 #define TCNT1H1_REG TCNT1H
501 #define TCNT1H2_REG TCNT1H
502 #define TCNT1H3_REG TCNT1H
503 #define TCNT1H4_REG TCNT1H
504 #define TCNT1H5_REG TCNT1H
505 #define TCNT1H6_REG TCNT1H
506 #define TCNT1H7_REG TCNT1H
509 #define PORTC0_REG PORTC
510 #define PORTC1_REG PORTC
511 #define PORTC2_REG PORTC
512 #define PORTC3_REG PORTC
513 #define PORTC4_REG PORTC
514 #define PORTC5_REG PORTC
515 #define PORTC6_REG PORTC
516 #define PORTC7_REG PORTC
519 #define PORTA0_REG PORTA
520 #define PORTA1_REG PORTA
521 #define PORTA2_REG PORTA
522 #define PORTA3_REG PORTA
523 #define PORTA4_REG PORTA
524 #define PORTA5_REG PORTA
525 #define PORTA6_REG PORTA
526 #define PORTA7_REG PORTA
529 #define TCNT2_0_REG TCNT2
530 #define TCNT2_1_REG TCNT2
531 #define TCNT2_2_REG TCNT2
532 #define TCNT2_3_REG TCNT2
533 #define TCNT2_4_REG TCNT2
534 #define TCNT2_5_REG TCNT2
535 #define TCNT2_6_REG TCNT2
536 #define TCNT2_7_REG TCNT2
539 #define TCNT0_0_REG TCNT0
540 #define TCNT0_1_REG TCNT0
541 #define TCNT0_2_REG TCNT0
542 #define TCNT0_3_REG TCNT0
543 #define TCNT0_4_REG TCNT0
544 #define TCNT0_5_REG TCNT0
545 #define TCNT0_6_REG TCNT0
546 #define TCNT0_7_REG TCNT0
549 #define PORF_REG MCUCSR
550 #define EXTRF_REG MCUCSR
551 #define BORF_REG MCUCSR
552 #define WDRF_REG MCUCSR
553 #define JTRF_REG MCUCSR
554 #define SM2_REG MCUCSR
555 #define JDT_REG MCUCSR
558 #define MPCM0_REG UCSR0A
559 #define U2X0_REG UCSR0A
560 #define UPE0_REG UCSR0A
561 #define DOR0_REG UCSR0A
562 #define FE0_REG UCSR0A
563 #define UDRE0_REG UCSR0A
564 #define TXC0_REG UCSR0A
565 #define RXC0_REG UCSR0A
568 #define EEAR0_REG EEARL
569 #define EEAR1_REG EEARL
570 #define EEAR2_REG EEARL
571 #define EEAR3_REG EEARL
572 #define EEAR4_REG EEARL
573 #define EEAR5_REG EEARL
574 #define EEAR6_REG EEARL
575 #define EEAR7_REG EEARL
578 #define UBRR1L0_REG UBRR1L
579 #define UBRR1L1_REG UBRR1L
580 #define UBRR1L2_REG UBRR1L
581 #define UBRR1L3_REG UBRR1L
582 #define UBRR1L4_REG UBRR1L
583 #define UBRR1L5_REG UBRR1L
584 #define UBRR1L6_REG UBRR1L
585 #define UBRR1L7_REG UBRR1L
588 #define CS20_REG TCCR2
589 #define CS21_REG TCCR2
590 #define CS22_REG TCCR2
591 #define WGM21_REG TCCR2
592 #define COM20_REG TCCR2
593 #define COM21_REG TCCR2
594 #define WGM20_REG TCCR2
595 #define FOC2_REG TCCR2
598 #define UDR1_0_REG UDR1
599 #define UDR1_1_REG UDR1
600 #define UDR1_2_REG UDR1
601 #define UDR1_3_REG UDR1
602 #define UDR1_4_REG UDR1
603 #define UDR1_5_REG UDR1
604 #define UDR1_6_REG UDR1
605 #define UDR1_7_REG UDR1
608 #define OCF0_REG TIFR
609 #define TOV0_REG TIFR
610 #define ICF1_REG TIFR
611 #define OCF1B_REG TIFR
612 #define OCF1A_REG TIFR
613 #define TOV1_REG TIFR
614 #define TOV2_REG TIFR
615 #define OCF2_REG TIFR
618 #define UBRR0_REG UBRR0L
619 #define UBRR1_REG UBRR0L
620 #define UBRR2_REG UBRR0L
621 #define UBRR3_REG UBRR0L
622 #define UBRR4_REG UBRR0L
623 #define UBRR5_REG UBRR0L
624 #define UBRR6_REG UBRR0L
625 #define UBRR7_REG UBRR0L
628 #define EEAR8_REG EEARH
631 #define PCINT0_REG PCMSK0
632 #define PCINT1_REG PCMSK0
633 #define PCINT2_REG PCMSK0
634 #define PCINT3_REG PCMSK0
635 #define PCINT4_REG PCMSK0
636 #define PCINT5_REG PCMSK0
637 #define PCINT6_REG PCMSK0
638 #define PCINT7_REG PCMSK0
641 #define PCINT8_REG PCMSK1
642 #define PCINT9_REG PCMSK1
643 #define PCINT10_REG PCMSK1
644 #define PCINT11_REG PCMSK1
645 #define PCINT12_REG PCMSK1
646 #define PCINT13_REG PCMSK1
647 #define PCINT14_REG PCMSK1
648 #define PCINT15_REG PCMSK1
651 #define PINC0_REG PINC
652 #define PINC1_REG PINC
653 #define PINC2_REG PINC
654 #define PINC3_REG PINC
655 #define PINC4_REG PINC
656 #define PINC5_REG PINC
657 #define PINC6_REG PINC
658 #define PINC7_REG PINC
661 #define PINB0_REG PINB
662 #define PINB1_REG PINB
663 #define PINB2_REG PINB
664 #define PINB3_REG PINB
665 #define PINB4_REG PINB
666 #define PINB5_REG PINB
667 #define PINB6_REG PINB
668 #define PINB7_REG PINB
671 #define PINA0_REG PINA
672 #define PINA1_REG PINA
673 #define PINA2_REG PINA
674 #define PINA3_REG PINA
675 #define PINA4_REG PINA
676 #define PINA5_REG PINA
677 #define PINA6_REG PINA
678 #define PINA7_REG PINA
681 #define PINE0_REG PINE
682 #define PINE1_REG PINE
683 #define PINE2_REG PINE
686 #define ISC00_REG MCUCR
687 #define ISC01_REG MCUCR
688 #define ISC10_REG MCUCR
689 #define ISC11_REG MCUCR
690 #define SM1_REG MCUCR
692 #define SRW10_REG MCUCR
693 #define SRE_REG MCUCR
696 #define OCR1AH0_REG OCR1AH
697 #define OCR1AH1_REG OCR1AH
698 #define OCR1AH2_REG OCR1AH
699 #define OCR1AH3_REG OCR1AH
700 #define OCR1AH4_REG OCR1AH
701 #define OCR1AH5_REG OCR1AH
702 #define OCR1AH6_REG OCR1AH
703 #define OCR1AH7_REG OCR1AH
706 #define OCR1AL0_REG OCR1AL
707 #define OCR1AL1_REG OCR1AL
708 #define OCR1AL2_REG OCR1AL
709 #define OCR1AL3_REG OCR1AL
710 #define OCR1AL4_REG OCR1AL
711 #define OCR1AL5_REG OCR1AL
712 #define OCR1AL6_REG OCR1AL
713 #define OCR1AL7_REG OCR1AL
716 #define SPR0_REG SPCR
717 #define SPR1_REG SPCR
718 #define CPHA_REG SPCR
719 #define CPOL_REG SPCR
720 #define MSTR_REG SPCR
721 #define DORD_REG SPCR
723 #define SPIE_REG SPCR
726 #define OCR0_0_REG OCR0
727 #define OCR0_1_REG OCR0
728 #define OCR0_2_REG OCR0
729 #define OCR0_3_REG OCR0
730 #define OCR0_4_REG OCR0
731 #define OCR0_5_REG OCR0
732 #define OCR0_6_REG OCR0
733 #define OCR0_7_REG OCR0
736 #define OCR2_0_REG OCR2
737 #define OCR2_1_REG OCR2
738 #define OCR2_2_REG OCR2
739 #define OCR2_3_REG OCR2
740 #define OCR2_4_REG OCR2
741 #define OCR2_5_REG OCR2
742 #define OCR2_6_REG OCR2
743 #define OCR2_7_REG OCR2
746 #define TCR2UB_REG ASSR
747 #define OCR2UB_REG ASSR
748 #define TCN2UB_REG ASSR
752 #define AD0_PORT PORTA
755 #define AD1_PORT PORTA
758 #define AD2_PORT PORTA
761 #define AD3_PORT PORTA
764 #define AD4_PORT PORTA
767 #define AD5_PORT PORTA
770 #define AD6_PORT PORTA
773 #define AD7_PORT PORTA
776 #define OC0/T0_PORT PORTB
779 #define OC2/T1_PORT PORTB
782 #define RXD1_PORT PORTB
784 #define AIN0_PORT PORTB
787 #define TXD1_PORT PORTB
789 #define AIN1_PORT PORTB
792 #define SS_PORT PORTB
795 #define MOSI_PORT PORTB
798 #define MISO_PORT PORTB
801 #define SCK_PORT PORTB
804 #define A8_PORT PORTC
807 #define A9_PORT PORTC
810 #define A10_PORT PORTC
813 #define A11_PORT PORTC
816 #define A12_PORT PORTC
819 #define A13_PORT PORTC
822 #define A14_PORT PORTC
825 #define A15_PORT PORTC
828 #define RXD_PORT PORTD
831 #define TXD_PORT PORTD
834 #define INT0_PORT PORTD
837 #define INT1_PORT PORTD
841 #define OC1A_PORT PORTD
843 #define TOSC2_PORT PORTD
846 #define WR_PORT PORTD
849 #define RD_PORT PORTD
852 #define ICP/INT2_PORT PORTE
853 #define ICP/INT2_BIT 0
855 #define ALE_PORT PORTE
858 #define OC1B_PORT PORTE