2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_2 2
50 #define TIMER1_PRESCALER_DIV_4 3
51 #define TIMER1_PRESCALER_DIV_8 4
52 #define TIMER1_PRESCALER_DIV_16 5
53 #define TIMER1_PRESCALER_DIV_32 6
54 #define TIMER1_PRESCALER_DIV_64 7
55 #define TIMER1_PRESCALER_DIV_128 8
56 #define TIMER1_PRESCALER_DIV_256 9
57 #define TIMER1_PRESCALER_DIV_512 10
58 #define TIMER1_PRESCALER_DIV_1024 11
59 #define TIMER1_PRESCALER_DIV_2048 12
60 #define TIMER1_PRESCALER_DIV_4096 13
61 #define TIMER1_PRESCALER_DIV_8192 14
62 #define TIMER1_PRESCALER_DIV_16384 15
64 #define TIMER1_PRESCALER_REG_0 0
65 #define TIMER1_PRESCALER_REG_1 1
66 #define TIMER1_PRESCALER_REG_2 2
67 #define TIMER1_PRESCALER_REG_3 4
68 #define TIMER1_PRESCALER_REG_4 8
69 #define TIMER1_PRESCALER_REG_5 16
70 #define TIMER1_PRESCALER_REG_6 32
71 #define TIMER1_PRESCALER_REG_7 64
72 #define TIMER1_PRESCALER_REG_8 128
73 #define TIMER1_PRESCALER_REG_9 256
74 #define TIMER1_PRESCALER_REG_10 512
75 #define TIMER1_PRESCALER_REG_11 1024
76 #define TIMER1_PRESCALER_REG_12 2048
77 #define TIMER1_PRESCALER_REG_13 4096
78 #define TIMER1_PRESCALER_REG_14 8192
79 #define TIMER1_PRESCALER_REG_15 16384
82 /* available timers */
83 #define TIMER0_AVAILABLE
84 #define TIMER1_AVAILABLE
86 /* overflow interrupt number */
87 #define SIG_OVERFLOW0_NUM 0
88 #define SIG_OVERFLOW1_NUM 1
89 #define SIG_OVERFLOW_TOTAL_NUM 2
91 /* output compare interrupt number */
92 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
95 #define PWM_TOTAL_NUM 0
97 /* input capture interrupt number */
98 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
102 #define WDP0_REG WDTCR
103 #define WDP1_REG WDTCR
104 #define WDP2_REG WDTCR
105 #define WDE_REG WDTCR
106 #define WDCE_REG WDTCR
109 #define PCIE0_REG GIMSK
110 #define PCIE1_REG GIMSK
111 #define INT0_REG GIMSK
114 #define MUX0_REG ADMUX
115 #define MUX1_REG ADMUX
116 #define MUX2_REG ADMUX
117 #define MUX3_REG ADMUX
118 #define MUX4_REG ADMUX
119 #define ADLAR_REG ADMUX
120 #define REFS0_REG ADMUX
121 #define REFS1_REG ADMUX
124 #define CS00_REG TCCR0
125 #define CS01_REG TCCR0
126 #define CS02_REG TCCR0
127 #define PSR0_REG TCCR0
140 #define DDB0_REG DDRB
141 #define DDB1_REG DDRB
142 #define DDB2_REG DDRB
143 #define DDB3_REG DDRB
144 #define DDB4_REG DDRB
145 #define DDB5_REG DDRB
146 #define DDB6_REG DDRB
147 #define DDB7_REG DDRB
150 #define EEDR0_REG EEDR
151 #define EEDR1_REG EEDR
152 #define EEDR2_REG EEDR
153 #define EEDR3_REG EEDR
154 #define EEDR4_REG EEDR
155 #define EEDR5_REG EEDR
156 #define EEDR6_REG EEDR
157 #define EEDR7_REG EEDR
160 #define ISC00_REG MCUCR
161 #define ISC01_REG MCUCR
162 #define SM0_REG MCUCR
163 #define SM1_REG MCUCR
165 #define PUD_REG MCUCR
168 #define PWM1B_REG TCCR1A
169 #define PWM1A_REG TCCR1A
170 #define FOC1B_REG TCCR1A
171 #define FOC1A_REG TCCR1A
172 #define COM1B0_REG TCCR1A
173 #define COM1B1_REG TCCR1A
174 #define COM1A0_REG TCCR1A
175 #define COM1A1_REG TCCR1A
178 #define CS10_REG TCCR1B
179 #define CS11_REG TCCR1B
180 #define CS12_REG TCCR1B
181 #define CS13_REG TCCR1B
182 #define PSR1_REG TCCR1B
183 #define CTC1_REG TCCR1B
186 #define PCIF_REG GIFR
187 #define INTF0_REG GIFR
190 #define TOIE0_REG TIMSK
191 #define TOIE1_REG TIMSK
192 #define OCIE1B_REG TIMSK
193 #define OCIE1A_REG TIMSK
196 #define DDA0_REG DDRA
197 #define DDA1_REG DDRA
198 #define DDA2_REG DDRA
199 #define DDA3_REG DDRA
200 #define DDA4_REG DDRA
201 #define DDA5_REG DDRA
202 #define DDA6_REG DDRA
203 #define DDA7_REG DDRA
206 #define ACIS0_REG ACSR
207 #define ACIS1_REG ACSR
208 #define ACME_REG ACSR
209 #define ACIE_REG ACSR
212 #define ACBG_REG ACSR
216 #define USITC_REG USICR
217 #define USICLK_REG USICR
218 #define USICS0_REG USICR
219 #define USICS1_REG USICR
220 #define USIWM0_REG USICR
221 #define USIWM1_REG USICR
222 #define USIOIE_REG USICR
223 #define USISIE_REG USICR
226 #define PORF_REG MCUSR
227 #define EXTRF_REG MCUSR
228 #define BORF_REG MCUSR
229 #define WDRF_REG MCUSR
232 #define EERE_REG EECR
233 #define EEWE_REG EECR
234 #define EEMWE_REG EECR
235 #define EERIE_REG EECR
238 #define USICNT0_REG USISR
239 #define USICNT1_REG USISR
240 #define USICNT2_REG USISR
241 #define USICNT3_REG USISR
242 #define USIDC_REG USISR
243 #define USIPF_REG USISR
244 #define USIOIF_REG USISR
245 #define USISIF_REG USISR
248 #define CAL0_REG OSCCAL
249 #define CAL1_REG OSCCAL
250 #define CAL2_REG OSCCAL
251 #define CAL3_REG OSCCAL
252 #define CAL4_REG OSCCAL
253 #define CAL5_REG OSCCAL
254 #define CAL6_REG OSCCAL
255 #define CAL7_REG OSCCAL
258 #define ADCL0_REG ADCL
259 #define ADCL1_REG ADCL
260 #define ADCL2_REG ADCL
261 #define ADCL3_REG ADCL
262 #define ADCL4_REG ADCL
263 #define ADCL5_REG ADCL
264 #define ADCL6_REG ADCL
265 #define ADCL7_REG ADCL
268 #define EEAR0_REG EEAR
269 #define EEAR1_REG EEAR
270 #define EEAR2_REG EEAR
271 #define EEAR3_REG EEAR
272 #define EEAR4_REG EEAR
273 #define EEAR5_REG EEAR
274 #define EEAR6_REG EEAR
277 #define PORTB0_REG PORTB
278 #define PORTB1_REG PORTB
279 #define PORTB2_REG PORTB
280 #define PORTB3_REG PORTB
281 #define PORTB4_REG PORTB
282 #define PORTB5_REG PORTB
283 #define PORTB6_REG PORTB
284 #define PORTB7_REG PORTB
287 #define ADCH0_REG ADCH
288 #define ADCH1_REG ADCH
289 #define ADCH2_REG ADCH
290 #define ADCH3_REG ADCH
291 #define ADCH4_REG ADCH
292 #define ADCH5_REG ADCH
293 #define ADCH6_REG ADCH
294 #define ADCH7_REG ADCH
297 #define PORTA0_REG PORTA
298 #define PORTA1_REG PORTA
299 #define PORTA2_REG PORTA
300 #define PORTA3_REG PORTA
301 #define PORTA4_REG PORTA
302 #define PORTA5_REG PORTA
303 #define PORTA6_REG PORTA
304 #define PORTA7_REG PORTA
307 #define TCNT00_REG TCNT0
308 #define TCNT01_REG TCNT0
309 #define TCNT02_REG TCNT0
310 #define TCNT03_REG TCNT0
311 #define TCNT04_REG TCNT0
312 #define TCNT05_REG TCNT0
313 #define TCNT06_REG TCNT0
314 #define TCNT07_REG TCNT0
317 #define TCNT1_0_REG TCNT1
318 #define TCNT1_1_REG TCNT1
319 #define TCNT1_2_REG TCNT1
320 #define TCNT1_3_REG TCNT1
321 #define TCNT1_4_REG TCNT1
322 #define TCNT1_5_REG TCNT1
323 #define TCNT1_6_REG TCNT1
324 #define TCNT1_7_REG TCNT1
327 #define TOV0_REG TIFR
328 #define TOV1_REG TIFR
329 #define OCF1B_REG TIFR
330 #define OCF1A_REG TIFR
333 #define PLOCK_REG PLLCSR
334 #define PLLE_REG PLLCSR
335 #define PCKE_REG PLLCSR
338 #define ADPS0_REG ADCSR
339 #define ADPS1_REG ADCSR
340 #define ADPS2_REG ADCSR
341 #define ADIE_REG ADCSR
342 #define ADIF_REG ADCSR
343 #define ADFR_REG ADCSR
344 #define ADSC_REG ADCSR
345 #define ADEN_REG ADCSR
348 #define PINB0_REG PINB
349 #define PINB1_REG PINB
350 #define PINB2_REG PINB
351 #define PINB3_REG PINB
352 #define PINB4_REG PINB
353 #define PINB5_REG PINB
354 #define PINB6_REG PINB
355 #define PINB7_REG PINB
358 #define PINA0_REG PINA
359 #define PINA1_REG PINA
360 #define PINA2_REG PINA
361 #define PINA3_REG PINA
362 #define PINA4_REG PINA
363 #define PINA5_REG PINA
364 #define PINA6_REG PINA
365 #define PINA7_REG PINA
378 #define OCR1B0_REG OCR1B
379 #define OCR1B1_REG OCR1B
380 #define OCR1B2_REG OCR1B
381 #define OCR1B3_REG OCR1B
382 #define OCR1B4_REG OCR1B
383 #define OCR1B5_REG OCR1B
384 #define OCR1B6_REG OCR1B
385 #define OCR1B7_REG OCR1B
388 #define OCR1C0_REG OCR1C
389 #define OCR1C1_REG OCR1C
390 #define OCR1C2_REG OCR1C
391 #define OCR1C3_REG OCR1C
392 #define OCR1C4_REG OCR1C
393 #define OCR1C5_REG OCR1C
394 #define OCR1C6_REG OCR1C
395 #define OCR1C7_REG OCR1C
398 #define OCR1A0_REG OCR1A
399 #define OCR1A1_REG OCR1A
400 #define OCR1A2_REG OCR1A
401 #define OCR1A3_REG OCR1A
402 #define OCR1A4_REG OCR1A
403 #define OCR1A5_REG OCR1A
404 #define OCR1A6_REG OCR1A
405 #define OCR1A7_REG OCR1A
408 #define USIDR0_REG USIDR
409 #define USIDR1_REG USIDR
410 #define USIDR2_REG USIDR
411 #define USIDR3_REG USIDR
412 #define USIDR4_REG USIDR
413 #define USIDR5_REG USIDR
414 #define USIDR6_REG USIDR
415 #define USIDR7_REG USIDR