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34 #include "rte_cpuflags.h"
51 #define AT_PLATFORM 15
60 typedef uint32_t cpuid_registers_t[4];
63 * Struct to hold a processor feature entry
65 struct feature_entry {
66 uint32_t leaf; /**< cpuid leaf */
67 uint32_t subleaf; /**< cpuid subleaf */
68 uint32_t reg; /**< cpuid register */
69 uint32_t bit; /**< cpuid register bit */
70 #define CPU_FLAG_NAME_MAX_LEN 64
71 char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
74 #define FEAT_DEF(name, leaf, subleaf, reg, bit) \
75 [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
78 #define PLATFORM_STR "v7l"
79 typedef Elf32_auxv_t _Elfx_auxv_t;
81 const struct feature_entry rte_cpu_feature_table[] = {
82 FEAT_DEF(SWP, 0x00000001, 0, REG_HWCAP, 0)
83 FEAT_DEF(HALF, 0x00000001, 0, REG_HWCAP, 1)
84 FEAT_DEF(THUMB, 0x00000001, 0, REG_HWCAP, 2)
85 FEAT_DEF(A26BIT, 0x00000001, 0, REG_HWCAP, 3)
86 FEAT_DEF(FAST_MULT, 0x00000001, 0, REG_HWCAP, 4)
87 FEAT_DEF(FPA, 0x00000001, 0, REG_HWCAP, 5)
88 FEAT_DEF(VFP, 0x00000001, 0, REG_HWCAP, 6)
89 FEAT_DEF(EDSP, 0x00000001, 0, REG_HWCAP, 7)
90 FEAT_DEF(JAVA, 0x00000001, 0, REG_HWCAP, 8)
91 FEAT_DEF(IWMMXT, 0x00000001, 0, REG_HWCAP, 9)
92 FEAT_DEF(CRUNCH, 0x00000001, 0, REG_HWCAP, 10)
93 FEAT_DEF(THUMBEE, 0x00000001, 0, REG_HWCAP, 11)
94 FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 12)
95 FEAT_DEF(VFPv3, 0x00000001, 0, REG_HWCAP, 13)
96 FEAT_DEF(VFPv3D16, 0x00000001, 0, REG_HWCAP, 14)
97 FEAT_DEF(TLS, 0x00000001, 0, REG_HWCAP, 15)
98 FEAT_DEF(VFPv4, 0x00000001, 0, REG_HWCAP, 16)
99 FEAT_DEF(IDIVA, 0x00000001, 0, REG_HWCAP, 17)
100 FEAT_DEF(IDIVT, 0x00000001, 0, REG_HWCAP, 18)
101 FEAT_DEF(VFPD32, 0x00000001, 0, REG_HWCAP, 19)
102 FEAT_DEF(LPAE, 0x00000001, 0, REG_HWCAP, 20)
103 FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 21)
104 FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP2, 0)
105 FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP2, 1)
106 FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2)
107 FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3)
108 FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4)
109 FEAT_DEF(V7L, 0x00000001, 0, REG_PLATFORM, 0)
112 #elif defined RTE_ARCH_ARM64
113 #define PLATFORM_STR "aarch64"
114 typedef Elf64_auxv_t _Elfx_auxv_t;
116 const struct feature_entry rte_cpu_feature_table[] = {
117 FEAT_DEF(FP, 0x00000001, 0, REG_HWCAP, 0)
118 FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 1)
119 FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 2)
120 FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP, 3)
121 FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP, 4)
122 FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP, 5)
123 FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP, 6)
124 FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP, 7)
125 FEAT_DEF(AARCH64, 0x00000001, 0, REG_PLATFORM, 1)
127 #endif /* RTE_ARCH */
130 * Read AUXV software register and get cpu features for ARM
133 rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
134 __attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
139 auxv_fd = open("/proc/self/auxv", O_RDONLY);
141 while (read(auxv_fd, &auxv, sizeof(auxv)) == sizeof(auxv)) {
142 if (auxv.a_type == AT_HWCAP) {
143 out[REG_HWCAP] = auxv.a_un.a_val;
144 } else if (auxv.a_type == AT_HWCAP2) {
145 out[REG_HWCAP2] = auxv.a_un.a_val;
146 } else if (auxv.a_type == AT_PLATFORM) {
147 if (!strcmp((const char *)auxv.a_un.a_val, PLATFORM_STR))
148 out[REG_PLATFORM] = 0x0001;
154 * Checks if a particular flag is available on current machine.
157 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
159 const struct feature_entry *feat;
160 cpuid_registers_t regs = {0};
162 if (feature >= RTE_CPUFLAG_NUMFLAGS)
163 /* Flag does not match anything in the feature tables */
166 feat = &rte_cpu_feature_table[feature];
169 /* This entry in the table wasn't filled out! */
172 /* get the cpuid leaf containing the desired feature */
173 rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
175 /* check if the feature is enabled */
176 return (regs[feat->reg] >> feat->bit) & 1;
180 rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
182 if (feature >= RTE_CPUFLAG_NUMFLAGS)
184 return rte_cpu_feature_table[feature].name;