4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright(c) 2014 6WIND S.A.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #include <rte_lcore.h>
46 #include <rte_version.h>
47 #include <rte_devargs.h>
48 #include <rte_memcpy.h>
50 #include "eal_internal_cfg.h"
51 #include "eal_options.h"
52 #include "eal_filesystem.h"
54 #define BITS_PER_HEX 4
58 "b:" /* pci-blacklist */
63 "m:" /* memory size */
64 "n:" /* memory channels */
65 "r:" /* memory ranks */
67 "w:" /* pci-whitelist */
71 eal_long_options[] = {
72 {OPT_BASE_VIRTADDR, 1, NULL, OPT_BASE_VIRTADDR_NUM },
73 {OPT_CREATE_UIO_DEV, 1, NULL, OPT_CREATE_UIO_DEV_NUM },
74 {OPT_FILE_PREFIX, 1, NULL, OPT_FILE_PREFIX_NUM },
75 {OPT_HELP, 0, NULL, OPT_HELP_NUM },
76 {OPT_HUGE_DIR, 1, NULL, OPT_HUGE_DIR_NUM },
77 {OPT_LCORES, 1, NULL, OPT_LCORES_NUM },
78 {OPT_LOG_LEVEL, 1, NULL, OPT_LOG_LEVEL_NUM },
79 {OPT_MASTER_LCORE, 1, NULL, OPT_MASTER_LCORE_NUM },
80 {OPT_NO_HPET, 0, NULL, OPT_NO_HPET_NUM },
81 {OPT_NO_HUGE, 0, NULL, OPT_NO_HUGE_NUM },
82 {OPT_NO_PCI, 0, NULL, OPT_NO_PCI_NUM },
83 {OPT_NO_SHCONF, 0, NULL, OPT_NO_SHCONF_NUM },
84 {OPT_PCI_BLACKLIST, 1, NULL, OPT_PCI_BLACKLIST_NUM },
85 {OPT_PCI_WHITELIST, 1, NULL, OPT_PCI_WHITELIST_NUM },
86 {OPT_PROC_TYPE, 1, NULL, OPT_PROC_TYPE_NUM },
87 {OPT_SOCKET_MEM, 1, NULL, OPT_SOCKET_MEM_NUM },
88 {OPT_SYSLOG, 1, NULL, OPT_SYSLOG_NUM },
89 {OPT_VDEV, 1, NULL, OPT_VDEV_NUM },
90 {OPT_VFIO_INTR, 1, NULL, OPT_VFIO_INTR_NUM },
91 {OPT_VMWARE_TSC_MAP, 0, NULL, OPT_VMWARE_TSC_MAP_NUM },
92 {OPT_XEN_DOM0, 0, NULL, OPT_XEN_DOM0_NUM },
96 static int lcores_parsed;
97 static int master_lcore_parsed;
98 static int mem_parsed;
101 eal_reset_internal_config(struct internal_config *internal_cfg)
105 internal_cfg->memory = 0;
106 internal_cfg->force_nrank = 0;
107 internal_cfg->force_nchannel = 0;
108 internal_cfg->hugefile_prefix = HUGEFILE_PREFIX_DEFAULT;
109 internal_cfg->hugepage_dir = NULL;
110 internal_cfg->force_sockets = 0;
111 /* zero out the NUMA config */
112 for (i = 0; i < RTE_MAX_NUMA_NODES; i++)
113 internal_cfg->socket_mem[i] = 0;
114 /* zero out hugedir descriptors */
115 for (i = 0; i < MAX_HUGEPAGE_SIZES; i++)
116 internal_cfg->hugepage_info[i].lock_descriptor = -1;
117 internal_cfg->base_virtaddr = 0;
119 internal_cfg->syslog_facility = LOG_DAEMON;
120 /* default value from build option */
121 internal_cfg->log_level = RTE_LOG_LEVEL;
123 internal_cfg->xen_dom0_support = 0;
125 /* if set to NONE, interrupt mode is determined automatically */
126 internal_cfg->vfio_intr_mode = RTE_INTR_MODE_NONE;
128 #ifdef RTE_LIBEAL_USE_HPET
129 internal_cfg->no_hpet = 0;
131 internal_cfg->no_hpet = 1;
133 internal_cfg->vmware_tsc_map = 0;
137 * Parse the coremask given as argument (hexadecimal string) and fill
138 * the global configuration (core role and core count) with the parsed
141 static int xdigit2val(unsigned char c)
155 eal_parse_coremask(const char *coremask)
157 struct rte_config *cfg = rte_eal_get_configuration();
163 if (coremask == NULL)
165 /* Remove all blank characters ahead and after .
166 * Remove 0x/0X if exists.
168 while (isblank(*coremask))
170 if (coremask[0] == '0' && ((coremask[1] == 'x')
171 || (coremask[1] == 'X')))
173 i = strnlen(coremask, PATH_MAX);
174 while ((i > 0) && isblank(coremask[i - 1]))
179 for (i = i - 1; i >= 0 && idx < RTE_MAX_LCORE; i--) {
181 if (isxdigit(c) == 0) {
182 /* invalid characters */
186 for (j = 0; j < BITS_PER_HEX && idx < RTE_MAX_LCORE; j++, idx++)
188 if ((1 << j) & val) {
189 if (!lcore_config[idx].detected) {
190 RTE_LOG(ERR, EAL, "lcore %u "
191 "unavailable\n", idx);
194 cfg->lcore_role[idx] = ROLE_RTE;
195 lcore_config[idx].core_index = count;
198 cfg->lcore_role[idx] = ROLE_OFF;
199 lcore_config[idx].core_index = -1;
204 if (coremask[i] != '0')
206 for (; idx < RTE_MAX_LCORE; idx++) {
207 cfg->lcore_role[idx] = ROLE_OFF;
208 lcore_config[idx].core_index = -1;
212 /* Update the count of enabled logical cores of the EAL configuration */
213 cfg->lcore_count = count;
219 eal_parse_corelist(const char *corelist)
221 struct rte_config *cfg = rte_eal_get_configuration();
227 if (corelist == NULL)
230 /* Remove all blank characters ahead and after */
231 while (isblank(*corelist))
233 i = strnlen(corelist, sysconf(_SC_ARG_MAX));
234 while ((i > 0) && isblank(corelist[i - 1]))
238 for (idx = 0; idx < RTE_MAX_LCORE; idx++) {
239 cfg->lcore_role[idx] = ROLE_OFF;
240 lcore_config[idx].core_index = -1;
243 /* Get list of cores */
246 while (isblank(*corelist))
248 if (*corelist == '\0')
251 idx = strtoul(corelist, &end, 10);
252 if (errno || end == NULL)
254 while (isblank(*end))
258 } else if ((*end == ',') || (*end == '\0')) {
260 if (min == RTE_MAX_LCORE)
262 for (idx = min; idx <= max; idx++) {
263 if (cfg->lcore_role[idx] != ROLE_RTE) {
264 cfg->lcore_role[idx] = ROLE_RTE;
265 lcore_config[idx].core_index = count;
273 } while (*end != '\0');
278 /* Update the count of enabled logical cores of the EAL configuration */
279 cfg->lcore_count = count;
285 /* Changes the lcore id of the master thread */
287 eal_parse_master_lcore(const char *arg)
290 struct rte_config *cfg = rte_eal_get_configuration();
293 cfg->master_lcore = (uint32_t) strtol(arg, &parsing_end, 0);
294 if (errno || parsing_end[0] != 0)
296 if (cfg->master_lcore >= RTE_MAX_LCORE)
298 master_lcore_parsed = 1;
303 * Parse elem, the elem could be single number/range or '(' ')' group
304 * 1) A single number elem, it's just a simple digit. e.g. 9
305 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
306 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
307 * Within group elem, '-' used for a range separator;
308 * ',' used for a single number.
311 eal_parse_set(const char *input, uint16_t set[], unsigned num)
314 const char *str = input;
318 memset(set, 0, num * sizeof(uint16_t));
320 while (isblank(*str))
323 /* only digit or left bracket is qualify for start point */
324 if ((!isdigit(*str) && *str != '(') || *str == '\0')
327 /* process single number or single range of number */
330 idx = strtoul(str, &end, 10);
331 if (errno || end == NULL || idx >= num)
334 while (isblank(*end))
340 /* process single <number>-<number> */
342 while (isblank(*end))
348 idx = strtoul(end, &end, 10);
349 if (errno || end == NULL || idx >= num)
352 while (isblank(*end))
354 if (*end != ',' && *end != '\0')
358 if (*end != ',' && *end != '\0' &&
362 for (idx = RTE_MIN(min, max);
363 idx <= RTE_MAX(min, max); idx++)
370 /* process set within bracket */
372 while (isblank(*str))
380 /* go ahead to the first digit */
381 while (isblank(*str))
386 /* get the digit value */
388 idx = strtoul(str, &end, 10);
389 if (errno || end == NULL || idx >= num)
392 /* go ahead to separator '-',',' and ')' */
393 while (isblank(*end))
396 if (min == RTE_MAX_LCORE)
398 else /* avoid continuous '-' */
400 } else if ((*end == ',') || (*end == ')')) {
402 if (min == RTE_MAX_LCORE)
404 for (idx = RTE_MIN(min, max);
405 idx <= RTE_MAX(min, max); idx++)
413 } while (*end != '\0' && *end != ')');
418 /* convert from set array to cpuset bitmap */
420 convert_to_cpuset(rte_cpuset_t *cpusetp,
421 uint16_t *set, unsigned num)
427 for (idx = 0; idx < num; idx++) {
431 if (!lcore_config[idx].detected) {
432 RTE_LOG(ERR, EAL, "core %u "
433 "unavailable\n", idx);
437 CPU_SET(idx, cpusetp);
444 * The format pattern: --lcores='<lcores[@cpus]>[<,lcores[@cpus]>...]'
445 * lcores, cpus could be a single digit/range or a group.
446 * '(' and ')' are necessary if it's a group.
447 * If not supply '@cpus', the value of cpus uses the same as lcores.
448 * e.g. '1,2@(5-7),(3-5)@(0,2),(0,6),7-8' means start 9 EAL thread as below
449 * lcore 0 runs on cpuset 0x41 (cpu 0,6)
450 * lcore 1 runs on cpuset 0x2 (cpu 1)
451 * lcore 2 runs on cpuset 0xe0 (cpu 5,6,7)
452 * lcore 3,4,5 runs on cpuset 0x5 (cpu 0,2)
453 * lcore 6 runs on cpuset 0x41 (cpu 0,6)
454 * lcore 7 runs on cpuset 0x80 (cpu 7)
455 * lcore 8 runs on cpuset 0x100 (cpu 8)
458 eal_parse_lcores(const char *lcores)
460 struct rte_config *cfg = rte_eal_get_configuration();
461 static uint16_t set[RTE_MAX_LCORE];
465 const char *lcore_start = NULL;
466 const char *end = NULL;
475 /* Remove all blank characters ahead and after */
476 while (isblank(*lcores))
478 i = strnlen(lcores, sysconf(_SC_ARG_MAX));
479 while ((i > 0) && isblank(lcores[i - 1]))
484 /* Reset lcore config */
485 for (idx = 0; idx < RTE_MAX_LCORE; idx++) {
486 cfg->lcore_role[idx] = ROLE_OFF;
487 lcore_config[idx].core_index = -1;
488 CPU_ZERO(&lcore_config[idx].cpuset);
491 /* Get list of cores */
493 while (isblank(*lcores))
498 /* record lcore_set start point */
499 lcore_start = lcores;
501 /* go across a complete bracket */
502 if (*lcore_start == '(') {
503 lcores += strcspn(lcores, ")");
504 if (*lcores++ == '\0')
508 /* scan the separator '@', ','(next) or '\0'(finish) */
509 lcores += strcspn(lcores, "@,");
511 if (*lcores == '@') {
512 /* explicit assign cpu_set */
513 offset = eal_parse_set(lcores + 1, set, RTE_DIM(set));
517 /* prepare cpu_set and update the end cursor */
518 if (0 > convert_to_cpuset(&cpuset,
521 end = lcores + 1 + offset;
522 } else { /* ',' or '\0' */
523 /* haven't given cpu_set, current loop done */
526 /* go back to check <number>-<number> */
527 offset = strcspn(lcore_start, "(-");
528 if (offset < (end - lcore_start) &&
529 *(lcore_start + offset) != '(')
533 if (*end != ',' && *end != '\0')
536 /* parse lcore_set from start point */
537 if (0 > eal_parse_set(lcore_start, set, RTE_DIM(set)))
540 /* without '@', by default using lcore_set as cpu_set */
541 if (*lcores != '@' &&
542 0 > convert_to_cpuset(&cpuset, set, RTE_DIM(set)))
545 /* start to update lcore_set */
546 for (idx = 0; idx < RTE_MAX_LCORE; idx++) {
550 if (cfg->lcore_role[idx] != ROLE_RTE) {
551 lcore_config[idx].core_index = count;
552 cfg->lcore_role[idx] = ROLE_RTE;
558 CPU_SET(idx, &cpuset);
560 rte_memcpy(&lcore_config[idx].cpuset, &cpuset,
561 sizeof(rte_cpuset_t));
565 } while (*end != '\0');
570 cfg->lcore_count = count;
580 eal_parse_syslog(const char *facility, struct internal_config *conf)
587 { "auth", LOG_AUTH },
588 { "cron", LOG_CRON },
589 { "daemon", LOG_DAEMON },
591 { "kern", LOG_KERN },
593 { "mail", LOG_MAIL },
594 { "news", LOG_NEWS },
595 { "syslog", LOG_SYSLOG },
596 { "user", LOG_USER },
597 { "uucp", LOG_UUCP },
598 { "local0", LOG_LOCAL0 },
599 { "local1", LOG_LOCAL1 },
600 { "local2", LOG_LOCAL2 },
601 { "local3", LOG_LOCAL3 },
602 { "local4", LOG_LOCAL4 },
603 { "local5", LOG_LOCAL5 },
604 { "local6", LOG_LOCAL6 },
605 { "local7", LOG_LOCAL7 },
609 for (i = 0; map[i].name; i++) {
610 if (!strcmp(facility, map[i].name)) {
611 conf->syslog_facility = map[i].value;
619 eal_parse_log_level(const char *level, uint32_t *log_level)
625 tmp = strtoul(level, &end, 0);
627 /* check for errors */
628 if ((errno != 0) || (level[0] == '\0') ||
629 end == NULL || (*end != '\0'))
632 /* log_level is a uint32_t */
633 if (tmp >= UINT32_MAX)
640 static enum rte_proc_type_t
641 eal_parse_proc_type(const char *arg)
643 if (strncasecmp(arg, "primary", sizeof("primary")) == 0)
644 return RTE_PROC_PRIMARY;
645 if (strncasecmp(arg, "secondary", sizeof("secondary")) == 0)
646 return RTE_PROC_SECONDARY;
647 if (strncasecmp(arg, "auto", sizeof("auto")) == 0)
648 return RTE_PROC_AUTO;
650 return RTE_PROC_INVALID;
654 eal_parse_common_option(int opt, const char *optarg,
655 struct internal_config *conf)
660 if (rte_eal_devargs_add(RTE_DEVTYPE_BLACKLISTED_PCI,
667 if (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI,
674 if (eal_parse_coremask(optarg) < 0) {
675 RTE_LOG(ERR, EAL, "invalid coremask\n");
681 if (eal_parse_corelist(optarg) < 0) {
682 RTE_LOG(ERR, EAL, "invalid core list\n");
688 conf->memory = atoi(optarg);
689 conf->memory *= 1024ULL;
690 conf->memory *= 1024ULL;
693 /* force number of channels */
695 conf->force_nchannel = atoi(optarg);
696 if (conf->force_nchannel == 0 ||
697 conf->force_nchannel > 4) {
698 RTE_LOG(ERR, EAL, "invalid channel number\n");
702 /* force number of ranks */
704 conf->force_nrank = atoi(optarg);
705 if (conf->force_nrank == 0 ||
706 conf->force_nrank > 16) {
707 RTE_LOG(ERR, EAL, "invalid rank number\n");
712 /* since message is explicitly requested by user, we
713 * write message at highest log level so it can always
715 * even if info or warning messages are disabled */
716 RTE_LOG(CRIT, EAL, "RTE Version: '%s'\n", rte_version());
720 case OPT_NO_HUGE_NUM:
721 conf->no_hugetlbfs = 1;
728 case OPT_NO_HPET_NUM:
732 case OPT_VMWARE_TSC_MAP_NUM:
733 conf->vmware_tsc_map = 1;
736 case OPT_NO_SHCONF_NUM:
740 case OPT_PROC_TYPE_NUM:
741 conf->process_type = eal_parse_proc_type(optarg);
744 case OPT_MASTER_LCORE_NUM:
745 if (eal_parse_master_lcore(optarg) < 0) {
746 RTE_LOG(ERR, EAL, "invalid parameter for --"
747 OPT_MASTER_LCORE "\n");
753 if (rte_eal_devargs_add(RTE_DEVTYPE_VIRTUAL,
760 if (eal_parse_syslog(optarg, conf) < 0) {
761 RTE_LOG(ERR, EAL, "invalid parameters for --"
767 case OPT_LOG_LEVEL_NUM: {
770 if (eal_parse_log_level(optarg, &log) < 0) {
772 "invalid parameters for --"
776 conf->log_level = log;
780 if (eal_parse_lcores(optarg) < 0) {
781 RTE_LOG(ERR, EAL, "invalid parameter for --"
787 /* don't know what to do, leave this to caller */
797 eal_adjust_config(struct internal_config *internal_cfg)
800 struct rte_config *cfg = rte_eal_get_configuration();
802 if (internal_config.process_type == RTE_PROC_AUTO)
803 internal_config.process_type = eal_proc_type_detect();
805 /* default master lcore is the first one */
806 if (!master_lcore_parsed)
807 cfg->master_lcore = rte_get_next_lcore(-1, 0, 0);
809 /* if no memory amounts were requested, this will result in 0 and
810 * will be overridden later, right after eal_hugepage_info_init() */
811 for (i = 0; i < RTE_MAX_NUMA_NODES; i++)
812 internal_cfg->memory += internal_cfg->socket_mem[i];
818 eal_check_common_options(struct internal_config *internal_cfg)
820 struct rte_config *cfg = rte_eal_get_configuration();
822 if (!lcores_parsed) {
823 RTE_LOG(ERR, EAL, "CPU cores must be enabled with options "
824 "-c, -l or --lcores\n");
827 if (cfg->lcore_role[cfg->master_lcore] != ROLE_RTE) {
828 RTE_LOG(ERR, EAL, "Master lcore is not enabled for DPDK\n");
832 if (internal_cfg->process_type == RTE_PROC_INVALID) {
833 RTE_LOG(ERR, EAL, "Invalid process type specified\n");
836 if (internal_cfg->process_type == RTE_PROC_PRIMARY &&
837 internal_cfg->force_nchannel == 0) {
838 RTE_LOG(ERR, EAL, "Number of memory channels (-n) not "
842 if (index(internal_cfg->hugefile_prefix, '%') != NULL) {
843 RTE_LOG(ERR, EAL, "Invalid char, '%%', in --"OPT_FILE_PREFIX" "
847 if (mem_parsed && internal_cfg->force_sockets == 1) {
848 RTE_LOG(ERR, EAL, "Options -m and --"OPT_SOCKET_MEM" cannot "
849 "be specified at the same time\n");
852 if (internal_cfg->no_hugetlbfs &&
853 (mem_parsed || internal_cfg->force_sockets == 1)) {
854 RTE_LOG(ERR, EAL, "Options -m or --"OPT_SOCKET_MEM" cannot "
855 "be specified together with --"OPT_NO_HUGE"\n");
859 if (rte_eal_devargs_type_count(RTE_DEVTYPE_WHITELISTED_PCI) != 0 &&
860 rte_eal_devargs_type_count(RTE_DEVTYPE_BLACKLISTED_PCI) != 0) {
861 RTE_LOG(ERR, EAL, "Options blacklist (-b) and whitelist (-w) "
862 "cannot be used at the same time\n");
870 eal_common_usage(void)
872 printf("-c COREMASK|-l CORELIST -n CHANNELS [options]\n\n"
873 "EAL common options:\n"
874 " -c COREMASK Hexadecimal bitmask of cores to run on\n"
875 " -l CORELIST List of cores to run on\n"
876 " The argument format is <c1>[-c2][,c3[-c4],...]\n"
877 " where c1, c2, etc are core indexes between 0 and %d\n"
878 " --"OPT_LCORES" COREMAP Map lcore set to physical cpu set\n"
879 " The argument format is\n"
880 " '<lcores[@cpus]>[<,lcores[@cpus]>...]'\n"
881 " lcores and cpus list are grouped by '(' and ')'\n"
882 " Within the group, '-' is used for range separator,\n"
883 " ',' is used for single number separator.\n"
884 " '( )' can be omitted for single element group,\n"
885 " '@' can be omitted if cpus and lcores have the same value\n"
886 " --"OPT_MASTER_LCORE" ID Core ID that is used as master\n"
887 " -n CHANNELS Number of memory channels\n"
888 " -m MB Memory to allocate (see also --"OPT_SOCKET_MEM")\n"
889 " -r RANKS Force number of memory ranks (don't detect)\n"
890 " -b, --"OPT_PCI_BLACKLIST" Add a PCI device in black list.\n"
891 " Prevent EAL from using this PCI device. The argument\n"
892 " format is <domain:bus:devid.func>.\n"
893 " -w, --"OPT_PCI_WHITELIST" Add a PCI device in white list.\n"
894 " Only use the specified PCI devices. The argument format\n"
895 " is <[domain:]bus:devid.func>. This option can be present\n"
896 " several times (once per device).\n"
897 " [NOTE: PCI whitelist cannot be used with -b option]\n"
898 " --"OPT_VDEV" Add a virtual device.\n"
899 " The argument format is <driver><id>[,key=val,...]\n"
900 " (ex: --vdev=eth_pcap0,iface=eth2).\n"
901 " --"OPT_VMWARE_TSC_MAP" Use VMware TSC map instead of native RDTSC\n"
902 " --"OPT_PROC_TYPE" Type of this process (primary|secondary|auto)\n"
903 " --"OPT_SYSLOG" Set syslog facility\n"
904 " --"OPT_LOG_LEVEL" Set default log level\n"
905 " -v Display version information on startup\n"
906 " -h, --help This help\n"
907 "\nEAL options for DEBUG use only:\n"
908 " --"OPT_NO_HUGE" Use malloc instead of hugetlbfs\n"
909 " --"OPT_NO_PCI" Disable PCI\n"
910 " --"OPT_NO_HPET" Disable HPET\n"
911 " --"OPT_NO_SHCONF" No shared config (mmap'd files)\n"
912 "\n", RTE_MAX_LCORE);