4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution
19 * in the file called LICENSE.GPL.
21 * Contact Information:
25 #include <linux/device.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/uio_driver.h>
30 #include <linux/msi.h>
31 #include <linux/version.h>
33 #ifdef CONFIG_XEN_DOM0
36 #include <rte_pci_dev_features.h>
39 * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
40 * but none of them in kernel 2.6.35.
42 #ifndef PCI_MSIX_ENTRY_SIZE
43 #define PCI_MSIX_ENTRY_SIZE 16
44 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
45 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
46 #define PCI_MSIX_ENTRY_DATA 8
47 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12
48 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
52 #define PCI_SYS_FILE_BUF_SIZE 10
53 #define PCI_DEV_CAP_REG 0xA4
54 #define PCI_DEV_CTRL_REG 0xA8
55 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
56 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
57 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
60 #define IGBUIO_NUM_MSI_VECTORS 1
63 * A structure describing the private information for a uio device.
65 struct rte_uio_pci_dev {
68 spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
69 enum rte_intr_mode mode;
71 msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
74 static char *intr_mode = NULL;
75 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
77 static inline struct rte_uio_pci_dev *
78 igbuio_get_uio_pci_dev(struct uio_info *info)
80 return container_of(info, struct rte_uio_pci_dev, info);
84 int local_pci_num_vf(struct pci_dev *dev)
86 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
95 } *iov = (struct iov*)dev->sriov;
100 return iov->nr_virtfn;
102 return pci_num_vf(dev);
107 show_max_vfs(struct device *dev, struct device_attribute *attr,
110 return snprintf(buf, 10, "%u\n", local_pci_num_vf(
111 container_of(dev, struct pci_dev, dev)));
115 store_max_vfs(struct device *dev, struct device_attribute *attr,
116 const char *buf, size_t count)
119 unsigned long max_vfs;
120 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
122 if (0 != strict_strtoul(buf, 0, &max_vfs))
126 pci_disable_sriov(pdev);
127 else if (0 == local_pci_num_vf(pdev))
128 err = pci_enable_sriov(pdev, max_vfs);
129 else /* do nothing if change max_vfs number */
132 return err ? err : count;
135 #ifdef RTE_PCI_CONFIG
137 show_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)
139 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
142 pci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);
143 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
144 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n", "invalid");
147 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
148 PCI_DEV_CTRL_REG, &val);
150 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%s\n",
151 (val & PCI_DEV_CTRL_EXT_TAG_MASK) ? "on" : "off");
155 store_extended_tag(struct device *dev,
156 struct device_attribute *attr,
160 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
161 uint32_t val = 0, enable;
163 if (strncmp(buf, "on", 2) == 0)
165 else if (strncmp(buf, "off", 3) == 0)
170 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
171 PCI_DEV_CAP_REG, &val);
172 if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
176 pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
177 PCI_DEV_CTRL_REG, &val);
179 val |= PCI_DEV_CTRL_EXT_TAG_MASK;
181 val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
182 pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
183 PCI_DEV_CTRL_REG, val);
189 show_max_read_request_size(struct device *dev,
190 struct device_attribute *attr,
193 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
194 int val = pcie_get_readrq(pci_dev);
196 return snprintf(buf, PCI_SYS_FILE_BUF_SIZE, "%d\n", val);
200 store_max_read_request_size(struct device *dev,
201 struct device_attribute *attr,
205 struct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);
206 unsigned long size = 0;
209 if (strict_strtoul(buf, 0, &size) != 0)
212 ret = pcie_set_readrq(pci_dev, (int)size);
220 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
221 #ifdef RTE_PCI_CONFIG
222 static DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag, \
224 static DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR, \
225 show_max_read_request_size, store_max_read_request_size);
228 static struct attribute *dev_attrs[] = {
229 &dev_attr_max_vfs.attr,
230 #ifdef RTE_PCI_CONFIG
231 &dev_attr_extended_tag.attr,
232 &dev_attr_max_read_request_size.attr,
237 static const struct attribute_group dev_attr_grp = {
242 pci_lock(struct pci_dev * pdev)
244 /* Some function names changes between 3.2.0 and 3.3.0... */
245 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
246 pci_block_user_cfg_access(pdev);
249 return pci_cfg_access_trylock(pdev);
254 pci_unlock(struct pci_dev * pdev)
256 /* Some function names changes between 3.2.0 and 3.3.0... */
257 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
258 pci_unblock_user_cfg_access(pdev);
260 pci_cfg_access_unlock(pdev);
265 * It masks the msix on/off of generating MSI-X messages.
268 igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
270 uint32_t mask_bits = desc->masked;
271 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
272 PCI_MSIX_ENTRY_VECTOR_CTRL;
275 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
277 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
279 if (mask_bits != desc->masked) {
280 writel(mask_bits, desc->mask_base + offset);
281 readl(desc->mask_base);
282 desc->masked = mask_bits;
289 * This function sets/clears the masks for generating LSC interrupts.
292 * The pointer to struct uio_info.
294 * The on/off flag of masking LSC.
296 * -On success, zero value.
297 * -On failure, a negative value.
300 igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
302 struct pci_dev *pdev = udev->pdev;
304 if (udev->mode == RTE_INTR_MODE_MSIX) {
305 struct msi_desc *desc;
307 list_for_each_entry(desc, &pdev->msi_list, list) {
308 igbuio_msix_mask_irq(desc, state);
310 } else if (udev->mode == RTE_INTR_MODE_LEGACY) {
314 pci_read_config_dword(pdev, PCI_COMMAND, &status);
317 new = old & (~PCI_COMMAND_INTX_DISABLE);
319 new = old | PCI_COMMAND_INTX_DISABLE;
322 pci_write_config_word(pdev, PCI_COMMAND, new);
329 * This is the irqcontrol callback to be registered to uio_info.
330 * It can be used to disable/enable interrupt from user space processes.
333 * pointer to uio_info.
335 * state value. 1 to enable interrupt, 0 to disable interrupt.
339 * - On failure, a negative value.
342 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
345 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
346 struct pci_dev *pdev = udev->pdev;
348 spin_lock_irqsave(&udev->lock, flags);
349 if (!pci_lock(pdev)) {
350 spin_unlock_irqrestore(&udev->lock, flags);
354 igbuio_set_interrupt_mask(udev, irq_state);
357 spin_unlock_irqrestore(&udev->lock, flags);
363 * This is interrupt handler which will check if the interrupt is for the right device.
364 * If yes, disable it here and will be enable later.
367 igbuio_pci_irqhandler(int irq, struct uio_info *info)
369 irqreturn_t ret = IRQ_NONE;
371 struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
372 struct pci_dev *pdev = udev->pdev;
373 uint32_t cmd_status_dword;
376 spin_lock_irqsave(&udev->lock, flags);
377 /* block userspace PCI config reads/writes */
381 /* for legacy mode, interrupt maybe shared */
382 if (udev->mode == RTE_INTR_MODE_LEGACY) {
383 pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
384 status = cmd_status_dword >> 16;
385 /* interrupt is not ours, goes to out */
386 if (!(status & PCI_STATUS_INTERRUPT))
390 igbuio_set_interrupt_mask(udev, 0);
393 /* unblock userspace PCI config reads/writes */
396 spin_unlock_irqrestore(&udev->lock, flags);
397 printk(KERN_INFO "irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
402 #ifdef CONFIG_XEN_DOM0
404 igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
407 idx = (int)vma->vm_pgoff;
408 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
409 vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
411 return remap_pfn_range(vma,
413 info->mem[idx].addr >> PAGE_SHIFT,
414 vma->vm_end - vma->vm_start,
419 * This is uio device mmap method which will use igbuio mmap for Xen
423 igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
427 if (vma->vm_pgoff >= MAX_UIO_MAPS)
429 if(info->mem[vma->vm_pgoff].size == 0)
432 idx = (int)vma->vm_pgoff;
433 switch (info->mem[idx].memtype) {
435 return igbuio_dom0_mmap_phys(info, vma);
436 case UIO_MEM_LOGICAL:
437 case UIO_MEM_VIRTUAL:
444 /* Remap pci resources described by bar #pci_bar in uio resource n. */
446 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
447 int n, int pci_bar, const char *name)
449 unsigned long addr, len;
452 if (sizeof(info->mem) / sizeof (info->mem[0]) <= n)
455 addr = pci_resource_start(dev, pci_bar);
456 len = pci_resource_len(dev, pci_bar);
457 if (addr == 0 || len == 0)
459 internal_addr = ioremap(addr, len);
460 if (internal_addr == NULL)
462 info->mem[n].name = name;
463 info->mem[n].addr = addr;
464 info->mem[n].internal_addr = internal_addr;
465 info->mem[n].size = len;
466 info->mem[n].memtype = UIO_MEM_PHYS;
470 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
472 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
473 int n, int pci_bar, const char *name)
475 unsigned long addr, len;
477 if (sizeof(info->port) / sizeof (info->port[0]) <= n)
480 addr = pci_resource_start(dev, pci_bar);
481 len = pci_resource_len(dev, pci_bar);
482 if (addr == 0 || len == 0)
485 info->port[n].name = name;
486 info->port[n].start = addr;
487 info->port[n].size = len;
488 info->port[n].porttype = UIO_PORT_X86;
493 /* Unmap previously ioremap'd resources */
495 igbuio_pci_release_iomem(struct uio_info *info)
498 for (i = 0; i < MAX_UIO_MAPS; i++) {
499 if (info->mem[i].internal_addr)
500 iounmap(info->mem[i].internal_addr);
505 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
507 int i, iom, iop, ret;
509 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
521 for (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {
522 if (pci_resource_len(dev, i) != 0 &&
523 pci_resource_start(dev, i) != 0) {
524 flags = pci_resource_flags(dev, i);
525 if (flags & IORESOURCE_MEM) {
526 if ((ret = igbuio_pci_setup_iomem(dev, info,
527 iom, i, bar_names[i])) != 0)
530 } else if (flags & IORESOURCE_IO) {
531 if ((ret = igbuio_pci_setup_ioport(dev, info,
532 iop, i, bar_names[i])) != 0)
539 return ((iom != 0) ? ret : ENOENT);
542 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
547 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
549 struct rte_uio_pci_dev *udev;
551 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
556 * enable device: ask low-level code to enable I/O and
559 if (pci_enable_device(dev)) {
560 printk(KERN_ERR "Cannot enable PCI device\n");
565 * reserve device's PCI memory regions for use by this
568 if (pci_request_regions(dev, "igb_uio")) {
569 printk(KERN_ERR "Cannot request regions\n");
573 /* enable bus mastering on the device */
576 /* remap IO memory */
577 if (igbuio_setup_bars(dev, &udev->info))
578 goto fail_release_iomem;
580 /* set 64-bit DMA mask */
581 if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
582 printk(KERN_ERR "Cannot set DMA mask\n");
583 goto fail_release_iomem;
584 } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
585 printk(KERN_ERR "Cannot set consistent DMA mask\n");
586 goto fail_release_iomem;
590 udev->info.name = "Intel IGB UIO";
591 udev->info.version = "0.1";
592 udev->info.handler = igbuio_pci_irqhandler;
593 udev->info.irqcontrol = igbuio_pci_irqcontrol;
594 #ifdef CONFIG_XEN_DOM0
595 /* check if the driver run on Xen Dom0 */
596 if (xen_initial_domain())
597 udev->info.mmap = igbuio_dom0_pci_mmap;
599 udev->info.priv = udev;
601 udev->mode = RTE_INTR_MODE_LEGACY;
602 spin_lock_init(&udev->lock);
604 /* check if it need to try msix first */
605 if (igbuio_intr_mode_preferred == RTE_INTR_MODE_MSIX) {
608 for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
609 udev->msix_entries[vector].entry = vector;
611 if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
612 udev->mode = RTE_INTR_MODE_MSIX;
615 pci_disable_msix(udev->pdev);
616 printk(KERN_INFO "fail to enable pci msix, or not enough msix entries\n");
619 switch (udev->mode) {
620 case RTE_INTR_MODE_MSIX:
621 udev->info.irq_flags = 0;
622 udev->info.irq = udev->msix_entries[0].vector;
624 case RTE_INTR_MODE_MSI:
626 case RTE_INTR_MODE_LEGACY:
627 udev->info.irq_flags = IRQF_SHARED;
628 udev->info.irq = dev->irq;
634 pci_set_drvdata(dev, udev);
635 igbuio_pci_irqcontrol(&udev->info, 0);
637 if (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))
638 goto fail_release_iomem;
640 /* register uio driver */
641 if (uio_register_device(&dev->dev, &udev->info))
642 goto fail_release_iomem;
644 printk(KERN_INFO "uio device registered with irq %lx\n", udev->info.irq);
649 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
650 igbuio_pci_release_iomem(&udev->info);
651 if (udev->mode == RTE_INTR_MODE_MSIX)
652 pci_disable_msix(udev->pdev);
653 pci_release_regions(dev);
655 pci_disable_device(dev);
663 igbuio_pci_remove(struct pci_dev *dev)
665 struct uio_info *info = pci_get_drvdata(dev);
667 if (info->priv == NULL) {
668 printk(KERN_DEBUG "Not igbuio device\n");
672 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
673 uio_unregister_device(info);
674 igbuio_pci_release_iomem(info);
675 if (((struct rte_uio_pci_dev *)info->priv)->mode ==
677 pci_disable_msix(dev);
678 pci_release_regions(dev);
679 pci_disable_device(dev);
680 pci_set_drvdata(dev, NULL);
685 igbuio_config_intr_mode(char *intr_str)
688 printk(KERN_INFO "Use MSIX interrupt by default\n");
692 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
693 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
694 printk(KERN_INFO "Use MSIX interrupt\n");
695 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
696 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
697 printk(KERN_INFO "Use legacy interrupt\n");
699 printk(KERN_INFO "Error: bad parameter - %s\n", intr_str);
706 static struct pci_driver igbuio_pci_driver = {
709 .probe = igbuio_pci_probe,
710 .remove = igbuio_pci_remove,
714 igbuio_pci_init_module(void)
718 ret = igbuio_config_intr_mode(intr_mode);
722 return pci_register_driver(&igbuio_pci_driver);
726 igbuio_pci_exit_module(void)
728 pci_unregister_driver(&igbuio_pci_driver);
731 module_init(igbuio_pci_init_module);
732 module_exit(igbuio_pci_exit_module);
734 module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
735 MODULE_PARM_DESC(intr_mode,
736 "igb_uio interrupt mode (default=msix):\n"
737 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
738 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
741 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
742 MODULE_LICENSE("GPL");
743 MODULE_AUTHOR("Intel Corporation");