1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
42 #include "e1000_api.h"
44 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
45 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
46 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
47 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
49 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
50 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
52 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
54 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw);
55 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
56 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
58 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
59 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
60 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
61 u32 offset, u16 *data);
62 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
63 u32 offset, u16 data);
64 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
66 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
68 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
70 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
71 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
72 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
73 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
74 u32 offset, u16 data);
75 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
77 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
78 u16 *speed, u16 *duplex);
79 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
80 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
81 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
82 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
83 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
84 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
85 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
86 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
87 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
88 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
89 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
90 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
91 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
92 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
94 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
96 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
97 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
99 static const u16 e1000_82580_rxpbs_table[] =
100 { 36, 72, 144, 1, 2, 4, 8, 16,
102 #define E1000_82580_RXPBS_TABLE_SIZE \
103 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
107 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
108 * @hw: pointer to the HW structure
110 * Called to determine if the I2C pins are being used for I2C or as an
111 * external MDIO interface since the two options are mutually exclusive.
113 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
116 bool ext_mdio = false;
118 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
120 switch (hw->mac.type) {
123 reg = E1000_READ_REG(hw, E1000_MDIC);
124 ext_mdio = !!(reg & E1000_MDIC_DEST);
128 reg = E1000_READ_REG(hw, E1000_MDICNFG);
129 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
138 * e1000_init_phy_params_82575 - Init PHY func ptrs.
139 * @hw: pointer to the HW structure
141 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
143 struct e1000_phy_info *phy = &hw->phy;
144 s32 ret_val = E1000_SUCCESS;
147 DEBUGFUNC("e1000_init_phy_params_82575");
149 if (hw->phy.media_type != e1000_media_type_copper) {
150 phy->type = e1000_phy_none;
154 phy->ops.power_up = e1000_power_up_phy_copper;
155 phy->ops.power_down = e1000_power_down_phy_copper_82575;
157 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
158 phy->reset_delay_us = 100;
160 phy->ops.acquire = e1000_acquire_phy_82575;
161 phy->ops.check_reset_block = e1000_check_reset_block_generic;
162 phy->ops.commit = e1000_phy_sw_reset_generic;
163 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
164 phy->ops.release = e1000_release_phy_82575;
166 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
168 if (e1000_sgmii_active_82575(hw)) {
169 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
170 ctrl_ext |= E1000_CTRL_I2C_ENA;
172 phy->ops.reset = e1000_phy_hw_reset_generic;
173 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
176 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
177 e1000_reset_mdicnfg_82580(hw);
179 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
180 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
181 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
182 } else if (hw->mac.type >= e1000_82580) {
183 phy->ops.read_reg = e1000_read_phy_reg_82580;
184 phy->ops.write_reg = e1000_write_phy_reg_82580;
186 phy->ops.read_reg = e1000_read_phy_reg_igp;
187 phy->ops.write_reg = e1000_write_phy_reg_igp;
190 /* Set phy->phy_addr and phy->id. */
191 ret_val = e1000_get_phy_id_82575(hw);
193 /* Verify phy id and set remaining function pointers */
195 case I347AT4_E_PHY_ID:
196 case M88E1112_E_PHY_ID:
197 case M88E1340M_E_PHY_ID:
198 case M88E1111_I_PHY_ID:
199 phy->type = e1000_phy_m88;
200 phy->ops.check_polarity = e1000_check_polarity_m88;
201 phy->ops.get_info = e1000_get_phy_info_m88;
202 if (phy->id == I347AT4_E_PHY_ID ||
203 phy->id == M88E1112_E_PHY_ID ||
204 phy->id == M88E1340M_E_PHY_ID)
205 phy->ops.get_cable_length =
206 e1000_get_cable_length_m88_gen2;
208 phy->ops.get_cable_length = e1000_get_cable_length_m88;
209 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
211 case IGP03E1000_E_PHY_ID:
212 case IGP04E1000_E_PHY_ID:
213 phy->type = e1000_phy_igp_3;
214 phy->ops.check_polarity = e1000_check_polarity_igp;
215 phy->ops.get_info = e1000_get_phy_info_igp;
216 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
217 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
218 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
219 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
221 case I82580_I_PHY_ID:
223 phy->type = e1000_phy_82580;
224 phy->ops.check_polarity = e1000_check_polarity_82577;
225 phy->ops.force_speed_duplex =
226 e1000_phy_force_speed_duplex_82577;
227 phy->ops.get_cable_length = e1000_get_cable_length_82577;
228 phy->ops.get_info = e1000_get_phy_info_82577;
229 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
230 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
233 ret_val = -E1000_ERR_PHY;
242 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
243 * @hw: pointer to the HW structure
245 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
247 struct e1000_nvm_info *nvm = &hw->nvm;
248 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
251 DEBUGFUNC("e1000_init_nvm_params_82575");
253 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
254 E1000_EECD_SIZE_EX_SHIFT);
256 * Added to a constant, "size" becomes the left-shift value
257 * for setting word_size.
259 size += NVM_WORD_SIZE_BASE_SHIFT;
261 nvm->word_size = 1 << size;
262 nvm->opcode_bits = 8;
264 switch (nvm->override) {
265 case e1000_nvm_override_spi_large:
267 nvm->address_bits = 16;
269 case e1000_nvm_override_spi_small:
271 nvm->address_bits = 8;
274 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
275 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
280 nvm->type = e1000_nvm_eeprom_spi;
282 if (nvm->word_size == (1 << 15))
283 nvm->page_size = 128;
285 /* Function Pointers */
286 nvm->ops.acquire = e1000_acquire_nvm_82575;
287 nvm->ops.release = e1000_release_nvm_82575;
288 if (nvm->word_size < (1 << 15))
289 nvm->ops.read = e1000_read_nvm_eerd;
291 nvm->ops.read = e1000_read_nvm_spi;
293 nvm->ops.write = e1000_write_nvm_spi;
294 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
295 nvm->ops.update = e1000_update_nvm_checksum_generic;
296 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
298 /* override generic family function pointers for specific descendants */
299 switch (hw->mac.type) {
301 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
302 nvm->ops.update = e1000_update_nvm_checksum_82580;
305 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
306 nvm->ops.update = e1000_update_nvm_checksum_i350;
312 return E1000_SUCCESS;
316 * e1000_init_mac_params_82575 - Init MAC func ptrs.
317 * @hw: pointer to the HW structure
319 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
321 struct e1000_mac_info *mac = &hw->mac;
322 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
325 DEBUGFUNC("e1000_init_mac_params_82575");
329 * The 82575 uses bits 22:23 for link mode. The mode can be changed
330 * based on the EEPROM. We cannot rely upon device ID. There
331 * is no distinguishable difference between fiber and internal
332 * SerDes mode on the 82575. There can be an external PHY attached
333 * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
335 hw->phy.media_type = e1000_media_type_copper;
336 dev_spec->sgmii_active = FALSE;
338 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
339 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
340 case E1000_CTRL_EXT_LINK_MODE_SGMII:
341 dev_spec->sgmii_active = TRUE;
343 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
344 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
345 hw->phy.media_type = e1000_media_type_internal_serdes;
351 /* Set mta register count */
352 mac->mta_reg_count = 128;
353 /* Set uta register count */
354 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
355 /* Set rar entry count */
356 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
357 if (mac->type == e1000_82576)
358 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
359 if (mac->type == e1000_82580)
360 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
361 if (mac->type == e1000_i350) {
362 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
363 /* Enable EEE default settings for i350 */
364 dev_spec->eee_disable = false;
367 /* Set if part includes ASF firmware */
368 mac->asf_firmware_present = true;
370 mac->has_fwsm = true;
371 /* ARC supported; valid only if manageability features are enabled. */
372 mac->arc_subsystem_valid =
373 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
375 /* Function pointers */
377 /* bus type/speed/width */
378 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
380 if (mac->type >= e1000_82580)
381 mac->ops.reset_hw = e1000_reset_hw_82580;
383 mac->ops.reset_hw = e1000_reset_hw_82575;
384 /* hw initialization */
385 mac->ops.init_hw = e1000_init_hw_82575;
387 mac->ops.setup_link = e1000_setup_link_generic;
388 /* physical interface link setup */
389 mac->ops.setup_physical_interface =
390 (hw->phy.media_type == e1000_media_type_copper)
391 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
392 /* physical interface shutdown */
393 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
394 /* physical interface power up */
395 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
397 mac->ops.check_for_link = e1000_check_for_link_82575;
398 /* receive address register setting */
399 mac->ops.rar_set = e1000_rar_set_generic;
400 /* read mac address */
401 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
402 /* configure collision distance */
403 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
404 /* multicast address update */
405 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
407 mac->ops.write_vfta = e1000_write_vfta_generic;
409 mac->ops.clear_vfta = e1000_clear_vfta_generic;
411 mac->ops.id_led_init = e1000_id_led_init_generic;
413 mac->ops.blink_led = e1000_blink_led_generic;
415 mac->ops.setup_led = e1000_setup_led_generic;
417 mac->ops.cleanup_led = e1000_cleanup_led_generic;
418 /* turn on/off LED */
419 mac->ops.led_on = e1000_led_on_generic;
420 mac->ops.led_off = e1000_led_off_generic;
421 /* clear hardware counters */
422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
424 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
426 /* set lan id for port to determine which phy lock to use */
427 hw->mac.ops.set_lan_id(hw);
429 return E1000_SUCCESS;
433 * e1000_init_function_pointers_82575 - Init func ptrs.
434 * @hw: pointer to the HW structure
436 * Called to initialize all function pointers and parameters.
438 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
440 DEBUGFUNC("e1000_init_function_pointers_82575");
442 hw->mac.ops.init_params = e1000_init_mac_params_82575;
443 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
444 hw->phy.ops.init_params = e1000_init_phy_params_82575;
445 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
449 * e1000_acquire_phy_82575 - Acquire rights to access PHY
450 * @hw: pointer to the HW structure
452 * Acquire access rights to the correct PHY.
454 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
456 u16 mask = E1000_SWFW_PHY0_SM;
458 DEBUGFUNC("e1000_acquire_phy_82575");
460 if (hw->bus.func == E1000_FUNC_1)
461 mask = E1000_SWFW_PHY1_SM;
462 else if (hw->bus.func == E1000_FUNC_2)
463 mask = E1000_SWFW_PHY2_SM;
464 else if (hw->bus.func == E1000_FUNC_3)
465 mask = E1000_SWFW_PHY3_SM;
467 return e1000_acquire_swfw_sync_82575(hw, mask);
471 * e1000_release_phy_82575 - Release rights to access PHY
472 * @hw: pointer to the HW structure
474 * A wrapper to release access rights to the correct PHY.
476 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
478 u16 mask = E1000_SWFW_PHY0_SM;
480 DEBUGFUNC("e1000_release_phy_82575");
482 if (hw->bus.func == E1000_FUNC_1)
483 mask = E1000_SWFW_PHY1_SM;
484 else if (hw->bus.func == E1000_FUNC_2)
485 mask = E1000_SWFW_PHY2_SM;
486 else if (hw->bus.func == E1000_FUNC_3)
487 mask = E1000_SWFW_PHY3_SM;
489 e1000_release_swfw_sync_82575(hw, mask);
493 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
494 * @hw: pointer to the HW structure
495 * @offset: register offset to be read
496 * @data: pointer to the read data
498 * Reads the PHY register at offset using the serial gigabit media independent
499 * interface and stores the retrieved information in data.
501 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
504 s32 ret_val = -E1000_ERR_PARAM;
506 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
508 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
509 DEBUGOUT1("PHY Address %u is out of range\n", offset);
513 ret_val = hw->phy.ops.acquire(hw);
517 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
519 hw->phy.ops.release(hw);
526 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
527 * @hw: pointer to the HW structure
528 * @offset: register offset to write to
529 * @data: data to write at register offset
531 * Writes the data to PHY register at the offset using the serial gigabit
532 * media independent interface.
534 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
537 s32 ret_val = -E1000_ERR_PARAM;
539 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
541 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
542 DEBUGOUT1("PHY Address %d is out of range\n", offset);
546 ret_val = hw->phy.ops.acquire(hw);
550 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
552 hw->phy.ops.release(hw);
559 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
560 * @hw: pointer to the HW structure
562 * Retrieves the PHY address and ID for both PHY's which do and do not use
565 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
567 struct e1000_phy_info *phy = &hw->phy;
568 s32 ret_val = E1000_SUCCESS;
573 DEBUGFUNC("e1000_get_phy_id_82575");
576 * For SGMII PHYs, we try the list of possible addresses until
577 * we find one that works. For non-SGMII PHYs
578 * (e.g. integrated copper PHYs), an address of 1 should
579 * work. The result of this function should mean phy->phy_addr
580 * and phy->id are set correctly.
582 if (!e1000_sgmii_active_82575(hw)) {
584 ret_val = e1000_get_phy_id(hw);
588 if (e1000_sgmii_uses_mdio_82575(hw)) {
589 switch (hw->mac.type) {
592 mdic = E1000_READ_REG(hw, E1000_MDIC);
593 mdic &= E1000_MDIC_PHY_MASK;
594 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
598 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
599 mdic &= E1000_MDICNFG_PHY_MASK;
600 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
603 ret_val = -E1000_ERR_PHY;
607 ret_val = e1000_get_phy_id(hw);
611 /* Power on sgmii phy if it is disabled */
612 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
613 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
614 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
615 E1000_WRITE_FLUSH(hw);
619 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
620 * Therefore, we need to test 1-7
622 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
623 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
624 if (ret_val == E1000_SUCCESS) {
625 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
628 * At the time of this writing, The M88 part is
629 * the only supported SGMII PHY product.
631 if (phy_id == M88_VENDOR)
634 DEBUGOUT1("PHY address %u was unreadable\n",
639 /* A valid PHY type couldn't be found. */
640 if (phy->addr == 8) {
642 ret_val = -E1000_ERR_PHY;
644 ret_val = e1000_get_phy_id(hw);
647 /* restore previous sfp cage power state */
648 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
655 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
656 * @hw: pointer to the HW structure
658 * Resets the PHY using the serial gigabit media independent interface.
660 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
662 s32 ret_val = E1000_SUCCESS;
664 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
667 * This isn't a true "hard" reset, but is the only reset
668 * available to us at this time.
671 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
673 if (!(hw->phy.ops.write_reg))
677 * SFP documentation requires the following to configure the SPF module
678 * to work on SGMII. No further documentation is given.
680 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
684 ret_val = hw->phy.ops.commit(hw);
691 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
692 * @hw: pointer to the HW structure
693 * @active: true to enable LPLU, false to disable
695 * Sets the LPLU D0 state according to the active flag. When
696 * activating LPLU this function also disables smart speed
697 * and vice versa. LPLU will not be activated unless the
698 * device autonegotiation advertisement meets standards of
699 * either 10 or 10/100 or 10/100/1000 at all duplexes.
700 * This is a function pointer entry point only called by
701 * PHY setup routines.
703 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
705 struct e1000_phy_info *phy = &hw->phy;
706 s32 ret_val = E1000_SUCCESS;
709 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
711 if (!(hw->phy.ops.read_reg))
714 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
719 data |= IGP02E1000_PM_D0_LPLU;
720 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
725 /* When LPLU is enabled, we should disable SmartSpeed */
726 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
728 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
729 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
734 data &= ~IGP02E1000_PM_D0_LPLU;
735 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
738 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
739 * during Dx states where the power conservation is most
740 * important. During driver activity we should enable
741 * SmartSpeed, so performance is maintained.
743 if (phy->smart_speed == e1000_smart_speed_on) {
744 ret_val = phy->ops.read_reg(hw,
745 IGP01E1000_PHY_PORT_CONFIG,
750 data |= IGP01E1000_PSCFR_SMART_SPEED;
751 ret_val = phy->ops.write_reg(hw,
752 IGP01E1000_PHY_PORT_CONFIG,
756 } else if (phy->smart_speed == e1000_smart_speed_off) {
757 ret_val = phy->ops.read_reg(hw,
758 IGP01E1000_PHY_PORT_CONFIG,
763 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
764 ret_val = phy->ops.write_reg(hw,
765 IGP01E1000_PHY_PORT_CONFIG,
777 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
778 * @hw: pointer to the HW structure
779 * @active: true to enable LPLU, false to disable
781 * Sets the LPLU D0 state according to the active flag. When
782 * activating LPLU this function also disables smart speed
783 * and vice versa. LPLU will not be activated unless the
784 * device autonegotiation advertisement meets standards of
785 * either 10 or 10/100 or 10/100/1000 at all duplexes.
786 * This is a function pointer entry point only called by
787 * PHY setup routines.
789 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
791 struct e1000_phy_info *phy = &hw->phy;
792 s32 ret_val = E1000_SUCCESS;
795 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
797 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
800 data |= E1000_82580_PM_D0_LPLU;
802 /* When LPLU is enabled, we should disable SmartSpeed */
803 data &= ~E1000_82580_PM_SPD;
805 data &= ~E1000_82580_PM_D0_LPLU;
808 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
809 * during Dx states where the power conservation is most
810 * important. During driver activity we should enable
811 * SmartSpeed, so performance is maintained.
813 if (phy->smart_speed == e1000_smart_speed_on)
814 data |= E1000_82580_PM_SPD;
815 else if (phy->smart_speed == e1000_smart_speed_off)
816 data &= ~E1000_82580_PM_SPD;
819 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
824 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
825 * @hw: pointer to the HW structure
826 * @active: boolean used to enable/disable lplu
828 * Success returns 0, Failure returns 1
830 * The low power link up (lplu) state is set to the power management level D3
831 * and SmartSpeed is disabled when active is true, else clear lplu for D3
832 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
833 * is used during Dx states where the power conservation is most important.
834 * During driver activity, SmartSpeed should be enabled so performance is
837 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
839 struct e1000_phy_info *phy = &hw->phy;
840 s32 ret_val = E1000_SUCCESS;
843 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
845 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
848 data &= ~E1000_82580_PM_D3_LPLU;
850 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
851 * during Dx states where the power conservation is most
852 * important. During driver activity we should enable
853 * SmartSpeed, so performance is maintained.
855 if (phy->smart_speed == e1000_smart_speed_on)
856 data |= E1000_82580_PM_SPD;
857 else if (phy->smart_speed == e1000_smart_speed_off)
858 data &= ~E1000_82580_PM_SPD;
859 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
860 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
861 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
862 data |= E1000_82580_PM_D3_LPLU;
863 /* When LPLU is enabled, we should disable SmartSpeed */
864 data &= ~E1000_82580_PM_SPD;
867 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
872 * e1000_acquire_nvm_82575 - Request for access to EEPROM
873 * @hw: pointer to the HW structure
875 * Acquire the necessary semaphores for exclusive access to the EEPROM.
876 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
877 * Return successful if access grant bit set, else clear the request for
878 * EEPROM access and return -E1000_ERR_NVM (-1).
880 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
884 DEBUGFUNC("e1000_acquire_nvm_82575");
886 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
891 * Check if there is some access
892 * error this access may hook on
894 if (hw->mac.type == e1000_i350) {
895 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
896 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
897 E1000_EECD_TIMEOUT)) {
898 /* Clear all access error flags */
899 E1000_WRITE_REG(hw, E1000_EECD, eecd |
900 E1000_EECD_ERROR_CLR);
901 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
904 if (hw->mac.type == e1000_82580) {
905 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
906 if (eecd & E1000_EECD_BLOCKED) {
907 /* Clear access error flag */
908 E1000_WRITE_REG(hw, E1000_EECD, eecd |
910 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
915 ret_val = e1000_acquire_nvm_generic(hw);
917 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
924 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
925 * @hw: pointer to the HW structure
927 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
928 * then release the semaphores acquired.
930 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
932 DEBUGFUNC("e1000_release_nvm_82575");
934 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
938 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
939 * @hw: pointer to the HW structure
940 * @mask: specifies which semaphore to acquire
942 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
943 * will also specify which port we're acquiring the lock for.
945 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
949 u32 fwmask = mask << 16;
950 s32 ret_val = E1000_SUCCESS;
951 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
953 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
955 while (i < timeout) {
956 if (e1000_get_hw_semaphore_generic(hw)) {
957 ret_val = -E1000_ERR_SWFW_SYNC;
961 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
962 if (!(swfw_sync & (fwmask | swmask)))
966 * Firmware currently using resource (fwmask)
967 * or other software thread using resource (swmask)
969 e1000_put_hw_semaphore_generic(hw);
975 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
976 ret_val = -E1000_ERR_SWFW_SYNC;
981 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
983 e1000_put_hw_semaphore_generic(hw);
990 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
991 * @hw: pointer to the HW structure
992 * @mask: specifies which semaphore to acquire
994 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
995 * will also specify which port we're releasing the lock for.
997 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1001 DEBUGFUNC("e1000_release_swfw_sync_82575");
1003 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1006 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1008 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1010 e1000_put_hw_semaphore_generic(hw);
1014 * e1000_get_cfg_done_82575 - Read config done bit
1015 * @hw: pointer to the HW structure
1017 * Read the management control register for the config done bit for
1018 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1019 * to read the config done bit, so an error is *ONLY* logged and returns
1020 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1021 * would not be able to be reset or change link.
1023 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1025 s32 timeout = PHY_CFG_TIMEOUT;
1026 s32 ret_val = E1000_SUCCESS;
1027 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1029 DEBUGFUNC("e1000_get_cfg_done_82575");
1031 if (hw->bus.func == E1000_FUNC_1)
1032 mask = E1000_NVM_CFG_DONE_PORT_1;
1033 else if (hw->bus.func == E1000_FUNC_2)
1034 mask = E1000_NVM_CFG_DONE_PORT_2;
1035 else if (hw->bus.func == E1000_FUNC_3)
1036 mask = E1000_NVM_CFG_DONE_PORT_3;
1038 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1044 DEBUGOUT("MNG configuration cycle has not completed.\n");
1046 /* If EEPROM is not marked present, init the PHY manually */
1047 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1048 (hw->phy.type == e1000_phy_igp_3))
1049 e1000_phy_init_script_igp3(hw);
1055 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1056 * @hw: pointer to the HW structure
1057 * @speed: stores the current speed
1058 * @duplex: stores the current duplex
1060 * This is a wrapper function, if using the serial gigabit media independent
1061 * interface, use PCS to retrieve the link speed and duplex information.
1062 * Otherwise, use the generic function to get the link speed and duplex info.
1064 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1069 DEBUGFUNC("e1000_get_link_up_info_82575");
1071 if (hw->phy.media_type != e1000_media_type_copper)
1072 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1075 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1082 * e1000_check_for_link_82575 - Check for link
1083 * @hw: pointer to the HW structure
1085 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1086 * use the generic interface for determining link.
1088 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1093 DEBUGFUNC("e1000_check_for_link_82575");
1095 if (hw->phy.media_type != e1000_media_type_copper) {
1096 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1099 * Use this flag to determine if link needs to be checked or
1100 * not. If we have link clear the flag so that we do not
1101 * continue to check for link.
1103 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1105 ret_val = e1000_check_for_copper_link_generic(hw);
1112 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1113 * @hw: pointer to the HW structure
1115 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1119 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1121 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1122 !e1000_sgmii_active_82575(hw))
1125 /* Enable PCS to turn on link */
1126 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1127 reg |= E1000_PCS_CFG_PCS_EN;
1128 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1130 /* Power up the laser */
1131 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1132 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1133 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1135 /* flush the write to verify completion */
1136 E1000_WRITE_FLUSH(hw);
1141 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1142 * @hw: pointer to the HW structure
1143 * @speed: stores the current speed
1144 * @duplex: stores the current duplex
1146 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1147 * duplex, then store the values in the pointers provided.
1149 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1150 u16 *speed, u16 *duplex)
1152 struct e1000_mac_info *mac = &hw->mac;
1155 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1157 /* Set up defaults for the return values of this function */
1158 mac->serdes_has_link = FALSE;
1163 * Read the PCS Status register for link state. For non-copper mode,
1164 * the status register is not accurate. The PCS status register is
1167 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1170 * The link up bit determines when link is up on autoneg. The sync ok
1171 * gets set once both sides sync up and agree upon link. Stable link
1172 * can be determined by checking for both link up and link sync ok
1174 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1175 mac->serdes_has_link = TRUE;
1177 /* Detect and store PCS speed */
1178 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1179 *speed = SPEED_1000;
1180 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1185 /* Detect and store PCS duplex */
1186 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1187 *duplex = FULL_DUPLEX;
1189 *duplex = HALF_DUPLEX;
1192 return E1000_SUCCESS;
1196 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1197 * @hw: pointer to the HW structure
1199 * In the case of serdes shut down sfp and PCS on driver unload
1200 * when management pass thru is not enabled.
1202 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1206 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1208 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1209 !e1000_sgmii_active_82575(hw))
1212 if (!e1000_enable_mng_pass_thru(hw)) {
1213 /* Disable PCS to turn off link */
1214 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1215 reg &= ~E1000_PCS_CFG_PCS_EN;
1216 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1218 /* shutdown the laser */
1219 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1220 reg |= E1000_CTRL_EXT_SDP3_DATA;
1221 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1223 /* flush the write to verify completion */
1224 E1000_WRITE_FLUSH(hw);
1232 * e1000_reset_hw_82575 - Reset hardware
1233 * @hw: pointer to the HW structure
1235 * This resets the hardware into a known state.
1237 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1242 DEBUGFUNC("e1000_reset_hw_82575");
1245 * Prevent the PCI-E bus from sticking if there is no TLP connection
1246 * on the last TLP read/write transaction when MAC is reset.
1248 ret_val = e1000_disable_pcie_master_generic(hw);
1250 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1252 /* set the completion timeout for interface */
1253 ret_val = e1000_set_pcie_completion_timeout(hw);
1255 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1257 DEBUGOUT("Masking off all interrupts\n");
1258 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1260 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1261 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1262 E1000_WRITE_FLUSH(hw);
1266 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1268 DEBUGOUT("Issuing a global reset to MAC\n");
1269 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1271 ret_val = e1000_get_auto_rd_done_generic(hw);
1274 * When auto config read does not complete, do not
1275 * return with an error. This can happen in situations
1276 * where there is no eeprom and prevents getting link.
1278 DEBUGOUT("Auto Read Done did not complete\n");
1281 /* If EEPROM is not present, run manual init scripts */
1282 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1283 e1000_reset_init_script_82575(hw);
1285 /* Clear any pending interrupt events. */
1286 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1287 E1000_READ_REG(hw, E1000_ICR);
1289 /* Install any alternate MAC address into RAR0 */
1290 ret_val = e1000_check_alt_mac_addr_generic(hw);
1296 * e1000_init_hw_82575 - Initialize hardware
1297 * @hw: pointer to the HW structure
1299 * This inits the hardware readying it for operation.
1301 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1303 struct e1000_mac_info *mac = &hw->mac;
1305 u16 i, rar_count = mac->rar_entry_count;
1307 DEBUGFUNC("e1000_init_hw_82575");
1309 /* Initialize identification LED */
1310 ret_val = mac->ops.id_led_init(hw);
1312 DEBUGOUT("Error initializing identification LED\n");
1313 /* This is not fatal and we should not stop init due to this */
1316 /* Disabling VLAN filtering */
1317 DEBUGOUT("Initializing the IEEE VLAN\n");
1318 mac->ops.clear_vfta(hw);
1320 /* Setup the receive address */
1321 e1000_init_rx_addrs_generic(hw, rar_count);
1323 /* Zero out the Multicast HASH table */
1324 DEBUGOUT("Zeroing the MTA\n");
1325 for (i = 0; i < mac->mta_reg_count; i++)
1326 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1328 /* Zero out the Unicast HASH table */
1329 DEBUGOUT("Zeroing the UTA\n");
1330 for (i = 0; i < mac->uta_reg_count; i++)
1331 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1333 /* Setup link and flow control */
1334 ret_val = mac->ops.setup_link(hw);
1337 * Clear all of the statistics registers (clear on read). It is
1338 * important that we do this after we have tried to establish link
1339 * because the symbol error count will increment wildly if there
1342 e1000_clear_hw_cntrs_82575(hw);
1348 * e1000_setup_copper_link_82575 - Configure copper link settings
1349 * @hw: pointer to the HW structure
1351 * Configures the link for auto-neg or forced speed and duplex. Then we check
1352 * for link, once link is established calls to configure collision distance
1353 * and flow control are called.
1355 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1360 DEBUGFUNC("e1000_setup_copper_link_82575");
1362 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1363 ctrl |= E1000_CTRL_SLU;
1364 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1365 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1367 ret_val = e1000_setup_serdes_link_82575(hw);
1371 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1372 /* allow time for SFP cage time to power up phy */
1375 ret_val = hw->phy.ops.reset(hw);
1377 DEBUGOUT("Error resetting the PHY.\n");
1381 switch (hw->phy.type) {
1383 if (hw->phy.id == I347AT4_E_PHY_ID ||
1384 hw->phy.id == M88E1112_E_PHY_ID ||
1385 hw->phy.id == M88E1340M_E_PHY_ID)
1386 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1388 ret_val = e1000_copper_link_setup_m88(hw);
1390 case e1000_phy_igp_3:
1391 ret_val = e1000_copper_link_setup_igp(hw);
1393 case e1000_phy_82580:
1394 ret_val = e1000_copper_link_setup_82577(hw);
1397 ret_val = -E1000_ERR_PHY;
1404 ret_val = e1000_setup_copper_link_generic(hw);
1410 * e1000_setup_serdes_link_82575 - Setup link for serdes
1411 * @hw: pointer to the HW structure
1413 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1414 * used on copper connections where the serialized gigabit media independent
1415 * interface (sgmii), or serdes fiber is being used. Configures the link
1416 * for auto-negotiation or forces speed/duplex.
1418 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1420 u32 ctrl_ext, ctrl_reg, reg;
1423 DEBUGFUNC("e1000_setup_serdes_link_82575");
1425 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1426 !e1000_sgmii_active_82575(hw))
1427 return E1000_SUCCESS;
1430 * On the 82575, SerDes loopback mode persists until it is
1431 * explicitly turned off or a power cycle is performed. A read to
1432 * the register does not indicate its status. Therefore, we ensure
1433 * loopback mode is disabled during initialization.
1435 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1437 /* power on the sfp cage if present */
1438 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1439 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1440 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1442 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1443 ctrl_reg |= E1000_CTRL_SLU;
1445 /* set both sw defined pins on 82575/82576*/
1446 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1447 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1449 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1451 /* default pcs_autoneg to the same setting as mac autoneg */
1452 pcs_autoneg = hw->mac.autoneg;
1454 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1455 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1456 /* sgmii mode lets the phy handle forcing speed/duplex */
1458 /* autoneg time out should be disabled for SGMII mode */
1459 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1461 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1462 /* disable PCS autoneg and support parallel detect only */
1463 pcs_autoneg = false;
1464 /* fall through to default case */
1467 * non-SGMII modes only supports a speed of 1000/Full for the
1468 * link so it is best to just force the MAC and let the pcs
1469 * link either autoneg or be forced to 1000/Full
1471 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1472 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1474 /* set speed of 1000/Full if speed/duplex is forced */
1475 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1479 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1482 * New SerDes mode allows for forcing speed or autonegotiating speed
1483 * at 1gb. Autoneg should be default set by most drivers. This is the
1484 * mode that will be compatible with older link partners and switches.
1485 * However, both are supported by the hardware and some drivers/tools.
1487 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1488 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1491 * We force flow control to prevent the CTRL register values from being
1492 * overwritten by the autonegotiated flow control values
1494 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1497 /* Set PCS register for autoneg */
1498 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1499 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1500 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1502 /* Set PCS register for forced link */
1503 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1504 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1507 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1509 if (!e1000_sgmii_active_82575(hw))
1510 e1000_force_mac_fc_generic(hw);
1512 return E1000_SUCCESS;
1516 * e1000_valid_led_default_82575 - Verify a valid default LED config
1517 * @hw: pointer to the HW structure
1518 * @data: pointer to the NVM (EEPROM)
1520 * Read the EEPROM for the current default LED configuration. If the
1521 * LED configuration is not valid, set to a valid LED configuration.
1523 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1527 DEBUGFUNC("e1000_valid_led_default_82575");
1529 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1531 DEBUGOUT("NVM Read Error\n");
1535 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1536 switch (hw->phy.media_type) {
1537 case e1000_media_type_internal_serdes:
1538 *data = ID_LED_DEFAULT_82575_SERDES;
1540 case e1000_media_type_copper:
1542 *data = ID_LED_DEFAULT;
1551 * e1000_sgmii_active_82575 - Return sgmii state
1552 * @hw: pointer to the HW structure
1554 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1555 * which can be enabled for use in the embedded applications. Simply
1556 * return the current state of the sgmii interface.
1558 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1560 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1561 return dev_spec->sgmii_active;
1565 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1566 * @hw: pointer to the HW structure
1568 * Inits recommended HW defaults after a reset when there is no EEPROM
1569 * detected. This is only for the 82575.
1571 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1573 DEBUGFUNC("e1000_reset_init_script_82575");
1575 if (hw->mac.type == e1000_82575) {
1576 DEBUGOUT("Running reset init script for 82575\n");
1577 /* SerDes configuration via SERDESCTRL */
1578 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1579 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1580 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1581 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1583 /* CCM configuration via CCMCTL register */
1584 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1585 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1587 /* PCIe lanes configuration */
1588 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1589 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1590 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1591 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1593 /* PCIe PLL Configuration */
1594 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1595 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1596 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1599 return E1000_SUCCESS;
1603 * e1000_read_mac_addr_82575 - Read device MAC address
1604 * @hw: pointer to the HW structure
1606 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1608 s32 ret_val = E1000_SUCCESS;
1610 DEBUGFUNC("e1000_read_mac_addr_82575");
1613 * If there's an alternate MAC address place it in RAR0
1614 * so that it will override the Si installed default perm
1617 ret_val = e1000_check_alt_mac_addr_generic(hw);
1621 ret_val = e1000_read_mac_addr_generic(hw);
1628 * e1000_config_collision_dist_82575 - Configure collision distance
1629 * @hw: pointer to the HW structure
1631 * Configures the collision distance to the default value and is used
1632 * during link setup.
1634 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1638 DEBUGFUNC("e1000_config_collision_dist_82575");
1640 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1642 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1643 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1645 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1646 E1000_WRITE_FLUSH(hw);
1650 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1651 * @hw: pointer to the HW structure
1653 * In the case of a PHY power down to save power, or to turn off link during a
1654 * driver unload, or wake on lan is not enabled, remove the link.
1656 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1658 struct e1000_phy_info *phy = &hw->phy;
1660 if (!(phy->ops.check_reset_block))
1663 /* If the management interface is not enabled, then power down */
1664 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1665 e1000_power_down_phy_copper(hw);
1671 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1672 * @hw: pointer to the HW structure
1674 * Clears the hardware counters by reading the counter registers.
1676 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1678 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1680 e1000_clear_hw_cntrs_base_generic(hw);
1682 E1000_READ_REG(hw, E1000_PRC64);
1683 E1000_READ_REG(hw, E1000_PRC127);
1684 E1000_READ_REG(hw, E1000_PRC255);
1685 E1000_READ_REG(hw, E1000_PRC511);
1686 E1000_READ_REG(hw, E1000_PRC1023);
1687 E1000_READ_REG(hw, E1000_PRC1522);
1688 E1000_READ_REG(hw, E1000_PTC64);
1689 E1000_READ_REG(hw, E1000_PTC127);
1690 E1000_READ_REG(hw, E1000_PTC255);
1691 E1000_READ_REG(hw, E1000_PTC511);
1692 E1000_READ_REG(hw, E1000_PTC1023);
1693 E1000_READ_REG(hw, E1000_PTC1522);
1695 E1000_READ_REG(hw, E1000_ALGNERRC);
1696 E1000_READ_REG(hw, E1000_RXERRC);
1697 E1000_READ_REG(hw, E1000_TNCRS);
1698 E1000_READ_REG(hw, E1000_CEXTERR);
1699 E1000_READ_REG(hw, E1000_TSCTC);
1700 E1000_READ_REG(hw, E1000_TSCTFC);
1702 E1000_READ_REG(hw, E1000_MGTPRC);
1703 E1000_READ_REG(hw, E1000_MGTPDC);
1704 E1000_READ_REG(hw, E1000_MGTPTC);
1706 E1000_READ_REG(hw, E1000_IAC);
1707 E1000_READ_REG(hw, E1000_ICRXOC);
1709 E1000_READ_REG(hw, E1000_ICRXPTC);
1710 E1000_READ_REG(hw, E1000_ICRXATC);
1711 E1000_READ_REG(hw, E1000_ICTXPTC);
1712 E1000_READ_REG(hw, E1000_ICTXATC);
1713 E1000_READ_REG(hw, E1000_ICTXQEC);
1714 E1000_READ_REG(hw, E1000_ICTXQMTC);
1715 E1000_READ_REG(hw, E1000_ICRXDMTC);
1717 E1000_READ_REG(hw, E1000_CBTMPC);
1718 E1000_READ_REG(hw, E1000_HTDPMC);
1719 E1000_READ_REG(hw, E1000_CBRMPC);
1720 E1000_READ_REG(hw, E1000_RPTHC);
1721 E1000_READ_REG(hw, E1000_HGPTC);
1722 E1000_READ_REG(hw, E1000_HTCBDPC);
1723 E1000_READ_REG(hw, E1000_HGORCL);
1724 E1000_READ_REG(hw, E1000_HGORCH);
1725 E1000_READ_REG(hw, E1000_HGOTCL);
1726 E1000_READ_REG(hw, E1000_HGOTCH);
1727 E1000_READ_REG(hw, E1000_LENERRS);
1729 /* This register should not be read in copper configurations */
1730 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1731 e1000_sgmii_active_82575(hw))
1732 E1000_READ_REG(hw, E1000_SCVPC);
1736 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
1737 * @hw: pointer to the HW structure
1739 * After rx enable if managability is enabled then there is likely some
1740 * bad data at the start of the fifo and possibly in the DMA fifo. This
1741 * function clears the fifos and flushes any packets that came in as rx was
1744 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1746 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1749 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1750 if (hw->mac.type != e1000_82575 ||
1751 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1754 /* Disable all Rx queues */
1755 for (i = 0; i < 4; i++) {
1756 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1757 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1758 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1760 /* Poll all queues to verify they have shut down */
1761 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1764 for (i = 0; i < 4; i++)
1765 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
1766 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1771 DEBUGOUT("Queue disable timed out after 10ms\n");
1773 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1774 * incoming packets are rejected. Set enable and wait 2ms so that
1775 * any packet that was coming in as RCTL.EN was set is flushed
1777 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1778 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1780 rlpml = E1000_READ_REG(hw, E1000_RLPML);
1781 E1000_WRITE_REG(hw, E1000_RLPML, 0);
1783 rctl = E1000_READ_REG(hw, E1000_RCTL);
1784 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1785 temp_rctl |= E1000_RCTL_LPE;
1787 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1788 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1789 E1000_WRITE_FLUSH(hw);
1792 /* Enable Rx queues that were previously enabled and restore our
1795 for (i = 0; i < 4; i++)
1796 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1797 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1798 E1000_WRITE_FLUSH(hw);
1800 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
1801 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1803 /* Flush receive errors generated by workaround */
1804 E1000_READ_REG(hw, E1000_ROC);
1805 E1000_READ_REG(hw, E1000_RNBC);
1806 E1000_READ_REG(hw, E1000_MPC);
1810 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1811 * @hw: pointer to the HW structure
1813 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1814 * however the hardware default for these parts is 500us to 1ms which is less
1815 * than the 10ms recommended by the pci-e spec. To address this we need to
1816 * increase the value to either 10ms to 200ms for capability version 1 config,
1817 * or 16ms to 55ms for version 2.
1819 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1821 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1822 s32 ret_val = E1000_SUCCESS;
1825 /* only take action if timeout value is defaulted to 0 */
1826 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1830 * if capababilities version is type 1 we can write the
1831 * timeout of 10ms to 200ms through the GCR register
1833 if (!(gcr & E1000_GCR_CAP_VER2)) {
1834 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1839 * for version 2 capabilities we need to write the config space
1840 * directly in order to set the completion timeout value for
1843 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1848 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1850 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1853 /* disable completion timeout resend */
1854 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1856 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1861 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1862 * @hw: pointer to the hardware struct
1863 * @enable: state to enter, either enabled or disabled
1864 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1866 * enables/disables L2 switch anti-spoofing functionality.
1868 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1872 switch (hw->mac.type) {
1874 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1876 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1877 E1000_DTXSWC_VLAN_SPOOF_MASK);
1878 /* The PF can spoof - it has to in order to
1879 * support emulation mode NICs */
1880 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1882 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1883 E1000_DTXSWC_VLAN_SPOOF_MASK);
1885 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1888 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
1890 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1891 E1000_DTXSWC_VLAN_SPOOF_MASK);
1892 /* The PF can spoof - it has to in order to
1893 * support emulation mode NICs
1895 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1897 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1898 E1000_DTXSWC_VLAN_SPOOF_MASK);
1900 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
1907 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
1908 * @hw: pointer to the hardware struct
1909 * @enable: state to enter, either enabled or disabled
1911 * enables/disables L2 switch loopback functionality.
1913 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1917 switch (hw->mac.type) {
1919 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1921 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1923 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1924 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1927 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
1929 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1931 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1932 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
1935 /* Currently no other hardware supports loopback */
1943 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
1944 * @hw: pointer to the hardware struct
1945 * @enable: state to enter, either enabled or disabled
1947 * enables/disables replication of packets across multiple pools.
1949 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1951 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1954 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1956 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1958 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1962 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
1963 * @hw: pointer to the HW structure
1964 * @offset: register offset to be read
1965 * @data: pointer to the read data
1967 * Reads the MDI control register in the PHY at offset and stores the
1968 * information read to data.
1970 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1974 DEBUGFUNC("e1000_read_phy_reg_82580");
1976 ret_val = hw->phy.ops.acquire(hw);
1980 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
1982 hw->phy.ops.release(hw);
1989 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
1990 * @hw: pointer to the HW structure
1991 * @offset: register offset to write to
1992 * @data: data to write to register at offset
1994 * Writes data to MDI control register in the PHY at offset.
1996 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2000 DEBUGFUNC("e1000_write_phy_reg_82580");
2002 ret_val = hw->phy.ops.acquire(hw);
2006 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2008 hw->phy.ops.release(hw);
2015 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2016 * @hw: pointer to the HW structure
2018 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2019 * the values found in the EEPROM. This addresses an issue in which these
2020 * bits are not restored from EEPROM after reset.
2022 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2024 s32 ret_val = E1000_SUCCESS;
2028 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2030 if (hw->mac.type != e1000_82580)
2032 if (!e1000_sgmii_active_82575(hw))
2035 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2036 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2039 DEBUGOUT("NVM Read Error\n");
2043 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2044 if (nvm_data & NVM_WORD24_EXT_MDIO)
2045 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2046 if (nvm_data & NVM_WORD24_COM_MDIO)
2047 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2048 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2054 * e1000_reset_hw_82580 - Reset hardware
2055 * @hw: pointer to the HW structure
2057 * This resets function or entire device (all ports, etc.)
2060 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2062 s32 ret_val = E1000_SUCCESS;
2063 /* BH SW mailbox bit in SW_FW_SYNC */
2064 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2066 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2068 DEBUGFUNC("e1000_reset_hw_82580");
2070 hw->dev_spec._82575.global_device_reset = false;
2072 /* Get current control state. */
2073 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2076 * Prevent the PCI-E bus from sticking if there is no TLP connection
2077 * on the last TLP read/write transaction when MAC is reset.
2079 ret_val = e1000_disable_pcie_master_generic(hw);
2081 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2083 DEBUGOUT("Masking off all interrupts\n");
2084 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2085 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2086 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2087 E1000_WRITE_FLUSH(hw);
2091 /* Determine whether or not a global dev reset is requested */
2092 if (global_device_reset &&
2093 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
2094 global_device_reset = FALSE;
2096 if (global_device_reset &&
2097 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2098 ctrl |= E1000_CTRL_DEV_RST;
2100 ctrl |= E1000_CTRL_RST;
2102 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2104 /* Add delay to insure DEV_RST has time to complete */
2105 if (global_device_reset)
2108 ret_val = e1000_get_auto_rd_done_generic(hw);
2111 * When auto config read does not complete, do not
2112 * return with an error. This can happen in situations
2113 * where there is no eeprom and prevents getting link.
2115 DEBUGOUT("Auto Read Done did not complete\n");
2118 /* If EEPROM is not present, run manual init scripts */
2119 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2120 e1000_reset_init_script_82575(hw);
2122 /* clear global device reset status bit */
2123 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2125 /* Clear any pending interrupt events. */
2126 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2127 E1000_READ_REG(hw, E1000_ICR);
2129 ret_val = e1000_reset_mdicnfg_82580(hw);
2131 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2133 /* Install any alternate MAC address into RAR0 */
2134 ret_val = e1000_check_alt_mac_addr_generic(hw);
2136 /* Release semaphore */
2137 if (global_device_reset)
2138 e1000_release_swfw_sync_82575(hw, swmbsw_mask);
2144 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2145 * @data: data received by reading RXPBS register
2147 * The 82580 uses a table based approach for packet buffer allocation sizes.
2148 * This function converts the retrieved value into the correct table value
2149 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2150 * 0x0 36 72 144 1 2 4 8 16
2151 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2153 u16 e1000_rxpbs_adjust_82580(u32 data)
2157 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2158 ret_val = e1000_82580_rxpbs_table[data];
2164 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2166 * @hw: pointer to the HW structure
2167 * @offset: offset in words of the checksum protected region
2169 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2170 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2172 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2174 s32 ret_val = E1000_SUCCESS;
2178 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2180 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2181 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2183 DEBUGOUT("NVM Read Error\n");
2186 checksum += nvm_data;
2189 if (checksum != (u16) NVM_SUM) {
2190 DEBUGOUT("NVM Checksum Invalid\n");
2191 ret_val = -E1000_ERR_NVM;
2200 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2202 * @hw: pointer to the HW structure
2203 * @offset: offset in words of the checksum protected region
2205 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2206 * up to the checksum. Then calculates the EEPROM checksum and writes the
2207 * value to the EEPROM.
2209 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2215 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2217 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2218 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2220 DEBUGOUT("NVM Read Error while updating checksum.\n");
2223 checksum += nvm_data;
2225 checksum = (u16) NVM_SUM - checksum;
2226 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2229 DEBUGOUT("NVM Write Error while updating checksum.\n");
2236 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2237 * @hw: pointer to the HW structure
2239 * Calculates the EEPROM section checksum by reading/adding each word of
2240 * the EEPROM and then verifies that the sum of the EEPROM is
2243 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2245 s32 ret_val = E1000_SUCCESS;
2246 u16 eeprom_regions_count = 1;
2250 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2252 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2254 DEBUGOUT("NVM Read Error\n");
2258 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2259 /* if chekcsums compatibility bit is set validate checksums
2260 * for all 4 ports. */
2261 eeprom_regions_count = 4;
2264 for (j = 0; j < eeprom_regions_count; j++) {
2265 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2266 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2268 if (ret_val != E1000_SUCCESS)
2277 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2278 * @hw: pointer to the HW structure
2280 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2281 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2282 * checksum and writes the value to the EEPROM.
2284 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2290 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2292 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2294 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2298 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2299 /* set compatibility bit to validate checksums appropriately */
2300 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2301 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2304 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2309 for (j = 0; j < 4; j++) {
2310 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2311 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2321 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2322 * @hw: pointer to the HW structure
2324 * Calculates the EEPROM section checksum by reading/adding each word of
2325 * the EEPROM and then verifies that the sum of the EEPROM is
2328 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2330 s32 ret_val = E1000_SUCCESS;
2334 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2336 for (j = 0; j < 4; j++) {
2337 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2338 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2340 if (ret_val != E1000_SUCCESS)
2349 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2350 * @hw: pointer to the HW structure
2352 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2353 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2354 * checksum and writes the value to the EEPROM.
2356 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2358 s32 ret_val = E1000_SUCCESS;
2362 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2364 for (j = 0; j < 4; j++) {
2365 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2366 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2367 if (ret_val != E1000_SUCCESS)
2376 * e1000_set_eee_i350 - Enable/disable EEE support
2377 * @hw: pointer to the HW structure
2379 * Enable/disable EEE based on setting in dev_spec structure.
2382 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2384 s32 ret_val = E1000_SUCCESS;
2385 u32 ipcnfg, eeer, ctrl_ext;
2387 DEBUGFUNC("e1000_set_eee_i350");
2389 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2390 if ((hw->mac.type != e1000_i350) ||
2391 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2393 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2394 eeer = E1000_READ_REG(hw, E1000_EEER);
2396 /* enable or disable per user setting */
2397 if (!(hw->dev_spec._82575.eee_disable)) {
2398 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2399 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2403 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2404 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2407 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2408 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2409 E1000_READ_REG(hw, E1000_IPCNFG);
2410 E1000_READ_REG(hw, E1000_EEER);