1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
40 * 82580 Gigabit Network Connection
41 * I350 Gigabit Network Connection
44 #include "e1000_api.h"
45 #include "e1000_i210.h"
47 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
49 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
55 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
69 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
71 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
73 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79 u32 offset, u16 data);
80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
88 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
118 STATIC const u16 e1000_82580_rxpbs_table[] = {
119 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
120 #define E1000_82580_RXPBS_TABLE_SIZE \
121 (sizeof(e1000_82580_rxpbs_table) / \
122 sizeof(e1000_82580_rxpbs_table[0]))
126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
127 * @hw: pointer to the HW structure
129 * Called to determine if the I2C pins are being used for I2C or as an
130 * external MDIO interface since the two options are mutually exclusive.
132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
135 bool ext_mdio = false;
137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
139 switch (hw->mac.type) {
142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 ext_mdio = !!(reg & E1000_MDIC_DEST);
150 reg = E1000_READ_REG(hw, E1000_MDICNFG);
151 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
160 * e1000_init_phy_params_82575 - Init PHY func ptrs.
161 * @hw: pointer to the HW structure
163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
165 struct e1000_phy_info *phy = &hw->phy;
166 s32 ret_val = E1000_SUCCESS;
169 DEBUGFUNC("e1000_init_phy_params_82575");
171 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
172 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
174 if (hw->phy.media_type != e1000_media_type_copper) {
175 phy->type = e1000_phy_none;
179 phy->ops.power_up = e1000_power_up_phy_copper;
180 phy->ops.power_down = e1000_power_down_phy_copper_82575;
182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
183 phy->reset_delay_us = 100;
185 phy->ops.acquire = e1000_acquire_phy_82575;
186 phy->ops.check_reset_block = e1000_check_reset_block_generic;
187 phy->ops.commit = e1000_phy_sw_reset_generic;
188 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
189 phy->ops.release = e1000_release_phy_82575;
191 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
193 if (e1000_sgmii_active_82575(hw)) {
194 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
195 ctrl_ext |= E1000_CTRL_I2C_ENA;
197 phy->ops.reset = e1000_phy_hw_reset_generic;
198 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
202 e1000_reset_mdicnfg_82580(hw);
204 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
205 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
206 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
208 switch (hw->mac.type) {
212 phy->ops.read_reg = e1000_read_phy_reg_82580;
213 phy->ops.write_reg = e1000_write_phy_reg_82580;
217 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
218 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
221 phy->ops.read_reg = e1000_read_phy_reg_igp;
222 phy->ops.write_reg = e1000_write_phy_reg_igp;
226 /* Set phy->phy_addr and phy->id. */
227 ret_val = e1000_get_phy_id_82575(hw);
229 /* Verify phy id and set remaining function pointers */
231 case M88E1543_E_PHY_ID:
232 case M88E1512_E_PHY_ID:
233 case I347AT4_E_PHY_ID:
234 case M88E1112_E_PHY_ID:
235 case M88E1340M_E_PHY_ID:
236 case M88E1111_I_PHY_ID:
237 phy->type = e1000_phy_m88;
238 phy->ops.check_polarity = e1000_check_polarity_m88;
239 phy->ops.get_info = e1000_get_phy_info_m88;
240 if (phy->id == I347AT4_E_PHY_ID ||
241 phy->id == M88E1112_E_PHY_ID ||
242 phy->id == M88E1340M_E_PHY_ID)
243 phy->ops.get_cable_length =
244 e1000_get_cable_length_m88_gen2;
245 else if (phy->id == M88E1543_E_PHY_ID ||
246 phy->id == M88E1512_E_PHY_ID)
247 phy->ops.get_cable_length =
248 e1000_get_cable_length_m88_gen2;
250 phy->ops.get_cable_length = e1000_get_cable_length_m88;
251 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
252 /* Check if this PHY is confgured for media swap. */
253 if (phy->id == M88E1112_E_PHY_ID) {
256 ret_val = phy->ops.write_reg(hw,
257 E1000_M88E1112_PAGE_ADDR,
262 ret_val = phy->ops.read_reg(hw,
263 E1000_M88E1112_MAC_CTRL_1,
268 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
269 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
270 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
271 data == E1000_M88E1112_AUTO_COPPER_BASEX)
272 hw->mac.ops.check_for_link =
273 e1000_check_for_link_media_swap;
276 case IGP03E1000_E_PHY_ID:
277 case IGP04E1000_E_PHY_ID:
278 phy->type = e1000_phy_igp_3;
279 phy->ops.check_polarity = e1000_check_polarity_igp;
280 phy->ops.get_info = e1000_get_phy_info_igp;
281 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
282 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
283 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
284 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
286 case I82580_I_PHY_ID:
288 phy->type = e1000_phy_82580;
289 phy->ops.check_polarity = e1000_check_polarity_82577;
290 phy->ops.force_speed_duplex =
291 e1000_phy_force_speed_duplex_82577;
292 phy->ops.get_cable_length = e1000_get_cable_length_82577;
293 phy->ops.get_info = e1000_get_phy_info_82577;
294 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
295 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
298 phy->type = e1000_phy_i210;
299 phy->ops.check_polarity = e1000_check_polarity_m88;
300 phy->ops.get_info = e1000_get_phy_info_m88;
301 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
302 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
303 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
304 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
307 ret_val = -E1000_ERR_PHY;
316 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
317 * @hw: pointer to the HW structure
319 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
321 struct e1000_nvm_info *nvm = &hw->nvm;
322 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
325 DEBUGFUNC("e1000_init_nvm_params_82575");
327 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
328 E1000_EECD_SIZE_EX_SHIFT);
330 * Added to a constant, "size" becomes the left-shift value
331 * for setting word_size.
333 size += NVM_WORD_SIZE_BASE_SHIFT;
335 /* Just in case size is out of range, cap it to the largest
336 * EEPROM size supported
341 nvm->word_size = 1 << size;
342 if (hw->mac.type < e1000_i210) {
343 nvm->opcode_bits = 8;
346 switch (nvm->override) {
347 case e1000_nvm_override_spi_large:
349 nvm->address_bits = 16;
351 case e1000_nvm_override_spi_small:
353 nvm->address_bits = 8;
356 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
357 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
361 if (nvm->word_size == (1 << 15))
362 nvm->page_size = 128;
364 nvm->type = e1000_nvm_eeprom_spi;
366 nvm->type = e1000_nvm_flash_hw;
369 /* Function Pointers */
370 nvm->ops.acquire = e1000_acquire_nvm_82575;
371 nvm->ops.release = e1000_release_nvm_82575;
372 if (nvm->word_size < (1 << 15))
373 nvm->ops.read = e1000_read_nvm_eerd;
375 nvm->ops.read = e1000_read_nvm_spi;
377 nvm->ops.write = e1000_write_nvm_spi;
378 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
379 nvm->ops.update = e1000_update_nvm_checksum_generic;
380 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
382 /* override generic family function pointers for specific descendants */
383 switch (hw->mac.type) {
385 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
386 nvm->ops.update = e1000_update_nvm_checksum_82580;
389 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
390 nvm->ops.update = e1000_update_nvm_checksum_i350;
396 return E1000_SUCCESS;
400 * e1000_init_mac_params_82575 - Init MAC func ptrs.
401 * @hw: pointer to the HW structure
403 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
405 struct e1000_mac_info *mac = &hw->mac;
406 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
408 DEBUGFUNC("e1000_init_mac_params_82575");
410 /* Derives media type */
411 e1000_get_media_type_82575(hw);
412 /* Set mta register count */
413 mac->mta_reg_count = 128;
414 /* Set uta register count */
415 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
416 /* Set rar entry count */
417 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
418 if (mac->type == e1000_82576)
419 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
420 if (mac->type == e1000_82580)
421 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
422 if (mac->type == e1000_i350 || mac->type == e1000_i354)
423 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
425 /* Enable EEE default settings for EEE supported devices */
426 if (mac->type >= e1000_i350)
427 dev_spec->eee_disable = false;
429 /* Allow a single clear of the SW semaphore on I210 and newer */
430 if (mac->type >= e1000_i210)
431 dev_spec->clear_semaphore_once = true;
433 /* Set if part includes ASF firmware */
434 mac->asf_firmware_present = true;
436 mac->has_fwsm = true;
437 /* ARC supported; valid only if manageability features are enabled. */
438 mac->arc_subsystem_valid =
439 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
441 /* Function pointers */
443 /* bus type/speed/width */
444 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
446 if (mac->type >= e1000_82580)
447 mac->ops.reset_hw = e1000_reset_hw_82580;
449 mac->ops.reset_hw = e1000_reset_hw_82575;
450 /* hw initialization */
451 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
452 mac->ops.init_hw = e1000_init_hw_i210;
454 mac->ops.init_hw = e1000_init_hw_82575;
456 mac->ops.setup_link = e1000_setup_link_generic;
457 /* physical interface link setup */
458 mac->ops.setup_physical_interface =
459 (hw->phy.media_type == e1000_media_type_copper)
460 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
461 /* physical interface shutdown */
462 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
463 /* physical interface power up */
464 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
466 mac->ops.check_for_link = e1000_check_for_link_82575;
467 /* read mac address */
468 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
469 /* configure collision distance */
470 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
471 /* multicast address update */
472 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
473 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
475 mac->ops.write_vfta = e1000_write_vfta_i350;
477 mac->ops.clear_vfta = e1000_clear_vfta_i350;
480 mac->ops.write_vfta = e1000_write_vfta_generic;
482 mac->ops.clear_vfta = e1000_clear_vfta_generic;
484 if (hw->mac.type >= e1000_82580)
485 mac->ops.validate_mdi_setting =
486 e1000_validate_mdi_setting_crossover_generic;
488 mac->ops.id_led_init = e1000_id_led_init_generic;
490 mac->ops.blink_led = e1000_blink_led_generic;
492 mac->ops.setup_led = e1000_setup_led_generic;
494 mac->ops.cleanup_led = e1000_cleanup_led_generic;
495 /* turn on/off LED */
496 mac->ops.led_on = e1000_led_on_generic;
497 mac->ops.led_off = e1000_led_off_generic;
498 /* clear hardware counters */
499 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
501 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
502 /* acquire SW_FW sync */
503 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
504 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
505 if (mac->type >= e1000_i210) {
506 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
507 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
510 /* set lan id for port to determine which phy lock to use */
511 hw->mac.ops.set_lan_id(hw);
513 return E1000_SUCCESS;
517 * e1000_init_function_pointers_82575 - Init func ptrs.
518 * @hw: pointer to the HW structure
520 * Called to initialize all function pointers and parameters.
522 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
524 DEBUGFUNC("e1000_init_function_pointers_82575");
526 hw->mac.ops.init_params = e1000_init_mac_params_82575;
527 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
528 hw->phy.ops.init_params = e1000_init_phy_params_82575;
529 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
533 * e1000_acquire_phy_82575 - Acquire rights to access PHY
534 * @hw: pointer to the HW structure
536 * Acquire access rights to the correct PHY.
538 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
540 u16 mask = E1000_SWFW_PHY0_SM;
542 DEBUGFUNC("e1000_acquire_phy_82575");
544 if (hw->bus.func == E1000_FUNC_1)
545 mask = E1000_SWFW_PHY1_SM;
546 else if (hw->bus.func == E1000_FUNC_2)
547 mask = E1000_SWFW_PHY2_SM;
548 else if (hw->bus.func == E1000_FUNC_3)
549 mask = E1000_SWFW_PHY3_SM;
551 return hw->mac.ops.acquire_swfw_sync(hw, mask);
555 * e1000_release_phy_82575 - Release rights to access PHY
556 * @hw: pointer to the HW structure
558 * A wrapper to release access rights to the correct PHY.
560 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
562 u16 mask = E1000_SWFW_PHY0_SM;
564 DEBUGFUNC("e1000_release_phy_82575");
566 if (hw->bus.func == E1000_FUNC_1)
567 mask = E1000_SWFW_PHY1_SM;
568 else if (hw->bus.func == E1000_FUNC_2)
569 mask = E1000_SWFW_PHY2_SM;
570 else if (hw->bus.func == E1000_FUNC_3)
571 mask = E1000_SWFW_PHY3_SM;
573 hw->mac.ops.release_swfw_sync(hw, mask);
577 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
578 * @hw: pointer to the HW structure
579 * @offset: register offset to be read
580 * @data: pointer to the read data
582 * Reads the PHY register at offset using the serial gigabit media independent
583 * interface and stores the retrieved information in data.
585 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
588 s32 ret_val = -E1000_ERR_PARAM;
590 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
592 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
593 DEBUGOUT1("PHY Address %u is out of range\n", offset);
597 ret_val = hw->phy.ops.acquire(hw);
601 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
603 hw->phy.ops.release(hw);
610 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
611 * @hw: pointer to the HW structure
612 * @offset: register offset to write to
613 * @data: data to write at register offset
615 * Writes the data to PHY register at the offset using the serial gigabit
616 * media independent interface.
618 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
621 s32 ret_val = -E1000_ERR_PARAM;
623 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
625 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
626 DEBUGOUT1("PHY Address %d is out of range\n", offset);
630 ret_val = hw->phy.ops.acquire(hw);
634 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
636 hw->phy.ops.release(hw);
643 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
644 * @hw: pointer to the HW structure
646 * Retrieves the PHY address and ID for both PHY's which do and do not use
649 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
651 struct e1000_phy_info *phy = &hw->phy;
652 s32 ret_val = E1000_SUCCESS;
657 DEBUGFUNC("e1000_get_phy_id_82575");
659 /* some i354 devices need an extra read for phy id */
660 if (hw->mac.type == e1000_i354)
661 e1000_get_phy_id(hw);
664 * For SGMII PHYs, we try the list of possible addresses until
665 * we find one that works. For non-SGMII PHYs
666 * (e.g. integrated copper PHYs), an address of 1 should
667 * work. The result of this function should mean phy->phy_addr
668 * and phy->id are set correctly.
670 if (!e1000_sgmii_active_82575(hw)) {
672 ret_val = e1000_get_phy_id(hw);
676 if (e1000_sgmii_uses_mdio_82575(hw)) {
677 switch (hw->mac.type) {
680 mdic = E1000_READ_REG(hw, E1000_MDIC);
681 mdic &= E1000_MDIC_PHY_MASK;
682 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
689 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
690 mdic &= E1000_MDICNFG_PHY_MASK;
691 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
694 ret_val = -E1000_ERR_PHY;
698 ret_val = e1000_get_phy_id(hw);
702 /* Power on sgmii phy if it is disabled */
703 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
704 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
705 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
706 E1000_WRITE_FLUSH(hw);
710 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
711 * Therefore, we need to test 1-7
713 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
714 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
715 if (ret_val == E1000_SUCCESS) {
716 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
719 * At the time of this writing, The M88 part is
720 * the only supported SGMII PHY product.
722 if (phy_id == M88_VENDOR)
725 DEBUGOUT1("PHY address %u was unreadable\n",
730 /* A valid PHY type couldn't be found. */
731 if (phy->addr == 8) {
733 ret_val = -E1000_ERR_PHY;
735 ret_val = e1000_get_phy_id(hw);
738 /* restore previous sfp cage power state */
739 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
746 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
747 * @hw: pointer to the HW structure
749 * Resets the PHY using the serial gigabit media independent interface.
751 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
753 s32 ret_val = E1000_SUCCESS;
755 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
758 * This isn't a true "hard" reset, but is the only reset
759 * available to us at this time.
762 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
764 if (!(hw->phy.ops.write_reg))
768 * SFP documentation requires the following to configure the SPF module
769 * to work on SGMII. No further documentation is given.
771 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
775 ret_val = hw->phy.ops.commit(hw);
782 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
783 * @hw: pointer to the HW structure
784 * @active: true to enable LPLU, false to disable
786 * Sets the LPLU D0 state according to the active flag. When
787 * activating LPLU this function also disables smart speed
788 * and vice versa. LPLU will not be activated unless the
789 * device autonegotiation advertisement meets standards of
790 * either 10 or 10/100 or 10/100/1000 at all duplexes.
791 * This is a function pointer entry point only called by
792 * PHY setup routines.
794 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
796 struct e1000_phy_info *phy = &hw->phy;
797 s32 ret_val = E1000_SUCCESS;
800 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
802 if (!(hw->phy.ops.read_reg))
805 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
810 data |= IGP02E1000_PM_D0_LPLU;
811 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
816 /* When LPLU is enabled, we should disable SmartSpeed */
817 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
819 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
820 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
825 data &= ~IGP02E1000_PM_D0_LPLU;
826 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
829 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
830 * during Dx states where the power conservation is most
831 * important. During driver activity we should enable
832 * SmartSpeed, so performance is maintained.
834 if (phy->smart_speed == e1000_smart_speed_on) {
835 ret_val = phy->ops.read_reg(hw,
836 IGP01E1000_PHY_PORT_CONFIG,
841 data |= IGP01E1000_PSCFR_SMART_SPEED;
842 ret_val = phy->ops.write_reg(hw,
843 IGP01E1000_PHY_PORT_CONFIG,
847 } else if (phy->smart_speed == e1000_smart_speed_off) {
848 ret_val = phy->ops.read_reg(hw,
849 IGP01E1000_PHY_PORT_CONFIG,
854 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
855 ret_val = phy->ops.write_reg(hw,
856 IGP01E1000_PHY_PORT_CONFIG,
868 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
869 * @hw: pointer to the HW structure
870 * @active: true to enable LPLU, false to disable
872 * Sets the LPLU D0 state according to the active flag. When
873 * activating LPLU this function also disables smart speed
874 * and vice versa. LPLU will not be activated unless the
875 * device autonegotiation advertisement meets standards of
876 * either 10 or 10/100 or 10/100/1000 at all duplexes.
877 * This is a function pointer entry point only called by
878 * PHY setup routines.
880 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
882 struct e1000_phy_info *phy = &hw->phy;
883 s32 ret_val = E1000_SUCCESS;
886 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
888 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
891 data |= E1000_82580_PM_D0_LPLU;
893 /* When LPLU is enabled, we should disable SmartSpeed */
894 data &= ~E1000_82580_PM_SPD;
896 data &= ~E1000_82580_PM_D0_LPLU;
899 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
900 * during Dx states where the power conservation is most
901 * important. During driver activity we should enable
902 * SmartSpeed, so performance is maintained.
904 if (phy->smart_speed == e1000_smart_speed_on)
905 data |= E1000_82580_PM_SPD;
906 else if (phy->smart_speed == e1000_smart_speed_off)
907 data &= ~E1000_82580_PM_SPD;
910 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
915 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
916 * @hw: pointer to the HW structure
917 * @active: boolean used to enable/disable lplu
919 * Success returns 0, Failure returns 1
921 * The low power link up (lplu) state is set to the power management level D3
922 * and SmartSpeed is disabled when active is true, else clear lplu for D3
923 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
924 * is used during Dx states where the power conservation is most important.
925 * During driver activity, SmartSpeed should be enabled so performance is
928 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
930 struct e1000_phy_info *phy = &hw->phy;
931 s32 ret_val = E1000_SUCCESS;
934 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
936 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
939 data &= ~E1000_82580_PM_D3_LPLU;
941 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
942 * during Dx states where the power conservation is most
943 * important. During driver activity we should enable
944 * SmartSpeed, so performance is maintained.
946 if (phy->smart_speed == e1000_smart_speed_on)
947 data |= E1000_82580_PM_SPD;
948 else if (phy->smart_speed == e1000_smart_speed_off)
949 data &= ~E1000_82580_PM_SPD;
950 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
951 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
952 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
953 data |= E1000_82580_PM_D3_LPLU;
954 /* When LPLU is enabled, we should disable SmartSpeed */
955 data &= ~E1000_82580_PM_SPD;
958 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
963 * e1000_acquire_nvm_82575 - Request for access to EEPROM
964 * @hw: pointer to the HW structure
966 * Acquire the necessary semaphores for exclusive access to the EEPROM.
967 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
968 * Return successful if access grant bit set, else clear the request for
969 * EEPROM access and return -E1000_ERR_NVM (-1).
971 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
975 DEBUGFUNC("e1000_acquire_nvm_82575");
977 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
982 * Check if there is some access
983 * error this access may hook on
985 if (hw->mac.type == e1000_i350) {
986 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
987 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
988 E1000_EECD_TIMEOUT)) {
989 /* Clear all access error flags */
990 E1000_WRITE_REG(hw, E1000_EECD, eecd |
991 E1000_EECD_ERROR_CLR);
992 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
995 if (hw->mac.type == e1000_82580) {
996 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
997 if (eecd & E1000_EECD_BLOCKED) {
998 /* Clear access error flag */
999 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1000 E1000_EECD_BLOCKED);
1001 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1006 ret_val = e1000_acquire_nvm_generic(hw);
1008 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1015 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1016 * @hw: pointer to the HW structure
1018 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1019 * then release the semaphores acquired.
1021 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1023 DEBUGFUNC("e1000_release_nvm_82575");
1025 e1000_release_nvm_generic(hw);
1027 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1031 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1032 * @hw: pointer to the HW structure
1033 * @mask: specifies which semaphore to acquire
1035 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1036 * will also specify which port we're acquiring the lock for.
1038 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1042 u32 fwmask = mask << 16;
1043 s32 ret_val = E1000_SUCCESS;
1044 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1046 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1048 while (i < timeout) {
1049 if (e1000_get_hw_semaphore_generic(hw)) {
1050 ret_val = -E1000_ERR_SWFW_SYNC;
1054 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1055 if (!(swfw_sync & (fwmask | swmask)))
1059 * Firmware currently using resource (fwmask)
1060 * or other software thread using resource (swmask)
1062 e1000_put_hw_semaphore_generic(hw);
1068 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1069 ret_val = -E1000_ERR_SWFW_SYNC;
1073 swfw_sync |= swmask;
1074 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1076 e1000_put_hw_semaphore_generic(hw);
1083 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1084 * @hw: pointer to the HW structure
1085 * @mask: specifies which semaphore to acquire
1087 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1088 * will also specify which port we're releasing the lock for.
1090 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1094 DEBUGFUNC("e1000_release_swfw_sync_82575");
1096 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1099 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1101 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1103 e1000_put_hw_semaphore_generic(hw);
1107 * e1000_get_cfg_done_82575 - Read config done bit
1108 * @hw: pointer to the HW structure
1110 * Read the management control register for the config done bit for
1111 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1112 * to read the config done bit, so an error is *ONLY* logged and returns
1113 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1114 * would not be able to be reset or change link.
1116 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1118 s32 timeout = PHY_CFG_TIMEOUT;
1119 s32 ret_val = E1000_SUCCESS;
1120 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1122 DEBUGFUNC("e1000_get_cfg_done_82575");
1124 if (hw->bus.func == E1000_FUNC_1)
1125 mask = E1000_NVM_CFG_DONE_PORT_1;
1126 else if (hw->bus.func == E1000_FUNC_2)
1127 mask = E1000_NVM_CFG_DONE_PORT_2;
1128 else if (hw->bus.func == E1000_FUNC_3)
1129 mask = E1000_NVM_CFG_DONE_PORT_3;
1131 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1137 DEBUGOUT("MNG configuration cycle has not completed.\n");
1139 /* If EEPROM is not marked present, init the PHY manually */
1140 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1141 (hw->phy.type == e1000_phy_igp_3))
1142 e1000_phy_init_script_igp3(hw);
1148 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1149 * @hw: pointer to the HW structure
1150 * @speed: stores the current speed
1151 * @duplex: stores the current duplex
1153 * This is a wrapper function, if using the serial gigabit media independent
1154 * interface, use PCS to retrieve the link speed and duplex information.
1155 * Otherwise, use the generic function to get the link speed and duplex info.
1157 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1162 DEBUGFUNC("e1000_get_link_up_info_82575");
1164 if (hw->phy.media_type != e1000_media_type_copper)
1165 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1168 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1175 * e1000_check_for_link_82575 - Check for link
1176 * @hw: pointer to the HW structure
1178 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1179 * use the generic interface for determining link.
1181 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1186 DEBUGFUNC("e1000_check_for_link_82575");
1188 if (hw->phy.media_type != e1000_media_type_copper) {
1189 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1192 * Use this flag to determine if link needs to be checked or
1193 * not. If we have link clear the flag so that we do not
1194 * continue to check for link.
1196 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1199 * Configure Flow Control now that Auto-Neg has completed.
1200 * First, we need to restore the desired flow control
1201 * settings because we may have had to re-autoneg with a
1202 * different link partner.
1204 ret_val = e1000_config_fc_after_link_up_generic(hw);
1206 DEBUGOUT("Error configuring flow control\n");
1208 ret_val = e1000_check_for_copper_link_generic(hw);
1215 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1216 * @hw: pointer to the HW structure
1218 * Poll the M88E1112 interfaces to see which interface achieved link.
1220 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1222 struct e1000_phy_info *phy = &hw->phy;
1227 DEBUGFUNC("e1000_check_for_link_media_swap");
1229 /* Check the copper medium. */
1230 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1234 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1238 if (data & E1000_M88E1112_STATUS_LINK)
1239 port = E1000_MEDIA_PORT_COPPER;
1241 /* Check the other medium. */
1242 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1246 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1250 if (data & E1000_M88E1112_STATUS_LINK)
1251 port = E1000_MEDIA_PORT_OTHER;
1253 /* Determine if a swap needs to happen. */
1254 if (port && (hw->dev_spec._82575.media_port != port)) {
1255 hw->dev_spec._82575.media_port = port;
1256 hw->dev_spec._82575.media_changed = true;
1258 ret_val = e1000_check_for_link_82575(hw);
1261 return E1000_SUCCESS;
1265 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1266 * @hw: pointer to the HW structure
1268 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1272 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1274 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1275 !e1000_sgmii_active_82575(hw))
1278 /* Enable PCS to turn on link */
1279 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1280 reg |= E1000_PCS_CFG_PCS_EN;
1281 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1283 /* Power up the laser */
1284 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1285 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1286 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1288 /* flush the write to verify completion */
1289 E1000_WRITE_FLUSH(hw);
1294 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1295 * @hw: pointer to the HW structure
1296 * @speed: stores the current speed
1297 * @duplex: stores the current duplex
1299 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1300 * duplex, then store the values in the pointers provided.
1302 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1303 u16 *speed, u16 *duplex)
1305 struct e1000_mac_info *mac = &hw->mac;
1309 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1312 * Read the PCS Status register for link state. For non-copper mode,
1313 * the status register is not accurate. The PCS status register is
1316 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1319 * The link up bit determines when link is up on autoneg.
1321 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1322 mac->serdes_has_link = true;
1324 /* Detect and store PCS speed */
1325 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1326 *speed = SPEED_1000;
1327 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1332 /* Detect and store PCS duplex */
1333 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1334 *duplex = FULL_DUPLEX;
1336 *duplex = HALF_DUPLEX;
1338 /* Check if it is an I354 2.5Gb backplane connection. */
1339 if (mac->type == e1000_i354) {
1340 status = E1000_READ_REG(hw, E1000_STATUS);
1341 if ((status & E1000_STATUS_2P5_SKU) &&
1342 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1343 *speed = SPEED_2500;
1344 *duplex = FULL_DUPLEX;
1345 DEBUGOUT("2500 Mbs, ");
1346 DEBUGOUT("Full Duplex\n");
1351 mac->serdes_has_link = false;
1356 return E1000_SUCCESS;
1360 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1361 * @hw: pointer to the HW structure
1363 * In the case of serdes shut down sfp and PCS on driver unload
1364 * when management pass thru is not enabled.
1366 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1370 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1372 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1373 !e1000_sgmii_active_82575(hw))
1376 if (!e1000_enable_mng_pass_thru(hw)) {
1377 /* Disable PCS to turn off link */
1378 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1379 reg &= ~E1000_PCS_CFG_PCS_EN;
1380 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1382 /* shutdown the laser */
1383 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1384 reg |= E1000_CTRL_EXT_SDP3_DATA;
1385 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1387 /* flush the write to verify completion */
1388 E1000_WRITE_FLUSH(hw);
1396 * e1000_reset_hw_82575 - Reset hardware
1397 * @hw: pointer to the HW structure
1399 * This resets the hardware into a known state.
1401 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1406 DEBUGFUNC("e1000_reset_hw_82575");
1409 * Prevent the PCI-E bus from sticking if there is no TLP connection
1410 * on the last TLP read/write transaction when MAC is reset.
1412 ret_val = e1000_disable_pcie_master_generic(hw);
1414 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1416 /* set the completion timeout for interface */
1417 ret_val = e1000_set_pcie_completion_timeout(hw);
1419 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1421 DEBUGOUT("Masking off all interrupts\n");
1422 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1424 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1425 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1426 E1000_WRITE_FLUSH(hw);
1430 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1432 DEBUGOUT("Issuing a global reset to MAC\n");
1433 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1435 ret_val = e1000_get_auto_rd_done_generic(hw);
1438 * When auto config read does not complete, do not
1439 * return with an error. This can happen in situations
1440 * where there is no eeprom and prevents getting link.
1442 DEBUGOUT("Auto Read Done did not complete\n");
1445 /* If EEPROM is not present, run manual init scripts */
1446 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1447 e1000_reset_init_script_82575(hw);
1449 /* Clear any pending interrupt events. */
1450 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1451 E1000_READ_REG(hw, E1000_ICR);
1453 /* Install any alternate MAC address into RAR0 */
1454 ret_val = e1000_check_alt_mac_addr_generic(hw);
1460 * e1000_init_hw_82575 - Initialize hardware
1461 * @hw: pointer to the HW structure
1463 * This inits the hardware readying it for operation.
1465 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1467 struct e1000_mac_info *mac = &hw->mac;
1469 u16 i, rar_count = mac->rar_entry_count;
1471 DEBUGFUNC("e1000_init_hw_82575");
1473 /* Initialize identification LED */
1474 ret_val = mac->ops.id_led_init(hw);
1476 DEBUGOUT("Error initializing identification LED\n");
1477 /* This is not fatal and we should not stop init due to this */
1480 /* Disabling VLAN filtering */
1481 DEBUGOUT("Initializing the IEEE VLAN\n");
1482 mac->ops.clear_vfta(hw);
1484 /* Setup the receive address */
1485 e1000_init_rx_addrs_generic(hw, rar_count);
1487 /* Zero out the Multicast HASH table */
1488 DEBUGOUT("Zeroing the MTA\n");
1489 for (i = 0; i < mac->mta_reg_count; i++)
1490 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1492 /* Zero out the Unicast HASH table */
1493 DEBUGOUT("Zeroing the UTA\n");
1494 for (i = 0; i < mac->uta_reg_count; i++)
1495 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1497 /* Setup link and flow control */
1498 ret_val = mac->ops.setup_link(hw);
1500 /* Set the default MTU size */
1501 hw->dev_spec._82575.mtu = 1500;
1504 * Clear all of the statistics registers (clear on read). It is
1505 * important that we do this after we have tried to establish link
1506 * because the symbol error count will increment wildly if there
1509 e1000_clear_hw_cntrs_82575(hw);
1515 * e1000_setup_copper_link_82575 - Configure copper link settings
1516 * @hw: pointer to the HW structure
1518 * Configures the link for auto-neg or forced speed and duplex. Then we check
1519 * for link, once link is established calls to configure collision distance
1520 * and flow control are called.
1522 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1528 DEBUGFUNC("e1000_setup_copper_link_82575");
1530 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1531 ctrl |= E1000_CTRL_SLU;
1532 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1533 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1535 /* Clear Go Link Disconnect bit on supported devices */
1536 switch (hw->mac.type) {
1541 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1542 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1543 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1549 ret_val = e1000_setup_serdes_link_82575(hw);
1553 if (e1000_sgmii_active_82575(hw)) {
1554 /* allow time for SFP cage time to power up phy */
1557 ret_val = hw->phy.ops.reset(hw);
1559 DEBUGOUT("Error resetting the PHY.\n");
1563 switch (hw->phy.type) {
1564 case e1000_phy_i210:
1566 switch (hw->phy.id) {
1567 case I347AT4_E_PHY_ID:
1568 case M88E1112_E_PHY_ID:
1569 case M88E1340M_E_PHY_ID:
1570 case M88E1543_E_PHY_ID:
1571 case M88E1512_E_PHY_ID:
1573 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1576 ret_val = e1000_copper_link_setup_m88(hw);
1580 case e1000_phy_igp_3:
1581 ret_val = e1000_copper_link_setup_igp(hw);
1583 case e1000_phy_82580:
1584 ret_val = e1000_copper_link_setup_82577(hw);
1587 ret_val = -E1000_ERR_PHY;
1594 ret_val = e1000_setup_copper_link_generic(hw);
1600 * e1000_setup_serdes_link_82575 - Setup link for serdes
1601 * @hw: pointer to the HW structure
1603 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1604 * used on copper connections where the serialized gigabit media independent
1605 * interface (sgmii), or serdes fiber is being used. Configures the link
1606 * for auto-negotiation or forces speed/duplex.
1608 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1610 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1612 s32 ret_val = E1000_SUCCESS;
1615 DEBUGFUNC("e1000_setup_serdes_link_82575");
1617 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1618 !e1000_sgmii_active_82575(hw))
1622 * On the 82575, SerDes loopback mode persists until it is
1623 * explicitly turned off or a power cycle is performed. A read to
1624 * the register does not indicate its status. Therefore, we ensure
1625 * loopback mode is disabled during initialization.
1627 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1629 /* power on the sfp cage if present */
1630 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1631 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1632 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1634 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1635 ctrl_reg |= E1000_CTRL_SLU;
1637 /* set both sw defined pins on 82575/82576*/
1638 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1639 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1641 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1643 /* default pcs_autoneg to the same setting as mac autoneg */
1644 pcs_autoneg = hw->mac.autoneg;
1646 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1647 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1648 /* sgmii mode lets the phy handle forcing speed/duplex */
1650 /* autoneg time out should be disabled for SGMII mode */
1651 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1653 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1654 /* disable PCS autoneg and support parallel detect only */
1655 pcs_autoneg = false;
1656 /* fall through to default case */
1658 if (hw->mac.type == e1000_82575 ||
1659 hw->mac.type == e1000_82576) {
1660 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1662 DEBUGOUT("NVM Read Error\n");
1666 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1667 pcs_autoneg = false;
1671 * non-SGMII modes only supports a speed of 1000/Full for the
1672 * link so it is best to just force the MAC and let the pcs
1673 * link either autoneg or be forced to 1000/Full
1675 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1676 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1678 /* set speed of 1000/Full if speed/duplex is forced */
1679 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1683 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1686 * New SerDes mode allows for forcing speed or autonegotiating speed
1687 * at 1gb. Autoneg should be default set by most drivers. This is the
1688 * mode that will be compatible with older link partners and switches.
1689 * However, both are supported by the hardware and some drivers/tools.
1691 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1692 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1695 /* Set PCS register for autoneg */
1696 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1697 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1699 /* Disable force flow control for autoneg */
1700 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1702 /* Configure flow control advertisement for autoneg */
1703 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1704 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1706 switch (hw->fc.requested_mode) {
1708 case e1000_fc_rx_pause:
1709 anadv_reg |= E1000_TXCW_ASM_DIR;
1710 anadv_reg |= E1000_TXCW_PAUSE;
1712 case e1000_fc_tx_pause:
1713 anadv_reg |= E1000_TXCW_ASM_DIR;
1719 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1721 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1723 /* Set PCS register for forced link */
1724 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1726 /* Force flow control for forced link */
1727 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1729 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1732 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1734 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1735 e1000_force_mac_fc_generic(hw);
1741 * e1000_get_media_type_82575 - derives current media type.
1742 * @hw: pointer to the HW structure
1744 * The media type is chosen reflecting few settings.
1745 * The following are taken into account:
1746 * - link mode set in the current port Init Control Word #3
1747 * - current link mode settings in CSR register
1748 * - MDIO vs. I2C PHY control interface chosen
1749 * - SFP module media type
1751 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1753 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1754 s32 ret_val = E1000_SUCCESS;
1758 /* Set internal phy as default */
1759 dev_spec->sgmii_active = false;
1760 dev_spec->module_plugged = false;
1762 /* Get CSR setting */
1763 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1765 /* extract link mode setting */
1766 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1768 switch (link_mode) {
1769 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1770 hw->phy.media_type = e1000_media_type_internal_serdes;
1772 case E1000_CTRL_EXT_LINK_MODE_GMII:
1773 hw->phy.media_type = e1000_media_type_copper;
1775 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1776 /* Get phy control interface type set (MDIO vs. I2C)*/
1777 if (e1000_sgmii_uses_mdio_82575(hw)) {
1778 hw->phy.media_type = e1000_media_type_copper;
1779 dev_spec->sgmii_active = true;
1782 /* fall through for I2C based SGMII */
1783 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1784 /* read media type from SFP EEPROM */
1785 ret_val = e1000_set_sfp_media_type_82575(hw);
1786 if ((ret_val != E1000_SUCCESS) ||
1787 (hw->phy.media_type == e1000_media_type_unknown)) {
1789 * If media type was not identified then return media
1790 * type defined by the CTRL_EXT settings.
1792 hw->phy.media_type = e1000_media_type_internal_serdes;
1794 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1795 hw->phy.media_type = e1000_media_type_copper;
1796 dev_spec->sgmii_active = true;
1802 /* do not change link mode for 100BaseFX */
1803 if (dev_spec->eth_flags.e100_base_fx)
1806 /* change current link mode setting */
1807 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1809 if (hw->phy.media_type == e1000_media_type_copper)
1810 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1812 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1814 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1823 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1824 * @hw: pointer to the HW structure
1826 * The media type is chosen based on SFP module.
1827 * compatibility flags retrieved from SFP ID EEPROM.
1829 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1831 s32 ret_val = E1000_ERR_CONFIG;
1833 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1834 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1835 u8 tranceiver_type = 0;
1838 /* Turn I2C interface ON and power on sfp cage */
1839 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1840 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1841 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1843 E1000_WRITE_FLUSH(hw);
1845 /* Read SFP module data */
1847 ret_val = e1000_read_sfp_data_byte(hw,
1848 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1850 if (ret_val == E1000_SUCCESS)
1855 if (ret_val != E1000_SUCCESS)
1858 ret_val = e1000_read_sfp_data_byte(hw,
1859 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1861 if (ret_val != E1000_SUCCESS)
1864 /* Check if there is some SFP module plugged and powered */
1865 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1866 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1867 dev_spec->module_plugged = true;
1868 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1869 hw->phy.media_type = e1000_media_type_internal_serdes;
1870 } else if (eth_flags->e100_base_fx) {
1871 dev_spec->sgmii_active = true;
1872 hw->phy.media_type = e1000_media_type_internal_serdes;
1873 } else if (eth_flags->e1000_base_t) {
1874 dev_spec->sgmii_active = true;
1875 hw->phy.media_type = e1000_media_type_copper;
1877 hw->phy.media_type = e1000_media_type_unknown;
1878 DEBUGOUT("PHY module has not been recognized\n");
1882 hw->phy.media_type = e1000_media_type_unknown;
1884 ret_val = E1000_SUCCESS;
1886 /* Restore I2C interface setting */
1887 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1892 * e1000_valid_led_default_82575 - Verify a valid default LED config
1893 * @hw: pointer to the HW structure
1894 * @data: pointer to the NVM (EEPROM)
1896 * Read the EEPROM for the current default LED configuration. If the
1897 * LED configuration is not valid, set to a valid LED configuration.
1899 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1903 DEBUGFUNC("e1000_valid_led_default_82575");
1905 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1907 DEBUGOUT("NVM Read Error\n");
1911 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1912 switch (hw->phy.media_type) {
1913 case e1000_media_type_internal_serdes:
1914 *data = ID_LED_DEFAULT_82575_SERDES;
1916 case e1000_media_type_copper:
1918 *data = ID_LED_DEFAULT;
1927 * e1000_sgmii_active_82575 - Return sgmii state
1928 * @hw: pointer to the HW structure
1930 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1931 * which can be enabled for use in the embedded applications. Simply
1932 * return the current state of the sgmii interface.
1934 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1936 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1937 return dev_spec->sgmii_active;
1941 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1942 * @hw: pointer to the HW structure
1944 * Inits recommended HW defaults after a reset when there is no EEPROM
1945 * detected. This is only for the 82575.
1947 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1949 DEBUGFUNC("e1000_reset_init_script_82575");
1951 if (hw->mac.type == e1000_82575) {
1952 DEBUGOUT("Running reset init script for 82575\n");
1953 /* SerDes configuration via SERDESCTRL */
1954 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1955 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1956 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1957 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1959 /* CCM configuration via CCMCTL register */
1960 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1961 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1963 /* PCIe lanes configuration */
1964 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1965 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1966 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1967 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1969 /* PCIe PLL Configuration */
1970 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1971 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1972 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1975 return E1000_SUCCESS;
1979 * e1000_read_mac_addr_82575 - Read device MAC address
1980 * @hw: pointer to the HW structure
1982 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1986 DEBUGFUNC("e1000_read_mac_addr_82575");
1989 * If there's an alternate MAC address place it in RAR0
1990 * so that it will override the Si installed default perm
1993 ret_val = e1000_check_alt_mac_addr_generic(hw);
1997 ret_val = e1000_read_mac_addr_generic(hw);
2004 * e1000_config_collision_dist_82575 - Configure collision distance
2005 * @hw: pointer to the HW structure
2007 * Configures the collision distance to the default value and is used
2008 * during link setup.
2010 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2014 DEBUGFUNC("e1000_config_collision_dist_82575");
2016 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2018 tctl_ext &= ~E1000_TCTL_EXT_COLD;
2019 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2021 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2022 E1000_WRITE_FLUSH(hw);
2026 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2027 * @hw: pointer to the HW structure
2029 * In the case of a PHY power down to save power, or to turn off link during a
2030 * driver unload, or wake on lan is not enabled, remove the link.
2032 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2034 struct e1000_phy_info *phy = &hw->phy;
2036 if (!(phy->ops.check_reset_block))
2039 /* If the management interface is not enabled, then power down */
2040 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2041 e1000_power_down_phy_copper(hw);
2047 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2048 * @hw: pointer to the HW structure
2050 * Clears the hardware counters by reading the counter registers.
2052 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2054 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2056 e1000_clear_hw_cntrs_base_generic(hw);
2058 E1000_READ_REG(hw, E1000_PRC64);
2059 E1000_READ_REG(hw, E1000_PRC127);
2060 E1000_READ_REG(hw, E1000_PRC255);
2061 E1000_READ_REG(hw, E1000_PRC511);
2062 E1000_READ_REG(hw, E1000_PRC1023);
2063 E1000_READ_REG(hw, E1000_PRC1522);
2064 E1000_READ_REG(hw, E1000_PTC64);
2065 E1000_READ_REG(hw, E1000_PTC127);
2066 E1000_READ_REG(hw, E1000_PTC255);
2067 E1000_READ_REG(hw, E1000_PTC511);
2068 E1000_READ_REG(hw, E1000_PTC1023);
2069 E1000_READ_REG(hw, E1000_PTC1522);
2071 E1000_READ_REG(hw, E1000_ALGNERRC);
2072 E1000_READ_REG(hw, E1000_RXERRC);
2073 E1000_READ_REG(hw, E1000_TNCRS);
2074 E1000_READ_REG(hw, E1000_CEXTERR);
2075 E1000_READ_REG(hw, E1000_TSCTC);
2076 E1000_READ_REG(hw, E1000_TSCTFC);
2078 E1000_READ_REG(hw, E1000_MGTPRC);
2079 E1000_READ_REG(hw, E1000_MGTPDC);
2080 E1000_READ_REG(hw, E1000_MGTPTC);
2082 E1000_READ_REG(hw, E1000_IAC);
2083 E1000_READ_REG(hw, E1000_ICRXOC);
2085 E1000_READ_REG(hw, E1000_ICRXPTC);
2086 E1000_READ_REG(hw, E1000_ICRXATC);
2087 E1000_READ_REG(hw, E1000_ICTXPTC);
2088 E1000_READ_REG(hw, E1000_ICTXATC);
2089 E1000_READ_REG(hw, E1000_ICTXQEC);
2090 E1000_READ_REG(hw, E1000_ICTXQMTC);
2091 E1000_READ_REG(hw, E1000_ICRXDMTC);
2093 E1000_READ_REG(hw, E1000_CBTMPC);
2094 E1000_READ_REG(hw, E1000_HTDPMC);
2095 E1000_READ_REG(hw, E1000_CBRMPC);
2096 E1000_READ_REG(hw, E1000_RPTHC);
2097 E1000_READ_REG(hw, E1000_HGPTC);
2098 E1000_READ_REG(hw, E1000_HTCBDPC);
2099 E1000_READ_REG(hw, E1000_HGORCL);
2100 E1000_READ_REG(hw, E1000_HGORCH);
2101 E1000_READ_REG(hw, E1000_HGOTCL);
2102 E1000_READ_REG(hw, E1000_HGOTCH);
2103 E1000_READ_REG(hw, E1000_LENERRS);
2105 /* This register should not be read in copper configurations */
2106 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2107 e1000_sgmii_active_82575(hw))
2108 E1000_READ_REG(hw, E1000_SCVPC);
2112 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2113 * @hw: pointer to the HW structure
2115 * After rx enable if managability is enabled then there is likely some
2116 * bad data at the start of the fifo and possibly in the DMA fifo. This
2117 * function clears the fifos and flushes any packets that came in as rx was
2120 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2122 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2125 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2126 if (hw->mac.type != e1000_82575 ||
2127 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2130 /* Disable all Rx queues */
2131 for (i = 0; i < 4; i++) {
2132 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2133 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2134 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2136 /* Poll all queues to verify they have shut down */
2137 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2140 for (i = 0; i < 4; i++)
2141 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2142 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2147 DEBUGOUT("Queue disable timed out after 10ms\n");
2149 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2150 * incoming packets are rejected. Set enable and wait 2ms so that
2151 * any packet that was coming in as RCTL.EN was set is flushed
2153 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2154 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2156 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2157 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2159 rctl = E1000_READ_REG(hw, E1000_RCTL);
2160 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2161 temp_rctl |= E1000_RCTL_LPE;
2163 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2164 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2165 E1000_WRITE_FLUSH(hw);
2168 /* Enable Rx queues that were previously enabled and restore our
2171 for (i = 0; i < 4; i++)
2172 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2173 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2174 E1000_WRITE_FLUSH(hw);
2176 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2177 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2179 /* Flush receive errors generated by workaround */
2180 E1000_READ_REG(hw, E1000_ROC);
2181 E1000_READ_REG(hw, E1000_RNBC);
2182 E1000_READ_REG(hw, E1000_MPC);
2186 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2187 * @hw: pointer to the HW structure
2189 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2190 * however the hardware default for these parts is 500us to 1ms which is less
2191 * than the 10ms recommended by the pci-e spec. To address this we need to
2192 * increase the value to either 10ms to 200ms for capability version 1 config,
2193 * or 16ms to 55ms for version 2.
2195 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2197 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2198 s32 ret_val = E1000_SUCCESS;
2201 /* only take action if timeout value is defaulted to 0 */
2202 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2206 * if capababilities version is type 1 we can write the
2207 * timeout of 10ms to 200ms through the GCR register
2209 if (!(gcr & E1000_GCR_CAP_VER2)) {
2210 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2215 * for version 2 capabilities we need to write the config space
2216 * directly in order to set the completion timeout value for
2219 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2224 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2226 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2229 /* disable completion timeout resend */
2230 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2232 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2237 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2238 * @hw: pointer to the hardware struct
2239 * @enable: state to enter, either enabled or disabled
2240 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2242 * enables/disables L2 switch anti-spoofing functionality.
2244 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2246 u32 reg_val, reg_offset;
2248 switch (hw->mac.type) {
2250 reg_offset = E1000_DTXSWC;
2254 reg_offset = E1000_TXSWC;
2260 reg_val = E1000_READ_REG(hw, reg_offset);
2262 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2263 E1000_DTXSWC_VLAN_SPOOF_MASK);
2264 /* The PF can spoof - it has to in order to
2265 * support emulation mode NICs
2267 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2269 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2270 E1000_DTXSWC_VLAN_SPOOF_MASK);
2272 E1000_WRITE_REG(hw, reg_offset, reg_val);
2276 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2277 * @hw: pointer to the hardware struct
2278 * @enable: state to enter, either enabled or disabled
2280 * enables/disables L2 switch loopback functionality.
2282 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2286 switch (hw->mac.type) {
2288 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2290 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2292 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2293 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2297 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2299 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2301 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2302 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2305 /* Currently no other hardware supports loopback */
2313 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2314 * @hw: pointer to the hardware struct
2315 * @enable: state to enter, either enabled or disabled
2317 * enables/disables replication of packets across multiple pools.
2319 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2321 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2324 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2326 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2328 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2332 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2333 * @hw: pointer to the HW structure
2334 * @offset: register offset to be read
2335 * @data: pointer to the read data
2337 * Reads the MDI control register in the PHY at offset and stores the
2338 * information read to data.
2340 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2344 DEBUGFUNC("e1000_read_phy_reg_82580");
2346 ret_val = hw->phy.ops.acquire(hw);
2350 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2352 hw->phy.ops.release(hw);
2359 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2360 * @hw: pointer to the HW structure
2361 * @offset: register offset to write to
2362 * @data: data to write to register at offset
2364 * Writes data to MDI control register in the PHY at offset.
2366 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2370 DEBUGFUNC("e1000_write_phy_reg_82580");
2372 ret_val = hw->phy.ops.acquire(hw);
2376 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2378 hw->phy.ops.release(hw);
2385 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2386 * @hw: pointer to the HW structure
2388 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2389 * the values found in the EEPROM. This addresses an issue in which these
2390 * bits are not restored from EEPROM after reset.
2392 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2394 s32 ret_val = E1000_SUCCESS;
2398 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2400 if (hw->mac.type != e1000_82580)
2402 if (!e1000_sgmii_active_82575(hw))
2405 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2406 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2409 DEBUGOUT("NVM Read Error\n");
2413 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2414 if (nvm_data & NVM_WORD24_EXT_MDIO)
2415 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2416 if (nvm_data & NVM_WORD24_COM_MDIO)
2417 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2418 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2424 * e1000_reset_hw_82580 - Reset hardware
2425 * @hw: pointer to the HW structure
2427 * This resets function or entire device (all ports, etc.)
2430 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2432 s32 ret_val = E1000_SUCCESS;
2433 /* BH SW mailbox bit in SW_FW_SYNC */
2434 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2436 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2438 DEBUGFUNC("e1000_reset_hw_82580");
2440 hw->dev_spec._82575.global_device_reset = false;
2442 /* 82580 does not reliably do global_device_reset due to hw errata */
2443 if (hw->mac.type == e1000_82580)
2444 global_device_reset = false;
2446 /* Get current control state. */
2447 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2450 * Prevent the PCI-E bus from sticking if there is no TLP connection
2451 * on the last TLP read/write transaction when MAC is reset.
2453 ret_val = e1000_disable_pcie_master_generic(hw);
2455 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2457 DEBUGOUT("Masking off all interrupts\n");
2458 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2459 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2460 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2461 E1000_WRITE_FLUSH(hw);
2465 /* Determine whether or not a global dev reset is requested */
2466 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2468 global_device_reset = false;
2470 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2471 E1000_STAT_DEV_RST_SET))
2472 ctrl |= E1000_CTRL_DEV_RST;
2474 ctrl |= E1000_CTRL_RST;
2476 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2477 E1000_WRITE_FLUSH(hw);
2479 /* Add delay to insure DEV_RST has time to complete */
2480 if (global_device_reset)
2483 ret_val = e1000_get_auto_rd_done_generic(hw);
2486 * When auto config read does not complete, do not
2487 * return with an error. This can happen in situations
2488 * where there is no eeprom and prevents getting link.
2490 DEBUGOUT("Auto Read Done did not complete\n");
2493 /* clear global device reset status bit */
2494 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2496 /* Clear any pending interrupt events. */
2497 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2498 E1000_READ_REG(hw, E1000_ICR);
2500 ret_val = e1000_reset_mdicnfg_82580(hw);
2502 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2504 /* Install any alternate MAC address into RAR0 */
2505 ret_val = e1000_check_alt_mac_addr_generic(hw);
2507 /* Release semaphore */
2508 if (global_device_reset)
2509 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2515 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2516 * @data: data received by reading RXPBS register
2518 * The 82580 uses a table based approach for packet buffer allocation sizes.
2519 * This function converts the retrieved value into the correct table value
2520 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2521 * 0x0 36 72 144 1 2 4 8 16
2522 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2524 u16 e1000_rxpbs_adjust_82580(u32 data)
2528 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2529 ret_val = e1000_82580_rxpbs_table[data];
2535 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2537 * @hw: pointer to the HW structure
2538 * @offset: offset in words of the checksum protected region
2540 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2541 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2543 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2545 s32 ret_val = E1000_SUCCESS;
2549 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2551 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2552 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2554 DEBUGOUT("NVM Read Error\n");
2557 checksum += nvm_data;
2560 if (checksum != (u16) NVM_SUM) {
2561 DEBUGOUT("NVM Checksum Invalid\n");
2562 ret_val = -E1000_ERR_NVM;
2571 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2573 * @hw: pointer to the HW structure
2574 * @offset: offset in words of the checksum protected region
2576 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2577 * up to the checksum. Then calculates the EEPROM checksum and writes the
2578 * value to the EEPROM.
2580 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2586 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2588 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2589 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2591 DEBUGOUT("NVM Read Error while updating checksum.\n");
2594 checksum += nvm_data;
2596 checksum = (u16) NVM_SUM - checksum;
2597 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2600 DEBUGOUT("NVM Write Error while updating checksum.\n");
2607 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2608 * @hw: pointer to the HW structure
2610 * Calculates the EEPROM section checksum by reading/adding each word of
2611 * the EEPROM and then verifies that the sum of the EEPROM is
2614 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2617 u16 eeprom_regions_count = 1;
2621 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2623 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2625 DEBUGOUT("NVM Read Error\n");
2629 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2630 /* if chekcsums compatibility bit is set validate checksums
2631 * for all 4 ports. */
2632 eeprom_regions_count = 4;
2635 for (j = 0; j < eeprom_regions_count; j++) {
2636 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2637 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2639 if (ret_val != E1000_SUCCESS)
2648 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2649 * @hw: pointer to the HW structure
2651 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2652 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2653 * checksum and writes the value to the EEPROM.
2655 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2661 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2663 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2665 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2669 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2670 /* set compatibility bit to validate checksums appropriately */
2671 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2672 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2675 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2680 for (j = 0; j < 4; j++) {
2681 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2682 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2692 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2693 * @hw: pointer to the HW structure
2695 * Calculates the EEPROM section checksum by reading/adding each word of
2696 * the EEPROM and then verifies that the sum of the EEPROM is
2699 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2701 s32 ret_val = E1000_SUCCESS;
2705 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2707 for (j = 0; j < 4; j++) {
2708 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2709 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2711 if (ret_val != E1000_SUCCESS)
2720 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2721 * @hw: pointer to the HW structure
2723 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2724 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2725 * checksum and writes the value to the EEPROM.
2727 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2729 s32 ret_val = E1000_SUCCESS;
2733 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2735 for (j = 0; j < 4; j++) {
2736 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2737 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2738 if (ret_val != E1000_SUCCESS)
2747 * __e1000_access_emi_reg - Read/write EMI register
2748 * @hw: pointer to the HW structure
2749 * @addr: EMI address to program
2750 * @data: pointer to value to read/write from/to the EMI address
2751 * @read: boolean flag to indicate read or write
2753 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2754 u16 *data, bool read)
2758 DEBUGFUNC("__e1000_access_emi_reg");
2760 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2765 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2767 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2773 * e1000_read_emi_reg - Read Extended Management Interface register
2774 * @hw: pointer to the HW structure
2775 * @addr: EMI address to program
2776 * @data: value to be read from the EMI address
2778 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2780 DEBUGFUNC("e1000_read_emi_reg");
2782 return __e1000_access_emi_reg(hw, addr, data, true);
2786 * e1000_set_eee_i350 - Enable/disable EEE support
2787 * @hw: pointer to the HW structure
2789 * Enable/disable EEE based on setting in dev_spec structure.
2792 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2794 s32 ret_val = E1000_SUCCESS;
2797 DEBUGFUNC("e1000_set_eee_i350");
2799 if ((hw->mac.type < e1000_i350) ||
2800 (hw->phy.media_type != e1000_media_type_copper))
2802 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2803 eeer = E1000_READ_REG(hw, E1000_EEER);
2805 /* enable or disable per user setting */
2806 if (!(hw->dev_spec._82575.eee_disable)) {
2807 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2809 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2810 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2813 /* This bit should not be set in normal operation. */
2814 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2815 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2817 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2818 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2821 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2822 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2823 E1000_READ_REG(hw, E1000_IPCNFG);
2824 E1000_READ_REG(hw, E1000_EEER);
2831 * e1000_set_eee_i354 - Enable/disable EEE support
2832 * @hw: pointer to the HW structure
2834 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2837 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2839 struct e1000_phy_info *phy = &hw->phy;
2840 s32 ret_val = E1000_SUCCESS;
2843 DEBUGFUNC("e1000_set_eee_i354");
2845 if ((hw->phy.media_type != e1000_media_type_copper) ||
2846 ((phy->id != M88E1543_E_PHY_ID) &&
2847 (phy->id != M88E1512_E_PHY_ID)))
2850 if (!hw->dev_spec._82575.eee_disable) {
2851 /* Switch to PHY page 18. */
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2856 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2861 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2862 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2867 /* Return the PHY to page 0. */
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2872 /* Turn on EEE advertisement. */
2873 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2874 E1000_EEE_ADV_DEV_I354,
2879 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2880 E1000_EEE_ADV_1000_SUPPORTED;
2881 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2882 E1000_EEE_ADV_DEV_I354,
2885 /* Turn off EEE advertisement. */
2886 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2887 E1000_EEE_ADV_DEV_I354,
2892 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2893 E1000_EEE_ADV_1000_SUPPORTED);
2894 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2895 E1000_EEE_ADV_DEV_I354,
2904 * e1000_get_eee_status_i354 - Get EEE status
2905 * @hw: pointer to the HW structure
2906 * @status: EEE status
2908 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2911 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2913 struct e1000_phy_info *phy = &hw->phy;
2914 s32 ret_val = E1000_SUCCESS;
2917 DEBUGFUNC("e1000_get_eee_status_i354");
2919 /* Check if EEE is supported on this device. */
2920 if ((hw->phy.media_type != e1000_media_type_copper) ||
2921 ((phy->id != M88E1543_E_PHY_ID) &&
2922 (phy->id != M88E1512_E_PHY_ID)))
2925 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2926 E1000_PCS_STATUS_DEV_I354,
2931 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2932 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2938 /* Due to a hw errata, if the host tries to configure the VFTA register
2939 * while performing queries from the BMC or DMA, then the VFTA in some
2940 * cases won't be written.
2944 * e1000_clear_vfta_i350 - Clear VLAN filter table
2945 * @hw: pointer to the HW structure
2947 * Clears the register array which contains the VLAN filter table by
2948 * setting all the values to 0.
2950 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2955 DEBUGFUNC("e1000_clear_vfta_350");
2957 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2958 for (i = 0; i < 10; i++)
2959 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2961 E1000_WRITE_FLUSH(hw);
2966 * e1000_write_vfta_i350 - Write value to VLAN filter table
2967 * @hw: pointer to the HW structure
2968 * @offset: register offset in VLAN filter table
2969 * @value: register value written to VLAN filter table
2971 * Writes value at the given offset in the register array which stores
2972 * the VLAN filter table.
2974 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2978 DEBUGFUNC("e1000_write_vfta_350");
2980 for (i = 0; i < 10; i++)
2981 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2983 E1000_WRITE_FLUSH(hw);
2988 * e1000_set_i2c_bb - Enable I2C bit-bang
2989 * @hw: pointer to the HW structure
2991 * Enable I2C bit-bang interface
2994 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2996 s32 ret_val = E1000_SUCCESS;
2997 u32 ctrl_ext, i2cparams;
2999 DEBUGFUNC("e1000_set_i2c_bb");
3001 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3002 ctrl_ext |= E1000_CTRL_I2C_ENA;
3003 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3004 E1000_WRITE_FLUSH(hw);
3006 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3007 i2cparams |= E1000_I2CBB_EN;
3008 i2cparams |= E1000_I2C_DATA_OE_N;
3009 i2cparams |= E1000_I2C_CLK_OE_N;
3010 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3011 E1000_WRITE_FLUSH(hw);
3017 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3018 * @hw: pointer to hardware structure
3019 * @byte_offset: byte offset to read
3020 * @dev_addr: device address
3023 * Performs byte read operation over I2C interface at
3024 * a specified device address.
3026 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3027 u8 dev_addr, u8 *data)
3029 s32 status = E1000_SUCCESS;
3036 DEBUGFUNC("e1000_read_i2c_byte_generic");
3038 swfw_mask = E1000_SWFW_PHY0_SM;
3041 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3043 status = E1000_ERR_SWFW_SYNC;
3047 e1000_i2c_start(hw);
3049 /* Device Address and write indication */
3050 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3051 if (status != E1000_SUCCESS)
3054 status = e1000_get_i2c_ack(hw);
3055 if (status != E1000_SUCCESS)
3058 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3059 if (status != E1000_SUCCESS)
3062 status = e1000_get_i2c_ack(hw);
3063 if (status != E1000_SUCCESS)
3066 e1000_i2c_start(hw);
3068 /* Device Address and read indication */
3069 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3070 if (status != E1000_SUCCESS)
3073 status = e1000_get_i2c_ack(hw);
3074 if (status != E1000_SUCCESS)
3077 status = e1000_clock_in_i2c_byte(hw, data);
3078 if (status != E1000_SUCCESS)
3081 status = e1000_clock_out_i2c_bit(hw, nack);
3082 if (status != E1000_SUCCESS)
3089 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3091 e1000_i2c_bus_clear(hw);
3093 if (retry < max_retry)
3094 DEBUGOUT("I2C byte read error - Retrying.\n");
3096 DEBUGOUT("I2C byte read error.\n");
3098 } while (retry < max_retry);
3100 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3108 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3109 * @hw: pointer to hardware structure
3110 * @byte_offset: byte offset to write
3111 * @dev_addr: device address
3112 * @data: value to write
3114 * Performs byte write operation over I2C interface at
3115 * a specified device address.
3117 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3118 u8 dev_addr, u8 data)
3120 s32 status = E1000_SUCCESS;
3125 DEBUGFUNC("e1000_write_i2c_byte_generic");
3127 swfw_mask = E1000_SWFW_PHY0_SM;
3129 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3130 status = E1000_ERR_SWFW_SYNC;
3131 goto write_byte_out;
3135 e1000_i2c_start(hw);
3137 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3138 if (status != E1000_SUCCESS)
3141 status = e1000_get_i2c_ack(hw);
3142 if (status != E1000_SUCCESS)
3145 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3146 if (status != E1000_SUCCESS)
3149 status = e1000_get_i2c_ack(hw);
3150 if (status != E1000_SUCCESS)
3153 status = e1000_clock_out_i2c_byte(hw, data);
3154 if (status != E1000_SUCCESS)
3157 status = e1000_get_i2c_ack(hw);
3158 if (status != E1000_SUCCESS)
3165 e1000_i2c_bus_clear(hw);
3167 if (retry < max_retry)
3168 DEBUGOUT("I2C byte write error - Retrying.\n");
3170 DEBUGOUT("I2C byte write error.\n");
3171 } while (retry < max_retry);
3173 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3181 * e1000_i2c_start - Sets I2C start condition
3182 * @hw: pointer to hardware structure
3184 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3186 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3188 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3190 DEBUGFUNC("e1000_i2c_start");
3192 /* Start condition must begin with data and clock high */
3193 e1000_set_i2c_data(hw, &i2cctl, 1);
3194 e1000_raise_i2c_clk(hw, &i2cctl);
3196 /* Setup time for start condition (4.7us) */
3197 usec_delay(E1000_I2C_T_SU_STA);
3199 e1000_set_i2c_data(hw, &i2cctl, 0);
3201 /* Hold time for start condition (4us) */
3202 usec_delay(E1000_I2C_T_HD_STA);
3204 e1000_lower_i2c_clk(hw, &i2cctl);
3206 /* Minimum low period of clock is 4.7 us */
3207 usec_delay(E1000_I2C_T_LOW);
3212 * e1000_i2c_stop - Sets I2C stop condition
3213 * @hw: pointer to hardware structure
3215 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3217 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3219 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3221 DEBUGFUNC("e1000_i2c_stop");
3223 /* Stop condition must begin with data low and clock high */
3224 e1000_set_i2c_data(hw, &i2cctl, 0);
3225 e1000_raise_i2c_clk(hw, &i2cctl);
3227 /* Setup time for stop condition (4us) */
3228 usec_delay(E1000_I2C_T_SU_STO);
3230 e1000_set_i2c_data(hw, &i2cctl, 1);
3232 /* bus free time between stop and start (4.7us)*/
3233 usec_delay(E1000_I2C_T_BUF);
3237 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3238 * @hw: pointer to hardware structure
3239 * @data: data byte to clock in
3241 * Clocks in one byte data via I2C data/clock
3243 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3248 DEBUGFUNC("e1000_clock_in_i2c_byte");
3251 for (i = 7; i >= 0; i--) {
3252 e1000_clock_in_i2c_bit(hw, &bit);
3256 return E1000_SUCCESS;
3260 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3261 * @hw: pointer to hardware structure
3262 * @data: data byte clocked out
3264 * Clocks out one byte data via I2C data/clock
3266 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3268 s32 status = E1000_SUCCESS;
3273 DEBUGFUNC("e1000_clock_out_i2c_byte");
3275 for (i = 7; i >= 0; i--) {
3276 bit = (data >> i) & 0x1;
3277 status = e1000_clock_out_i2c_bit(hw, bit);
3279 if (status != E1000_SUCCESS)
3283 /* Release SDA line (set high) */
3284 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3286 i2cctl |= E1000_I2C_DATA_OE_N;
3287 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3288 E1000_WRITE_FLUSH(hw);
3294 * e1000_get_i2c_ack - Polls for I2C ACK
3295 * @hw: pointer to hardware structure
3297 * Clocks in/out one bit via I2C data/clock
3299 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3301 s32 status = E1000_SUCCESS;
3303 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3307 DEBUGFUNC("e1000_get_i2c_ack");
3309 e1000_raise_i2c_clk(hw, &i2cctl);
3311 /* Minimum high period of clock is 4us */
3312 usec_delay(E1000_I2C_T_HIGH);
3314 /* Wait until SCL returns high */
3315 for (i = 0; i < timeout; i++) {
3317 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3318 if (i2cctl & E1000_I2C_CLK_IN)
3321 if (!(i2cctl & E1000_I2C_CLK_IN))
3322 return E1000_ERR_I2C;
3324 ack = e1000_get_i2c_data(&i2cctl);
3326 DEBUGOUT("I2C ack was not received.\n");
3327 status = E1000_ERR_I2C;
3330 e1000_lower_i2c_clk(hw, &i2cctl);
3332 /* Minimum low period of clock is 4.7 us */
3333 usec_delay(E1000_I2C_T_LOW);
3339 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3340 * @hw: pointer to hardware structure
3341 * @data: read data value
3343 * Clocks in one bit via I2C data/clock
3345 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3347 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3349 DEBUGFUNC("e1000_clock_in_i2c_bit");
3351 e1000_raise_i2c_clk(hw, &i2cctl);
3353 /* Minimum high period of clock is 4us */
3354 usec_delay(E1000_I2C_T_HIGH);
3356 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3357 *data = e1000_get_i2c_data(&i2cctl);
3359 e1000_lower_i2c_clk(hw, &i2cctl);
3361 /* Minimum low period of clock is 4.7 us */
3362 usec_delay(E1000_I2C_T_LOW);
3364 return E1000_SUCCESS;
3368 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3369 * @hw: pointer to hardware structure
3370 * @data: data value to write
3372 * Clocks out one bit via I2C data/clock
3374 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3377 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3379 DEBUGFUNC("e1000_clock_out_i2c_bit");
3381 status = e1000_set_i2c_data(hw, &i2cctl, data);
3382 if (status == E1000_SUCCESS) {
3383 e1000_raise_i2c_clk(hw, &i2cctl);
3385 /* Minimum high period of clock is 4us */
3386 usec_delay(E1000_I2C_T_HIGH);
3388 e1000_lower_i2c_clk(hw, &i2cctl);
3390 /* Minimum low period of clock is 4.7 us.
3391 * This also takes care of the data hold time.
3393 usec_delay(E1000_I2C_T_LOW);
3395 status = E1000_ERR_I2C;
3396 DEBUGOUT1("I2C data was not set to %X\n", data);
3402 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3403 * @hw: pointer to hardware structure
3404 * @i2cctl: Current value of I2CCTL register
3406 * Raises the I2C clock line '0'->'1'
3408 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3410 DEBUGFUNC("e1000_raise_i2c_clk");
3412 *i2cctl |= E1000_I2C_CLK_OUT;
3413 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3414 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3415 E1000_WRITE_FLUSH(hw);
3417 /* SCL rise time (1000ns) */
3418 usec_delay(E1000_I2C_T_RISE);
3422 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3423 * @hw: pointer to hardware structure
3424 * @i2cctl: Current value of I2CCTL register
3426 * Lowers the I2C clock line '1'->'0'
3428 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3431 DEBUGFUNC("e1000_lower_i2c_clk");
3433 *i2cctl &= ~E1000_I2C_CLK_OUT;
3434 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3435 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3436 E1000_WRITE_FLUSH(hw);
3438 /* SCL fall time (300ns) */
3439 usec_delay(E1000_I2C_T_FALL);
3443 * e1000_set_i2c_data - Sets the I2C data bit
3444 * @hw: pointer to hardware structure
3445 * @i2cctl: Current value of I2CCTL register
3446 * @data: I2C data value (0 or 1) to set
3448 * Sets the I2C data bit
3450 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3452 s32 status = E1000_SUCCESS;
3454 DEBUGFUNC("e1000_set_i2c_data");
3457 *i2cctl |= E1000_I2C_DATA_OUT;
3459 *i2cctl &= ~E1000_I2C_DATA_OUT;
3461 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3462 *i2cctl |= E1000_I2C_CLK_OE_N;
3463 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3464 E1000_WRITE_FLUSH(hw);
3466 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3467 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3469 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3470 if (data != e1000_get_i2c_data(i2cctl)) {
3471 status = E1000_ERR_I2C;
3472 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3479 * e1000_get_i2c_data - Reads the I2C SDA data bit
3480 * @hw: pointer to hardware structure
3481 * @i2cctl: Current value of I2CCTL register
3483 * Returns the I2C data bit value
3485 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3489 DEBUGFUNC("e1000_get_i2c_data");
3491 if (*i2cctl & E1000_I2C_DATA_IN)
3500 * e1000_i2c_bus_clear - Clears the I2C bus
3501 * @hw: pointer to hardware structure
3503 * Clears the I2C bus by sending nine clock pulses.
3504 * Used when data line is stuck low.
3506 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3508 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3511 DEBUGFUNC("e1000_i2c_bus_clear");
3513 e1000_i2c_start(hw);
3515 e1000_set_i2c_data(hw, &i2cctl, 1);
3517 for (i = 0; i < 9; i++) {
3518 e1000_raise_i2c_clk(hw, &i2cctl);
3520 /* Min high period of clock is 4us */
3521 usec_delay(E1000_I2C_T_HIGH);
3523 e1000_lower_i2c_clk(hw, &i2cctl);
3525 /* Min low period of clock is 4.7us*/
3526 usec_delay(E1000_I2C_T_LOW);
3529 e1000_i2c_start(hw);
3531 /* Put the i2c bus back to default state */