1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
40 * 82580 Gigabit Network Connection
41 * I350 Gigabit Network Connection
44 #include "e1000_api.h"
45 #include "e1000_i210.h"
47 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
49 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
55 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw);
59 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
62 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
65 u32 offset, u16 *data);
66 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
67 u32 offset, u16 data);
68 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
80 u32 offset, u16 data);
81 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
84 u16 *speed, u16 *duplex);
85 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
100 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
102 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
105 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
107 STATIC void e1000_i2c_start(struct e1000_hw *hw);
108 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
109 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
110 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
111 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
112 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
113 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
114 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
116 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
117 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
119 STATIC const u16 e1000_82580_rxpbs_table[] = {
120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
121 #define E1000_82580_RXPBS_TABLE_SIZE \
122 (sizeof(e1000_82580_rxpbs_table) / \
123 sizeof(e1000_82580_rxpbs_table[0]))
127 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
128 * @hw: pointer to the HW structure
130 * Called to determine if the I2C pins are being used for I2C or as an
131 * external MDIO interface since the two options are mutually exclusive.
133 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
136 bool ext_mdio = false;
138 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
140 switch (hw->mac.type) {
143 reg = E1000_READ_REG(hw, E1000_MDIC);
144 ext_mdio = !!(reg & E1000_MDIC_DEST);
151 reg = E1000_READ_REG(hw, E1000_MDICNFG);
152 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
161 * e1000_init_phy_params_82575 - Init PHY func ptrs.
162 * @hw: pointer to the HW structure
164 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
166 struct e1000_phy_info *phy = &hw->phy;
167 s32 ret_val = E1000_SUCCESS;
170 DEBUGFUNC("e1000_init_phy_params_82575");
172 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
173 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
175 if (hw->phy.media_type != e1000_media_type_copper) {
176 phy->type = e1000_phy_none;
180 phy->ops.power_up = e1000_power_up_phy_copper;
181 phy->ops.power_down = e1000_power_down_phy_copper_82575;
183 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
184 phy->reset_delay_us = 100;
186 phy->ops.acquire = e1000_acquire_phy_82575;
187 phy->ops.check_reset_block = e1000_check_reset_block_generic;
188 phy->ops.commit = e1000_phy_sw_reset_generic;
189 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
190 phy->ops.release = e1000_release_phy_82575;
192 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
194 if (e1000_sgmii_active_82575(hw)) {
195 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
196 ctrl_ext |= E1000_CTRL_I2C_ENA;
198 phy->ops.reset = e1000_phy_hw_reset_generic;
199 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
202 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
203 e1000_reset_mdicnfg_82580(hw);
205 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
206 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
207 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
209 switch (hw->mac.type) {
213 phy->ops.read_reg = e1000_read_phy_reg_82580;
214 phy->ops.write_reg = e1000_write_phy_reg_82580;
218 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
219 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
222 phy->ops.read_reg = e1000_read_phy_reg_igp;
223 phy->ops.write_reg = e1000_write_phy_reg_igp;
227 /* Set phy->phy_addr and phy->id. */
228 ret_val = e1000_get_phy_id_82575(hw);
230 /* Verify phy id and set remaining function pointers */
232 case M88E1543_E_PHY_ID:
233 case M88E1512_E_PHY_ID:
234 case I347AT4_E_PHY_ID:
235 case M88E1112_E_PHY_ID:
236 case M88E1340M_E_PHY_ID:
237 case M88E1111_I_PHY_ID:
238 phy->type = e1000_phy_m88;
239 phy->ops.check_polarity = e1000_check_polarity_m88;
240 phy->ops.get_info = e1000_get_phy_info_m88;
241 if (phy->id == I347AT4_E_PHY_ID ||
242 phy->id == M88E1112_E_PHY_ID ||
243 phy->id == M88E1340M_E_PHY_ID)
244 phy->ops.get_cable_length =
245 e1000_get_cable_length_m88_gen2;
246 else if (phy->id == M88E1543_E_PHY_ID ||
247 phy->id == M88E1512_E_PHY_ID)
248 phy->ops.get_cable_length =
249 e1000_get_cable_length_m88_gen2;
251 phy->ops.get_cable_length = e1000_get_cable_length_m88;
252 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
253 /* Check if this PHY is confgured for media swap. */
254 if (phy->id == M88E1112_E_PHY_ID) {
257 ret_val = phy->ops.write_reg(hw,
258 E1000_M88E1112_PAGE_ADDR,
263 ret_val = phy->ops.read_reg(hw,
264 E1000_M88E1112_MAC_CTRL_1,
269 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
270 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
271 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
272 data == E1000_M88E1112_AUTO_COPPER_BASEX)
273 hw->mac.ops.check_for_link =
274 e1000_check_for_link_media_swap;
277 case IGP03E1000_E_PHY_ID:
278 case IGP04E1000_E_PHY_ID:
279 phy->type = e1000_phy_igp_3;
280 phy->ops.check_polarity = e1000_check_polarity_igp;
281 phy->ops.get_info = e1000_get_phy_info_igp;
282 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
283 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
284 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
285 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
287 case I82580_I_PHY_ID:
289 phy->type = e1000_phy_82580;
290 phy->ops.check_polarity = e1000_check_polarity_82577;
291 phy->ops.force_speed_duplex =
292 e1000_phy_force_speed_duplex_82577;
293 phy->ops.get_cable_length = e1000_get_cable_length_82577;
294 phy->ops.get_info = e1000_get_phy_info_82577;
295 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
296 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
299 phy->type = e1000_phy_i210;
300 phy->ops.check_polarity = e1000_check_polarity_m88;
301 phy->ops.get_info = e1000_get_phy_info_m88;
302 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
303 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
304 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
305 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
308 ret_val = -E1000_ERR_PHY;
317 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
318 * @hw: pointer to the HW structure
320 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
322 struct e1000_nvm_info *nvm = &hw->nvm;
323 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
326 DEBUGFUNC("e1000_init_nvm_params_82575");
328 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
329 E1000_EECD_SIZE_EX_SHIFT);
331 * Added to a constant, "size" becomes the left-shift value
332 * for setting word_size.
334 size += NVM_WORD_SIZE_BASE_SHIFT;
336 /* Just in case size is out of range, cap it to the largest
337 * EEPROM size supported
342 nvm->word_size = 1 << size;
343 if (hw->mac.type < e1000_i210) {
344 nvm->opcode_bits = 8;
347 switch (nvm->override) {
348 case e1000_nvm_override_spi_large:
350 nvm->address_bits = 16;
352 case e1000_nvm_override_spi_small:
354 nvm->address_bits = 8;
357 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
358 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
362 if (nvm->word_size == (1 << 15))
363 nvm->page_size = 128;
365 nvm->type = e1000_nvm_eeprom_spi;
367 nvm->type = e1000_nvm_flash_hw;
370 /* Function Pointers */
371 nvm->ops.acquire = e1000_acquire_nvm_82575;
372 nvm->ops.release = e1000_release_nvm_82575;
373 if (nvm->word_size < (1 << 15))
374 nvm->ops.read = e1000_read_nvm_eerd;
376 nvm->ops.read = e1000_read_nvm_spi;
378 nvm->ops.write = e1000_write_nvm_spi;
379 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
380 nvm->ops.update = e1000_update_nvm_checksum_generic;
381 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
383 /* override generic family function pointers for specific descendants */
384 switch (hw->mac.type) {
386 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
387 nvm->ops.update = e1000_update_nvm_checksum_82580;
390 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
391 nvm->ops.update = e1000_update_nvm_checksum_i350;
397 return E1000_SUCCESS;
401 * e1000_init_mac_params_82575 - Init MAC func ptrs.
402 * @hw: pointer to the HW structure
404 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
406 struct e1000_mac_info *mac = &hw->mac;
407 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
409 DEBUGFUNC("e1000_init_mac_params_82575");
411 /* Derives media type */
412 e1000_get_media_type_82575(hw);
413 /* Set mta register count */
414 mac->mta_reg_count = 128;
415 /* Set uta register count */
416 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
417 /* Set rar entry count */
418 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
419 if (mac->type == e1000_82576)
420 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
421 if (mac->type == e1000_82580)
422 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
423 if (mac->type == e1000_i350 || mac->type == e1000_i354)
424 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
426 /* Enable EEE default settings for EEE supported devices */
427 if (mac->type >= e1000_i350)
428 dev_spec->eee_disable = false;
430 /* Allow a single clear of the SW semaphore on I210 and newer */
431 if (mac->type >= e1000_i210)
432 dev_spec->clear_semaphore_once = true;
434 /* Set if part includes ASF firmware */
435 mac->asf_firmware_present = true;
437 mac->has_fwsm = true;
438 /* ARC supported; valid only if manageability features are enabled. */
439 mac->arc_subsystem_valid =
440 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
442 /* Function pointers */
444 /* bus type/speed/width */
445 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
447 if (mac->type >= e1000_82580)
448 mac->ops.reset_hw = e1000_reset_hw_82580;
450 mac->ops.reset_hw = e1000_reset_hw_82575;
451 /* hw initialization */
452 mac->ops.init_hw = e1000_init_hw_82575;
454 mac->ops.setup_link = e1000_setup_link_generic;
455 /* physical interface link setup */
456 mac->ops.setup_physical_interface =
457 (hw->phy.media_type == e1000_media_type_copper)
458 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
459 /* physical interface shutdown */
460 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
461 /* physical interface power up */
462 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
464 mac->ops.check_for_link = e1000_check_for_link_82575;
465 /* read mac address */
466 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
467 /* configure collision distance */
468 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
469 /* multicast address update */
470 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
471 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
473 mac->ops.write_vfta = e1000_write_vfta_i350;
475 mac->ops.clear_vfta = e1000_clear_vfta_i350;
478 mac->ops.write_vfta = e1000_write_vfta_generic;
480 mac->ops.clear_vfta = e1000_clear_vfta_generic;
482 if (hw->mac.type >= e1000_82580)
483 mac->ops.validate_mdi_setting =
484 e1000_validate_mdi_setting_crossover_generic;
486 mac->ops.id_led_init = e1000_id_led_init_generic;
488 mac->ops.blink_led = e1000_blink_led_generic;
490 mac->ops.setup_led = e1000_setup_led_generic;
492 mac->ops.cleanup_led = e1000_cleanup_led_generic;
493 /* turn on/off LED */
494 mac->ops.led_on = e1000_led_on_generic;
495 mac->ops.led_off = e1000_led_off_generic;
496 /* clear hardware counters */
497 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
499 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
500 /* acquire SW_FW sync */
501 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
502 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
503 if (mac->type >= e1000_i210) {
504 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
505 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
508 /* set lan id for port to determine which phy lock to use */
509 hw->mac.ops.set_lan_id(hw);
511 return E1000_SUCCESS;
515 * e1000_init_function_pointers_82575 - Init func ptrs.
516 * @hw: pointer to the HW structure
518 * Called to initialize all function pointers and parameters.
520 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
522 DEBUGFUNC("e1000_init_function_pointers_82575");
524 hw->mac.ops.init_params = e1000_init_mac_params_82575;
525 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
526 hw->phy.ops.init_params = e1000_init_phy_params_82575;
527 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
531 * e1000_acquire_phy_82575 - Acquire rights to access PHY
532 * @hw: pointer to the HW structure
534 * Acquire access rights to the correct PHY.
536 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
538 u16 mask = E1000_SWFW_PHY0_SM;
540 DEBUGFUNC("e1000_acquire_phy_82575");
542 if (hw->bus.func == E1000_FUNC_1)
543 mask = E1000_SWFW_PHY1_SM;
544 else if (hw->bus.func == E1000_FUNC_2)
545 mask = E1000_SWFW_PHY2_SM;
546 else if (hw->bus.func == E1000_FUNC_3)
547 mask = E1000_SWFW_PHY3_SM;
549 return hw->mac.ops.acquire_swfw_sync(hw, mask);
553 * e1000_release_phy_82575 - Release rights to access PHY
554 * @hw: pointer to the HW structure
556 * A wrapper to release access rights to the correct PHY.
558 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
560 u16 mask = E1000_SWFW_PHY0_SM;
562 DEBUGFUNC("e1000_release_phy_82575");
564 if (hw->bus.func == E1000_FUNC_1)
565 mask = E1000_SWFW_PHY1_SM;
566 else if (hw->bus.func == E1000_FUNC_2)
567 mask = E1000_SWFW_PHY2_SM;
568 else if (hw->bus.func == E1000_FUNC_3)
569 mask = E1000_SWFW_PHY3_SM;
571 hw->mac.ops.release_swfw_sync(hw, mask);
575 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
576 * @hw: pointer to the HW structure
577 * @offset: register offset to be read
578 * @data: pointer to the read data
580 * Reads the PHY register at offset using the serial gigabit media independent
581 * interface and stores the retrieved information in data.
583 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
586 s32 ret_val = -E1000_ERR_PARAM;
588 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
590 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
591 DEBUGOUT1("PHY Address %u is out of range\n", offset);
595 ret_val = hw->phy.ops.acquire(hw);
599 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
601 hw->phy.ops.release(hw);
608 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
609 * @hw: pointer to the HW structure
610 * @offset: register offset to write to
611 * @data: data to write at register offset
613 * Writes the data to PHY register at the offset using the serial gigabit
614 * media independent interface.
616 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
619 s32 ret_val = -E1000_ERR_PARAM;
621 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
623 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
624 DEBUGOUT1("PHY Address %d is out of range\n", offset);
628 ret_val = hw->phy.ops.acquire(hw);
632 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
634 hw->phy.ops.release(hw);
641 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
642 * @hw: pointer to the HW structure
644 * Retrieves the PHY address and ID for both PHY's which do and do not use
647 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
649 struct e1000_phy_info *phy = &hw->phy;
650 s32 ret_val = E1000_SUCCESS;
655 DEBUGFUNC("e1000_get_phy_id_82575");
657 /* some i354 devices need an extra read for phy id */
658 if (hw->mac.type == e1000_i354)
659 e1000_get_phy_id(hw);
662 * For SGMII PHYs, we try the list of possible addresses until
663 * we find one that works. For non-SGMII PHYs
664 * (e.g. integrated copper PHYs), an address of 1 should
665 * work. The result of this function should mean phy->phy_addr
666 * and phy->id are set correctly.
668 if (!e1000_sgmii_active_82575(hw)) {
670 ret_val = e1000_get_phy_id(hw);
674 if (e1000_sgmii_uses_mdio_82575(hw)) {
675 switch (hw->mac.type) {
678 mdic = E1000_READ_REG(hw, E1000_MDIC);
679 mdic &= E1000_MDIC_PHY_MASK;
680 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
687 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
688 mdic &= E1000_MDICNFG_PHY_MASK;
689 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
692 ret_val = -E1000_ERR_PHY;
696 ret_val = e1000_get_phy_id(hw);
700 /* Power on sgmii phy if it is disabled */
701 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
702 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
703 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
704 E1000_WRITE_FLUSH(hw);
708 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
709 * Therefore, we need to test 1-7
711 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
712 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
713 if (ret_val == E1000_SUCCESS) {
714 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
717 * At the time of this writing, The M88 part is
718 * the only supported SGMII PHY product.
720 if (phy_id == M88_VENDOR)
723 DEBUGOUT1("PHY address %u was unreadable\n",
728 /* A valid PHY type couldn't be found. */
729 if (phy->addr == 8) {
731 ret_val = -E1000_ERR_PHY;
733 ret_val = e1000_get_phy_id(hw);
736 /* restore previous sfp cage power state */
737 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
744 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
745 * @hw: pointer to the HW structure
747 * Resets the PHY using the serial gigabit media independent interface.
749 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
751 s32 ret_val = E1000_SUCCESS;
753 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
756 * This isn't a true "hard" reset, but is the only reset
757 * available to us at this time.
760 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
762 if (!(hw->phy.ops.write_reg))
766 * SFP documentation requires the following to configure the SPF module
767 * to work on SGMII. No further documentation is given.
769 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
773 ret_val = hw->phy.ops.commit(hw);
780 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
781 * @hw: pointer to the HW structure
782 * @active: true to enable LPLU, false to disable
784 * Sets the LPLU D0 state according to the active flag. When
785 * activating LPLU this function also disables smart speed
786 * and vice versa. LPLU will not be activated unless the
787 * device autonegotiation advertisement meets standards of
788 * either 10 or 10/100 or 10/100/1000 at all duplexes.
789 * This is a function pointer entry point only called by
790 * PHY setup routines.
792 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
794 struct e1000_phy_info *phy = &hw->phy;
795 s32 ret_val = E1000_SUCCESS;
798 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
800 if (!(hw->phy.ops.read_reg))
803 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
808 data |= IGP02E1000_PM_D0_LPLU;
809 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
814 /* When LPLU is enabled, we should disable SmartSpeed */
815 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
817 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
818 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
823 data &= ~IGP02E1000_PM_D0_LPLU;
824 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
827 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
828 * during Dx states where the power conservation is most
829 * important. During driver activity we should enable
830 * SmartSpeed, so performance is maintained.
832 if (phy->smart_speed == e1000_smart_speed_on) {
833 ret_val = phy->ops.read_reg(hw,
834 IGP01E1000_PHY_PORT_CONFIG,
839 data |= IGP01E1000_PSCFR_SMART_SPEED;
840 ret_val = phy->ops.write_reg(hw,
841 IGP01E1000_PHY_PORT_CONFIG,
845 } else if (phy->smart_speed == e1000_smart_speed_off) {
846 ret_val = phy->ops.read_reg(hw,
847 IGP01E1000_PHY_PORT_CONFIG,
852 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
853 ret_val = phy->ops.write_reg(hw,
854 IGP01E1000_PHY_PORT_CONFIG,
866 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
867 * @hw: pointer to the HW structure
868 * @active: true to enable LPLU, false to disable
870 * Sets the LPLU D0 state according to the active flag. When
871 * activating LPLU this function also disables smart speed
872 * and vice versa. LPLU will not be activated unless the
873 * device autonegotiation advertisement meets standards of
874 * either 10 or 10/100 or 10/100/1000 at all duplexes.
875 * This is a function pointer entry point only called by
876 * PHY setup routines.
878 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
880 struct e1000_phy_info *phy = &hw->phy;
881 s32 ret_val = E1000_SUCCESS;
884 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
886 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
889 data |= E1000_82580_PM_D0_LPLU;
891 /* When LPLU is enabled, we should disable SmartSpeed */
892 data &= ~E1000_82580_PM_SPD;
894 data &= ~E1000_82580_PM_D0_LPLU;
897 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
898 * during Dx states where the power conservation is most
899 * important. During driver activity we should enable
900 * SmartSpeed, so performance is maintained.
902 if (phy->smart_speed == e1000_smart_speed_on)
903 data |= E1000_82580_PM_SPD;
904 else if (phy->smart_speed == e1000_smart_speed_off)
905 data &= ~E1000_82580_PM_SPD;
908 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
913 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
914 * @hw: pointer to the HW structure
915 * @active: boolean used to enable/disable lplu
917 * Success returns 0, Failure returns 1
919 * The low power link up (lplu) state is set to the power management level D3
920 * and SmartSpeed is disabled when active is true, else clear lplu for D3
921 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
922 * is used during Dx states where the power conservation is most important.
923 * During driver activity, SmartSpeed should be enabled so performance is
926 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
928 struct e1000_phy_info *phy = &hw->phy;
929 s32 ret_val = E1000_SUCCESS;
932 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
934 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
937 data &= ~E1000_82580_PM_D3_LPLU;
939 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
940 * during Dx states where the power conservation is most
941 * important. During driver activity we should enable
942 * SmartSpeed, so performance is maintained.
944 if (phy->smart_speed == e1000_smart_speed_on)
945 data |= E1000_82580_PM_SPD;
946 else if (phy->smart_speed == e1000_smart_speed_off)
947 data &= ~E1000_82580_PM_SPD;
948 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
949 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
950 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
951 data |= E1000_82580_PM_D3_LPLU;
952 /* When LPLU is enabled, we should disable SmartSpeed */
953 data &= ~E1000_82580_PM_SPD;
956 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
961 * e1000_acquire_nvm_82575 - Request for access to EEPROM
962 * @hw: pointer to the HW structure
964 * Acquire the necessary semaphores for exclusive access to the EEPROM.
965 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
966 * Return successful if access grant bit set, else clear the request for
967 * EEPROM access and return -E1000_ERR_NVM (-1).
969 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
973 DEBUGFUNC("e1000_acquire_nvm_82575");
975 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
980 * Check if there is some access
981 * error this access may hook on
983 if (hw->mac.type == e1000_i350) {
984 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
985 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
986 E1000_EECD_TIMEOUT)) {
987 /* Clear all access error flags */
988 E1000_WRITE_REG(hw, E1000_EECD, eecd |
989 E1000_EECD_ERROR_CLR);
990 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
993 if (hw->mac.type == e1000_82580) {
994 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
995 if (eecd & E1000_EECD_BLOCKED) {
996 /* Clear access error flag */
997 E1000_WRITE_REG(hw, E1000_EECD, eecd |
999 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1004 ret_val = e1000_acquire_nvm_generic(hw);
1006 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1013 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1014 * @hw: pointer to the HW structure
1016 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1017 * then release the semaphores acquired.
1019 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1021 DEBUGFUNC("e1000_release_nvm_82575");
1023 e1000_release_nvm_generic(hw);
1025 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1029 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1030 * @hw: pointer to the HW structure
1031 * @mask: specifies which semaphore to acquire
1033 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1034 * will also specify which port we're acquiring the lock for.
1036 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1040 u32 fwmask = mask << 16;
1041 s32 ret_val = E1000_SUCCESS;
1042 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1044 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1046 while (i < timeout) {
1047 if (e1000_get_hw_semaphore_generic(hw)) {
1048 ret_val = -E1000_ERR_SWFW_SYNC;
1052 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1053 if (!(swfw_sync & (fwmask | swmask)))
1057 * Firmware currently using resource (fwmask)
1058 * or other software thread using resource (swmask)
1060 e1000_put_hw_semaphore_generic(hw);
1066 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1067 ret_val = -E1000_ERR_SWFW_SYNC;
1071 swfw_sync |= swmask;
1072 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1074 e1000_put_hw_semaphore_generic(hw);
1081 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1082 * @hw: pointer to the HW structure
1083 * @mask: specifies which semaphore to acquire
1085 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1086 * will also specify which port we're releasing the lock for.
1088 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1092 DEBUGFUNC("e1000_release_swfw_sync_82575");
1094 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1097 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1099 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1101 e1000_put_hw_semaphore_generic(hw);
1105 * e1000_get_cfg_done_82575 - Read config done bit
1106 * @hw: pointer to the HW structure
1108 * Read the management control register for the config done bit for
1109 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1110 * to read the config done bit, so an error is *ONLY* logged and returns
1111 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1112 * would not be able to be reset or change link.
1114 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1116 s32 timeout = PHY_CFG_TIMEOUT;
1117 s32 ret_val = E1000_SUCCESS;
1118 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1120 DEBUGFUNC("e1000_get_cfg_done_82575");
1122 if (hw->bus.func == E1000_FUNC_1)
1123 mask = E1000_NVM_CFG_DONE_PORT_1;
1124 else if (hw->bus.func == E1000_FUNC_2)
1125 mask = E1000_NVM_CFG_DONE_PORT_2;
1126 else if (hw->bus.func == E1000_FUNC_3)
1127 mask = E1000_NVM_CFG_DONE_PORT_3;
1129 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1135 DEBUGOUT("MNG configuration cycle has not completed.\n");
1137 /* If EEPROM is not marked present, init the PHY manually */
1138 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1139 (hw->phy.type == e1000_phy_igp_3))
1140 e1000_phy_init_script_igp3(hw);
1146 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1147 * @hw: pointer to the HW structure
1148 * @speed: stores the current speed
1149 * @duplex: stores the current duplex
1151 * This is a wrapper function, if using the serial gigabit media independent
1152 * interface, use PCS to retrieve the link speed and duplex information.
1153 * Otherwise, use the generic function to get the link speed and duplex info.
1155 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1160 DEBUGFUNC("e1000_get_link_up_info_82575");
1162 if (hw->phy.media_type != e1000_media_type_copper)
1163 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1166 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1173 * e1000_check_for_link_82575 - Check for link
1174 * @hw: pointer to the HW structure
1176 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1177 * use the generic interface for determining link.
1179 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1184 DEBUGFUNC("e1000_check_for_link_82575");
1186 if (hw->phy.media_type != e1000_media_type_copper) {
1187 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1190 * Use this flag to determine if link needs to be checked or
1191 * not. If we have link clear the flag so that we do not
1192 * continue to check for link.
1194 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1197 * Configure Flow Control now that Auto-Neg has completed.
1198 * First, we need to restore the desired flow control
1199 * settings because we may have had to re-autoneg with a
1200 * different link partner.
1202 ret_val = e1000_config_fc_after_link_up_generic(hw);
1204 DEBUGOUT("Error configuring flow control\n");
1206 ret_val = e1000_check_for_copper_link_generic(hw);
1213 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1214 * @hw: pointer to the HW structure
1216 * Poll the M88E1112 interfaces to see which interface achieved link.
1218 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1220 struct e1000_phy_info *phy = &hw->phy;
1225 DEBUGFUNC("e1000_check_for_link_media_swap");
1227 /* Check the copper medium. */
1228 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1232 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1236 if (data & E1000_M88E1112_STATUS_LINK)
1237 port = E1000_MEDIA_PORT_COPPER;
1239 /* Check the other medium. */
1240 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1244 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1248 if (data & E1000_M88E1112_STATUS_LINK)
1249 port = E1000_MEDIA_PORT_OTHER;
1251 /* Determine if a swap needs to happen. */
1252 if (port && (hw->dev_spec._82575.media_port != port)) {
1253 hw->dev_spec._82575.media_port = port;
1254 hw->dev_spec._82575.media_changed = true;
1256 ret_val = e1000_check_for_link_82575(hw);
1259 return E1000_SUCCESS;
1263 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1264 * @hw: pointer to the HW structure
1266 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1270 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1272 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1273 !e1000_sgmii_active_82575(hw))
1276 /* Enable PCS to turn on link */
1277 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1278 reg |= E1000_PCS_CFG_PCS_EN;
1279 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1281 /* Power up the laser */
1282 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1283 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1284 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1286 /* flush the write to verify completion */
1287 E1000_WRITE_FLUSH(hw);
1292 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1293 * @hw: pointer to the HW structure
1294 * @speed: stores the current speed
1295 * @duplex: stores the current duplex
1297 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1298 * duplex, then store the values in the pointers provided.
1300 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1301 u16 *speed, u16 *duplex)
1303 struct e1000_mac_info *mac = &hw->mac;
1307 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1310 * Read the PCS Status register for link state. For non-copper mode,
1311 * the status register is not accurate. The PCS status register is
1314 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1317 * The link up bit determines when link is up on autoneg.
1319 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1320 mac->serdes_has_link = true;
1322 /* Detect and store PCS speed */
1323 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1324 *speed = SPEED_1000;
1325 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1330 /* Detect and store PCS duplex */
1331 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1332 *duplex = FULL_DUPLEX;
1334 *duplex = HALF_DUPLEX;
1336 /* Check if it is an I354 2.5Gb backplane connection. */
1337 if (mac->type == e1000_i354) {
1338 status = E1000_READ_REG(hw, E1000_STATUS);
1339 if ((status & E1000_STATUS_2P5_SKU) &&
1340 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1341 *speed = SPEED_2500;
1342 *duplex = FULL_DUPLEX;
1343 DEBUGOUT("2500 Mbs, ");
1344 DEBUGOUT("Full Duplex\n");
1349 mac->serdes_has_link = false;
1354 return E1000_SUCCESS;
1358 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1359 * @hw: pointer to the HW structure
1361 * In the case of serdes shut down sfp and PCS on driver unload
1362 * when management pass thru is not enabled.
1364 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1368 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1370 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1371 !e1000_sgmii_active_82575(hw))
1374 if (!e1000_enable_mng_pass_thru(hw)) {
1375 /* Disable PCS to turn off link */
1376 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1377 reg &= ~E1000_PCS_CFG_PCS_EN;
1378 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1380 /* shutdown the laser */
1381 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1382 reg |= E1000_CTRL_EXT_SDP3_DATA;
1383 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1385 /* flush the write to verify completion */
1386 E1000_WRITE_FLUSH(hw);
1394 * e1000_reset_hw_82575 - Reset hardware
1395 * @hw: pointer to the HW structure
1397 * This resets the hardware into a known state.
1399 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1404 DEBUGFUNC("e1000_reset_hw_82575");
1407 * Prevent the PCI-E bus from sticking if there is no TLP connection
1408 * on the last TLP read/write transaction when MAC is reset.
1410 ret_val = e1000_disable_pcie_master_generic(hw);
1412 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1414 /* set the completion timeout for interface */
1415 ret_val = e1000_set_pcie_completion_timeout(hw);
1417 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1419 DEBUGOUT("Masking off all interrupts\n");
1420 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1422 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1423 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1424 E1000_WRITE_FLUSH(hw);
1428 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1430 DEBUGOUT("Issuing a global reset to MAC\n");
1431 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1433 ret_val = e1000_get_auto_rd_done_generic(hw);
1436 * When auto config read does not complete, do not
1437 * return with an error. This can happen in situations
1438 * where there is no eeprom and prevents getting link.
1440 DEBUGOUT("Auto Read Done did not complete\n");
1443 /* If EEPROM is not present, run manual init scripts */
1444 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1445 e1000_reset_init_script_82575(hw);
1447 /* Clear any pending interrupt events. */
1448 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1449 E1000_READ_REG(hw, E1000_ICR);
1451 /* Install any alternate MAC address into RAR0 */
1452 ret_val = e1000_check_alt_mac_addr_generic(hw);
1458 * e1000_init_hw_82575 - Initialize hardware
1459 * @hw: pointer to the HW structure
1461 * This inits the hardware readying it for operation.
1463 STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw)
1465 struct e1000_mac_info *mac = &hw->mac;
1467 u16 i, rar_count = mac->rar_entry_count;
1469 DEBUGFUNC("e1000_init_hw_82575");
1471 /* Initialize identification LED */
1472 ret_val = mac->ops.id_led_init(hw);
1474 DEBUGOUT("Error initializing identification LED\n");
1475 /* This is not fatal and we should not stop init due to this */
1478 /* Disabling VLAN filtering */
1479 DEBUGOUT("Initializing the IEEE VLAN\n");
1480 mac->ops.clear_vfta(hw);
1482 /* Setup the receive address */
1483 e1000_init_rx_addrs_generic(hw, rar_count);
1485 /* Zero out the Multicast HASH table */
1486 DEBUGOUT("Zeroing the MTA\n");
1487 for (i = 0; i < mac->mta_reg_count; i++)
1488 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1490 /* Zero out the Unicast HASH table */
1491 DEBUGOUT("Zeroing the UTA\n");
1492 for (i = 0; i < mac->uta_reg_count; i++)
1493 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1495 /* Setup link and flow control */
1496 ret_val = mac->ops.setup_link(hw);
1498 /* Set the default MTU size */
1499 hw->dev_spec._82575.mtu = 1500;
1502 * Clear all of the statistics registers (clear on read). It is
1503 * important that we do this after we have tried to establish link
1504 * because the symbol error count will increment wildly if there
1507 e1000_clear_hw_cntrs_82575(hw);
1513 * e1000_setup_copper_link_82575 - Configure copper link settings
1514 * @hw: pointer to the HW structure
1516 * Configures the link for auto-neg or forced speed and duplex. Then we check
1517 * for link, once link is established calls to configure collision distance
1518 * and flow control are called.
1520 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1526 DEBUGFUNC("e1000_setup_copper_link_82575");
1528 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1529 ctrl |= E1000_CTRL_SLU;
1530 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1531 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1533 /* Clear Go Link Disconnect bit on supported devices */
1534 switch (hw->mac.type) {
1539 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1540 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1541 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1547 ret_val = e1000_setup_serdes_link_82575(hw);
1551 if (e1000_sgmii_active_82575(hw)) {
1552 /* allow time for SFP cage time to power up phy */
1555 ret_val = hw->phy.ops.reset(hw);
1557 DEBUGOUT("Error resetting the PHY.\n");
1561 switch (hw->phy.type) {
1562 case e1000_phy_i210:
1564 switch (hw->phy.id) {
1565 case I347AT4_E_PHY_ID:
1566 case M88E1112_E_PHY_ID:
1567 case M88E1340M_E_PHY_ID:
1568 case M88E1543_E_PHY_ID:
1569 case M88E1512_E_PHY_ID:
1571 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1574 ret_val = e1000_copper_link_setup_m88(hw);
1578 case e1000_phy_igp_3:
1579 ret_val = e1000_copper_link_setup_igp(hw);
1581 case e1000_phy_82580:
1582 ret_val = e1000_copper_link_setup_82577(hw);
1585 ret_val = -E1000_ERR_PHY;
1592 ret_val = e1000_setup_copper_link_generic(hw);
1598 * e1000_setup_serdes_link_82575 - Setup link for serdes
1599 * @hw: pointer to the HW structure
1601 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1602 * used on copper connections where the serialized gigabit media independent
1603 * interface (sgmii), or serdes fiber is being used. Configures the link
1604 * for auto-negotiation or forces speed/duplex.
1606 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1608 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1610 s32 ret_val = E1000_SUCCESS;
1613 DEBUGFUNC("e1000_setup_serdes_link_82575");
1615 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1616 !e1000_sgmii_active_82575(hw))
1620 * On the 82575, SerDes loopback mode persists until it is
1621 * explicitly turned off or a power cycle is performed. A read to
1622 * the register does not indicate its status. Therefore, we ensure
1623 * loopback mode is disabled during initialization.
1625 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1627 /* power on the sfp cage if present */
1628 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1629 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1630 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1632 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1633 ctrl_reg |= E1000_CTRL_SLU;
1635 /* set both sw defined pins on 82575/82576*/
1636 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1637 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1639 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1641 /* default pcs_autoneg to the same setting as mac autoneg */
1642 pcs_autoneg = hw->mac.autoneg;
1644 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1645 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1646 /* sgmii mode lets the phy handle forcing speed/duplex */
1648 /* autoneg time out should be disabled for SGMII mode */
1649 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1651 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1652 /* disable PCS autoneg and support parallel detect only */
1653 pcs_autoneg = false;
1654 /* fall through to default case */
1656 if (hw->mac.type == e1000_82575 ||
1657 hw->mac.type == e1000_82576) {
1658 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1660 DEBUGOUT("NVM Read Error\n");
1664 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1665 pcs_autoneg = false;
1669 * non-SGMII modes only supports a speed of 1000/Full for the
1670 * link so it is best to just force the MAC and let the pcs
1671 * link either autoneg or be forced to 1000/Full
1673 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1674 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1676 /* set speed of 1000/Full if speed/duplex is forced */
1677 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1681 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1684 * New SerDes mode allows for forcing speed or autonegotiating speed
1685 * at 1gb. Autoneg should be default set by most drivers. This is the
1686 * mode that will be compatible with older link partners and switches.
1687 * However, both are supported by the hardware and some drivers/tools.
1689 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1690 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1693 /* Set PCS register for autoneg */
1694 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1695 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1697 /* Disable force flow control for autoneg */
1698 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1700 /* Configure flow control advertisement for autoneg */
1701 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1702 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1704 switch (hw->fc.requested_mode) {
1706 case e1000_fc_rx_pause:
1707 anadv_reg |= E1000_TXCW_ASM_DIR;
1708 anadv_reg |= E1000_TXCW_PAUSE;
1710 case e1000_fc_tx_pause:
1711 anadv_reg |= E1000_TXCW_ASM_DIR;
1717 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1719 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1721 /* Set PCS register for forced link */
1722 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1724 /* Force flow control for forced link */
1725 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1727 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1730 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1732 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1733 e1000_force_mac_fc_generic(hw);
1739 * e1000_get_media_type_82575 - derives current media type.
1740 * @hw: pointer to the HW structure
1742 * The media type is chosen reflecting few settings.
1743 * The following are taken into account:
1744 * - link mode set in the current port Init Control Word #3
1745 * - current link mode settings in CSR register
1746 * - MDIO vs. I2C PHY control interface chosen
1747 * - SFP module media type
1749 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1751 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1752 s32 ret_val = E1000_SUCCESS;
1756 /* Set internal phy as default */
1757 dev_spec->sgmii_active = false;
1758 dev_spec->module_plugged = false;
1760 /* Get CSR setting */
1761 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1763 /* extract link mode setting */
1764 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1766 switch (link_mode) {
1767 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1768 hw->phy.media_type = e1000_media_type_internal_serdes;
1770 case E1000_CTRL_EXT_LINK_MODE_GMII:
1771 hw->phy.media_type = e1000_media_type_copper;
1773 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1774 /* Get phy control interface type set (MDIO vs. I2C)*/
1775 if (e1000_sgmii_uses_mdio_82575(hw)) {
1776 hw->phy.media_type = e1000_media_type_copper;
1777 dev_spec->sgmii_active = true;
1780 /* fall through for I2C based SGMII */
1781 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1782 /* read media type from SFP EEPROM */
1783 ret_val = e1000_set_sfp_media_type_82575(hw);
1784 if ((ret_val != E1000_SUCCESS) ||
1785 (hw->phy.media_type == e1000_media_type_unknown)) {
1787 * If media type was not identified then return media
1788 * type defined by the CTRL_EXT settings.
1790 hw->phy.media_type = e1000_media_type_internal_serdes;
1792 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1793 hw->phy.media_type = e1000_media_type_copper;
1794 dev_spec->sgmii_active = true;
1800 /* do not change link mode for 100BaseFX */
1801 if (dev_spec->eth_flags.e100_base_fx)
1804 /* change current link mode setting */
1805 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1807 if (hw->phy.media_type == e1000_media_type_copper)
1808 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1810 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1812 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1821 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1822 * @hw: pointer to the HW structure
1824 * The media type is chosen based on SFP module.
1825 * compatibility flags retrieved from SFP ID EEPROM.
1827 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1829 s32 ret_val = E1000_ERR_CONFIG;
1831 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1832 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1833 u8 tranceiver_type = 0;
1836 /* Turn I2C interface ON and power on sfp cage */
1837 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1838 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1839 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1841 E1000_WRITE_FLUSH(hw);
1843 /* Read SFP module data */
1845 ret_val = e1000_read_sfp_data_byte(hw,
1846 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1848 if (ret_val == E1000_SUCCESS)
1853 if (ret_val != E1000_SUCCESS)
1856 ret_val = e1000_read_sfp_data_byte(hw,
1857 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1859 if (ret_val != E1000_SUCCESS)
1862 /* Check if there is some SFP module plugged and powered */
1863 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1864 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1865 dev_spec->module_plugged = true;
1866 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1867 hw->phy.media_type = e1000_media_type_internal_serdes;
1868 } else if (eth_flags->e100_base_fx) {
1869 dev_spec->sgmii_active = true;
1870 hw->phy.media_type = e1000_media_type_internal_serdes;
1871 } else if (eth_flags->e1000_base_t) {
1872 dev_spec->sgmii_active = true;
1873 hw->phy.media_type = e1000_media_type_copper;
1875 hw->phy.media_type = e1000_media_type_unknown;
1876 DEBUGOUT("PHY module has not been recognized\n");
1880 hw->phy.media_type = e1000_media_type_unknown;
1882 ret_val = E1000_SUCCESS;
1884 /* Restore I2C interface setting */
1885 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1890 * e1000_valid_led_default_82575 - Verify a valid default LED config
1891 * @hw: pointer to the HW structure
1892 * @data: pointer to the NVM (EEPROM)
1894 * Read the EEPROM for the current default LED configuration. If the
1895 * LED configuration is not valid, set to a valid LED configuration.
1897 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1901 DEBUGFUNC("e1000_valid_led_default_82575");
1903 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1905 DEBUGOUT("NVM Read Error\n");
1909 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1910 switch (hw->phy.media_type) {
1911 case e1000_media_type_internal_serdes:
1912 *data = ID_LED_DEFAULT_82575_SERDES;
1914 case e1000_media_type_copper:
1916 *data = ID_LED_DEFAULT;
1925 * e1000_sgmii_active_82575 - Return sgmii state
1926 * @hw: pointer to the HW structure
1928 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1929 * which can be enabled for use in the embedded applications. Simply
1930 * return the current state of the sgmii interface.
1932 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1934 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1935 return dev_spec->sgmii_active;
1939 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1940 * @hw: pointer to the HW structure
1942 * Inits recommended HW defaults after a reset when there is no EEPROM
1943 * detected. This is only for the 82575.
1945 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1947 DEBUGFUNC("e1000_reset_init_script_82575");
1949 if (hw->mac.type == e1000_82575) {
1950 DEBUGOUT("Running reset init script for 82575\n");
1951 /* SerDes configuration via SERDESCTRL */
1952 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1953 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1954 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1955 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1957 /* CCM configuration via CCMCTL register */
1958 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1959 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1961 /* PCIe lanes configuration */
1962 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1963 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1964 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1965 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1967 /* PCIe PLL Configuration */
1968 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1969 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1970 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1973 return E1000_SUCCESS;
1977 * e1000_read_mac_addr_82575 - Read device MAC address
1978 * @hw: pointer to the HW structure
1980 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1984 DEBUGFUNC("e1000_read_mac_addr_82575");
1987 * If there's an alternate MAC address place it in RAR0
1988 * so that it will override the Si installed default perm
1991 ret_val = e1000_check_alt_mac_addr_generic(hw);
1995 ret_val = e1000_read_mac_addr_generic(hw);
2002 * e1000_config_collision_dist_82575 - Configure collision distance
2003 * @hw: pointer to the HW structure
2005 * Configures the collision distance to the default value and is used
2006 * during link setup.
2008 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2012 DEBUGFUNC("e1000_config_collision_dist_82575");
2014 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2016 tctl_ext &= ~E1000_TCTL_EXT_COLD;
2017 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2019 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2020 E1000_WRITE_FLUSH(hw);
2024 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2025 * @hw: pointer to the HW structure
2027 * In the case of a PHY power down to save power, or to turn off link during a
2028 * driver unload, or wake on lan is not enabled, remove the link.
2030 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2032 struct e1000_phy_info *phy = &hw->phy;
2034 if (!(phy->ops.check_reset_block))
2037 /* If the management interface is not enabled, then power down */
2038 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2039 e1000_power_down_phy_copper(hw);
2045 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2046 * @hw: pointer to the HW structure
2048 * Clears the hardware counters by reading the counter registers.
2050 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2052 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2054 e1000_clear_hw_cntrs_base_generic(hw);
2056 E1000_READ_REG(hw, E1000_PRC64);
2057 E1000_READ_REG(hw, E1000_PRC127);
2058 E1000_READ_REG(hw, E1000_PRC255);
2059 E1000_READ_REG(hw, E1000_PRC511);
2060 E1000_READ_REG(hw, E1000_PRC1023);
2061 E1000_READ_REG(hw, E1000_PRC1522);
2062 E1000_READ_REG(hw, E1000_PTC64);
2063 E1000_READ_REG(hw, E1000_PTC127);
2064 E1000_READ_REG(hw, E1000_PTC255);
2065 E1000_READ_REG(hw, E1000_PTC511);
2066 E1000_READ_REG(hw, E1000_PTC1023);
2067 E1000_READ_REG(hw, E1000_PTC1522);
2069 E1000_READ_REG(hw, E1000_ALGNERRC);
2070 E1000_READ_REG(hw, E1000_RXERRC);
2071 E1000_READ_REG(hw, E1000_TNCRS);
2072 E1000_READ_REG(hw, E1000_CEXTERR);
2073 E1000_READ_REG(hw, E1000_TSCTC);
2074 E1000_READ_REG(hw, E1000_TSCTFC);
2076 E1000_READ_REG(hw, E1000_MGTPRC);
2077 E1000_READ_REG(hw, E1000_MGTPDC);
2078 E1000_READ_REG(hw, E1000_MGTPTC);
2080 E1000_READ_REG(hw, E1000_IAC);
2081 E1000_READ_REG(hw, E1000_ICRXOC);
2083 E1000_READ_REG(hw, E1000_ICRXPTC);
2084 E1000_READ_REG(hw, E1000_ICRXATC);
2085 E1000_READ_REG(hw, E1000_ICTXPTC);
2086 E1000_READ_REG(hw, E1000_ICTXATC);
2087 E1000_READ_REG(hw, E1000_ICTXQEC);
2088 E1000_READ_REG(hw, E1000_ICTXQMTC);
2089 E1000_READ_REG(hw, E1000_ICRXDMTC);
2091 E1000_READ_REG(hw, E1000_CBTMPC);
2092 E1000_READ_REG(hw, E1000_HTDPMC);
2093 E1000_READ_REG(hw, E1000_CBRMPC);
2094 E1000_READ_REG(hw, E1000_RPTHC);
2095 E1000_READ_REG(hw, E1000_HGPTC);
2096 E1000_READ_REG(hw, E1000_HTCBDPC);
2097 E1000_READ_REG(hw, E1000_HGORCL);
2098 E1000_READ_REG(hw, E1000_HGORCH);
2099 E1000_READ_REG(hw, E1000_HGOTCL);
2100 E1000_READ_REG(hw, E1000_HGOTCH);
2101 E1000_READ_REG(hw, E1000_LENERRS);
2103 /* This register should not be read in copper configurations */
2104 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2105 e1000_sgmii_active_82575(hw))
2106 E1000_READ_REG(hw, E1000_SCVPC);
2110 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2111 * @hw: pointer to the HW structure
2113 * After rx enable if managability is enabled then there is likely some
2114 * bad data at the start of the fifo and possibly in the DMA fifo. This
2115 * function clears the fifos and flushes any packets that came in as rx was
2118 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2120 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2123 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2124 if (hw->mac.type != e1000_82575 ||
2125 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2128 /* Disable all Rx queues */
2129 for (i = 0; i < 4; i++) {
2130 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2131 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2132 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2134 /* Poll all queues to verify they have shut down */
2135 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2138 for (i = 0; i < 4; i++)
2139 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2140 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2145 DEBUGOUT("Queue disable timed out after 10ms\n");
2147 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2148 * incoming packets are rejected. Set enable and wait 2ms so that
2149 * any packet that was coming in as RCTL.EN was set is flushed
2151 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2152 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2154 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2155 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2157 rctl = E1000_READ_REG(hw, E1000_RCTL);
2158 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2159 temp_rctl |= E1000_RCTL_LPE;
2161 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2162 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2163 E1000_WRITE_FLUSH(hw);
2166 /* Enable Rx queues that were previously enabled and restore our
2169 for (i = 0; i < 4; i++)
2170 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2171 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2172 E1000_WRITE_FLUSH(hw);
2174 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2175 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2177 /* Flush receive errors generated by workaround */
2178 E1000_READ_REG(hw, E1000_ROC);
2179 E1000_READ_REG(hw, E1000_RNBC);
2180 E1000_READ_REG(hw, E1000_MPC);
2184 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2185 * @hw: pointer to the HW structure
2187 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2188 * however the hardware default for these parts is 500us to 1ms which is less
2189 * than the 10ms recommended by the pci-e spec. To address this we need to
2190 * increase the value to either 10ms to 200ms for capability version 1 config,
2191 * or 16ms to 55ms for version 2.
2193 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2195 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2196 s32 ret_val = E1000_SUCCESS;
2199 /* only take action if timeout value is defaulted to 0 */
2200 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2204 * if capababilities version is type 1 we can write the
2205 * timeout of 10ms to 200ms through the GCR register
2207 if (!(gcr & E1000_GCR_CAP_VER2)) {
2208 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2213 * for version 2 capabilities we need to write the config space
2214 * directly in order to set the completion timeout value for
2217 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2222 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2224 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2227 /* disable completion timeout resend */
2228 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2230 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2235 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2236 * @hw: pointer to the hardware struct
2237 * @enable: state to enter, either enabled or disabled
2238 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2240 * enables/disables L2 switch anti-spoofing functionality.
2242 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2244 u32 reg_val, reg_offset;
2246 switch (hw->mac.type) {
2248 reg_offset = E1000_DTXSWC;
2252 reg_offset = E1000_TXSWC;
2258 reg_val = E1000_READ_REG(hw, reg_offset);
2260 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2261 E1000_DTXSWC_VLAN_SPOOF_MASK);
2262 /* The PF can spoof - it has to in order to
2263 * support emulation mode NICs
2265 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2267 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2268 E1000_DTXSWC_VLAN_SPOOF_MASK);
2270 E1000_WRITE_REG(hw, reg_offset, reg_val);
2274 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2275 * @hw: pointer to the hardware struct
2276 * @enable: state to enter, either enabled or disabled
2278 * enables/disables L2 switch loopback functionality.
2280 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2284 switch (hw->mac.type) {
2286 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2288 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2290 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2291 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2295 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2297 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2299 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2300 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2303 /* Currently no other hardware supports loopback */
2311 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2312 * @hw: pointer to the hardware struct
2313 * @enable: state to enter, either enabled or disabled
2315 * enables/disables replication of packets across multiple pools.
2317 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2319 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2322 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2324 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2326 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2330 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2331 * @hw: pointer to the HW structure
2332 * @offset: register offset to be read
2333 * @data: pointer to the read data
2335 * Reads the MDI control register in the PHY at offset and stores the
2336 * information read to data.
2338 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2342 DEBUGFUNC("e1000_read_phy_reg_82580");
2344 ret_val = hw->phy.ops.acquire(hw);
2348 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2350 hw->phy.ops.release(hw);
2357 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2358 * @hw: pointer to the HW structure
2359 * @offset: register offset to write to
2360 * @data: data to write to register at offset
2362 * Writes data to MDI control register in the PHY at offset.
2364 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2368 DEBUGFUNC("e1000_write_phy_reg_82580");
2370 ret_val = hw->phy.ops.acquire(hw);
2374 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2376 hw->phy.ops.release(hw);
2383 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2384 * @hw: pointer to the HW structure
2386 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2387 * the values found in the EEPROM. This addresses an issue in which these
2388 * bits are not restored from EEPROM after reset.
2390 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2392 s32 ret_val = E1000_SUCCESS;
2396 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2398 if (hw->mac.type != e1000_82580)
2400 if (!e1000_sgmii_active_82575(hw))
2403 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2404 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2407 DEBUGOUT("NVM Read Error\n");
2411 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2412 if (nvm_data & NVM_WORD24_EXT_MDIO)
2413 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2414 if (nvm_data & NVM_WORD24_COM_MDIO)
2415 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2416 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2422 * e1000_reset_hw_82580 - Reset hardware
2423 * @hw: pointer to the HW structure
2425 * This resets function or entire device (all ports, etc.)
2428 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2430 s32 ret_val = E1000_SUCCESS;
2431 /* BH SW mailbox bit in SW_FW_SYNC */
2432 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2434 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2436 DEBUGFUNC("e1000_reset_hw_82580");
2438 hw->dev_spec._82575.global_device_reset = false;
2440 /* 82580 does not reliably do global_device_reset due to hw errata */
2441 if (hw->mac.type == e1000_82580)
2442 global_device_reset = false;
2444 /* Get current control state. */
2445 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2448 * Prevent the PCI-E bus from sticking if there is no TLP connection
2449 * on the last TLP read/write transaction when MAC is reset.
2451 ret_val = e1000_disable_pcie_master_generic(hw);
2453 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2455 DEBUGOUT("Masking off all interrupts\n");
2456 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2457 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2458 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2459 E1000_WRITE_FLUSH(hw);
2463 /* Determine whether or not a global dev reset is requested */
2464 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2466 global_device_reset = false;
2468 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2469 E1000_STAT_DEV_RST_SET))
2470 ctrl |= E1000_CTRL_DEV_RST;
2472 ctrl |= E1000_CTRL_RST;
2474 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2475 E1000_WRITE_FLUSH(hw);
2477 /* Add delay to insure DEV_RST has time to complete */
2478 if (global_device_reset)
2481 ret_val = e1000_get_auto_rd_done_generic(hw);
2484 * When auto config read does not complete, do not
2485 * return with an error. This can happen in situations
2486 * where there is no eeprom and prevents getting link.
2488 DEBUGOUT("Auto Read Done did not complete\n");
2491 /* clear global device reset status bit */
2492 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2494 /* Clear any pending interrupt events. */
2495 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2496 E1000_READ_REG(hw, E1000_ICR);
2498 ret_val = e1000_reset_mdicnfg_82580(hw);
2500 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2502 /* Install any alternate MAC address into RAR0 */
2503 ret_val = e1000_check_alt_mac_addr_generic(hw);
2505 /* Release semaphore */
2506 if (global_device_reset)
2507 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2513 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2514 * @data: data received by reading RXPBS register
2516 * The 82580 uses a table based approach for packet buffer allocation sizes.
2517 * This function converts the retrieved value into the correct table value
2518 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2519 * 0x0 36 72 144 1 2 4 8 16
2520 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2522 u16 e1000_rxpbs_adjust_82580(u32 data)
2526 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2527 ret_val = e1000_82580_rxpbs_table[data];
2533 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2535 * @hw: pointer to the HW structure
2536 * @offset: offset in words of the checksum protected region
2538 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2539 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2541 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2543 s32 ret_val = E1000_SUCCESS;
2547 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2549 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2550 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2552 DEBUGOUT("NVM Read Error\n");
2555 checksum += nvm_data;
2558 if (checksum != (u16) NVM_SUM) {
2559 DEBUGOUT("NVM Checksum Invalid\n");
2560 ret_val = -E1000_ERR_NVM;
2569 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2571 * @hw: pointer to the HW structure
2572 * @offset: offset in words of the checksum protected region
2574 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2575 * up to the checksum. Then calculates the EEPROM checksum and writes the
2576 * value to the EEPROM.
2578 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2584 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2586 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2587 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2589 DEBUGOUT("NVM Read Error while updating checksum.\n");
2592 checksum += nvm_data;
2594 checksum = (u16) NVM_SUM - checksum;
2595 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2598 DEBUGOUT("NVM Write Error while updating checksum.\n");
2605 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2606 * @hw: pointer to the HW structure
2608 * Calculates the EEPROM section checksum by reading/adding each word of
2609 * the EEPROM and then verifies that the sum of the EEPROM is
2612 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2615 u16 eeprom_regions_count = 1;
2619 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2621 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2623 DEBUGOUT("NVM Read Error\n");
2627 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2628 /* if chekcsums compatibility bit is set validate checksums
2629 * for all 4 ports. */
2630 eeprom_regions_count = 4;
2633 for (j = 0; j < eeprom_regions_count; j++) {
2634 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2635 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2637 if (ret_val != E1000_SUCCESS)
2646 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2647 * @hw: pointer to the HW structure
2649 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2650 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2651 * checksum and writes the value to the EEPROM.
2653 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2659 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2661 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2663 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2667 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2668 /* set compatibility bit to validate checksums appropriately */
2669 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2670 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2673 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2678 for (j = 0; j < 4; j++) {
2679 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2680 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2690 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2691 * @hw: pointer to the HW structure
2693 * Calculates the EEPROM section checksum by reading/adding each word of
2694 * the EEPROM and then verifies that the sum of the EEPROM is
2697 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2699 s32 ret_val = E1000_SUCCESS;
2703 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2705 for (j = 0; j < 4; j++) {
2706 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2707 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2709 if (ret_val != E1000_SUCCESS)
2718 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2719 * @hw: pointer to the HW structure
2721 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2722 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2723 * checksum and writes the value to the EEPROM.
2725 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2727 s32 ret_val = E1000_SUCCESS;
2731 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2733 for (j = 0; j < 4; j++) {
2734 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2735 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2736 if (ret_val != E1000_SUCCESS)
2745 * __e1000_access_emi_reg - Read/write EMI register
2746 * @hw: pointer to the HW structure
2747 * @addr: EMI address to program
2748 * @data: pointer to value to read/write from/to the EMI address
2749 * @read: boolean flag to indicate read or write
2751 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2752 u16 *data, bool read)
2756 DEBUGFUNC("__e1000_access_emi_reg");
2758 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2763 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2765 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2771 * e1000_read_emi_reg - Read Extended Management Interface register
2772 * @hw: pointer to the HW structure
2773 * @addr: EMI address to program
2774 * @data: value to be read from the EMI address
2776 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2778 DEBUGFUNC("e1000_read_emi_reg");
2780 return __e1000_access_emi_reg(hw, addr, data, true);
2784 * e1000_set_eee_i350 - Enable/disable EEE support
2785 * @hw: pointer to the HW structure
2787 * Enable/disable EEE based on setting in dev_spec structure.
2790 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2792 s32 ret_val = E1000_SUCCESS;
2795 DEBUGFUNC("e1000_set_eee_i350");
2797 if ((hw->mac.type < e1000_i350) ||
2798 (hw->phy.media_type != e1000_media_type_copper))
2800 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2801 eeer = E1000_READ_REG(hw, E1000_EEER);
2803 /* enable or disable per user setting */
2804 if (!(hw->dev_spec._82575.eee_disable)) {
2805 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2807 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2808 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2811 /* This bit should not be set in normal operation. */
2812 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2813 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2815 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2816 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2819 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2820 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2821 E1000_READ_REG(hw, E1000_IPCNFG);
2822 E1000_READ_REG(hw, E1000_EEER);
2829 * e1000_set_eee_i354 - Enable/disable EEE support
2830 * @hw: pointer to the HW structure
2832 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2835 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2837 struct e1000_phy_info *phy = &hw->phy;
2838 s32 ret_val = E1000_SUCCESS;
2841 DEBUGFUNC("e1000_set_eee_i354");
2843 if ((hw->phy.media_type != e1000_media_type_copper) ||
2844 ((phy->id != M88E1543_E_PHY_ID) &&
2845 (phy->id != M88E1512_E_PHY_ID)))
2848 if (!hw->dev_spec._82575.eee_disable) {
2849 /* Switch to PHY page 18. */
2850 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2854 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2859 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2865 /* Return the PHY to page 0. */
2866 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2870 /* Turn on EEE advertisement. */
2871 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2872 E1000_EEE_ADV_DEV_I354,
2877 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2878 E1000_EEE_ADV_1000_SUPPORTED;
2879 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2880 E1000_EEE_ADV_DEV_I354,
2883 /* Turn off EEE advertisement. */
2884 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2885 E1000_EEE_ADV_DEV_I354,
2890 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2891 E1000_EEE_ADV_1000_SUPPORTED);
2892 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2893 E1000_EEE_ADV_DEV_I354,
2902 * e1000_get_eee_status_i354 - Get EEE status
2903 * @hw: pointer to the HW structure
2904 * @status: EEE status
2906 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2909 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2911 struct e1000_phy_info *phy = &hw->phy;
2912 s32 ret_val = E1000_SUCCESS;
2915 DEBUGFUNC("e1000_get_eee_status_i354");
2917 /* Check if EEE is supported on this device. */
2918 if ((hw->phy.media_type != e1000_media_type_copper) ||
2919 ((phy->id != M88E1543_E_PHY_ID) &&
2920 (phy->id != M88E1512_E_PHY_ID)))
2923 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2924 E1000_PCS_STATUS_DEV_I354,
2929 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2930 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2936 /* Due to a hw errata, if the host tries to configure the VFTA register
2937 * while performing queries from the BMC or DMA, then the VFTA in some
2938 * cases won't be written.
2942 * e1000_clear_vfta_i350 - Clear VLAN filter table
2943 * @hw: pointer to the HW structure
2945 * Clears the register array which contains the VLAN filter table by
2946 * setting all the values to 0.
2948 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2953 DEBUGFUNC("e1000_clear_vfta_350");
2955 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2956 for (i = 0; i < 10; i++)
2957 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2959 E1000_WRITE_FLUSH(hw);
2964 * e1000_write_vfta_i350 - Write value to VLAN filter table
2965 * @hw: pointer to the HW structure
2966 * @offset: register offset in VLAN filter table
2967 * @value: register value written to VLAN filter table
2969 * Writes value at the given offset in the register array which stores
2970 * the VLAN filter table.
2972 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2976 DEBUGFUNC("e1000_write_vfta_350");
2978 for (i = 0; i < 10; i++)
2979 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2981 E1000_WRITE_FLUSH(hw);
2986 * e1000_set_i2c_bb - Enable I2C bit-bang
2987 * @hw: pointer to the HW structure
2989 * Enable I2C bit-bang interface
2992 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2994 s32 ret_val = E1000_SUCCESS;
2995 u32 ctrl_ext, i2cparams;
2997 DEBUGFUNC("e1000_set_i2c_bb");
2999 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3000 ctrl_ext |= E1000_CTRL_I2C_ENA;
3001 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3002 E1000_WRITE_FLUSH(hw);
3004 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3005 i2cparams |= E1000_I2CBB_EN;
3006 i2cparams |= E1000_I2C_DATA_OE_N;
3007 i2cparams |= E1000_I2C_CLK_OE_N;
3008 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3009 E1000_WRITE_FLUSH(hw);
3015 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3016 * @hw: pointer to hardware structure
3017 * @byte_offset: byte offset to read
3018 * @dev_addr: device address
3021 * Performs byte read operation over I2C interface at
3022 * a specified device address.
3024 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3025 u8 dev_addr, u8 *data)
3027 s32 status = E1000_SUCCESS;
3034 DEBUGFUNC("e1000_read_i2c_byte_generic");
3036 swfw_mask = E1000_SWFW_PHY0_SM;
3039 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3041 status = E1000_ERR_SWFW_SYNC;
3045 e1000_i2c_start(hw);
3047 /* Device Address and write indication */
3048 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3049 if (status != E1000_SUCCESS)
3052 status = e1000_get_i2c_ack(hw);
3053 if (status != E1000_SUCCESS)
3056 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3057 if (status != E1000_SUCCESS)
3060 status = e1000_get_i2c_ack(hw);
3061 if (status != E1000_SUCCESS)
3064 e1000_i2c_start(hw);
3066 /* Device Address and read indication */
3067 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3068 if (status != E1000_SUCCESS)
3071 status = e1000_get_i2c_ack(hw);
3072 if (status != E1000_SUCCESS)
3075 status = e1000_clock_in_i2c_byte(hw, data);
3076 if (status != E1000_SUCCESS)
3079 status = e1000_clock_out_i2c_bit(hw, nack);
3080 if (status != E1000_SUCCESS)
3087 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3089 e1000_i2c_bus_clear(hw);
3091 if (retry < max_retry)
3092 DEBUGOUT("I2C byte read error - Retrying.\n");
3094 DEBUGOUT("I2C byte read error.\n");
3096 } while (retry < max_retry);
3098 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3106 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3107 * @hw: pointer to hardware structure
3108 * @byte_offset: byte offset to write
3109 * @dev_addr: device address
3110 * @data: value to write
3112 * Performs byte write operation over I2C interface at
3113 * a specified device address.
3115 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3116 u8 dev_addr, u8 data)
3118 s32 status = E1000_SUCCESS;
3123 DEBUGFUNC("e1000_write_i2c_byte_generic");
3125 swfw_mask = E1000_SWFW_PHY0_SM;
3127 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3128 status = E1000_ERR_SWFW_SYNC;
3129 goto write_byte_out;
3133 e1000_i2c_start(hw);
3135 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3136 if (status != E1000_SUCCESS)
3139 status = e1000_get_i2c_ack(hw);
3140 if (status != E1000_SUCCESS)
3143 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3144 if (status != E1000_SUCCESS)
3147 status = e1000_get_i2c_ack(hw);
3148 if (status != E1000_SUCCESS)
3151 status = e1000_clock_out_i2c_byte(hw, data);
3152 if (status != E1000_SUCCESS)
3155 status = e1000_get_i2c_ack(hw);
3156 if (status != E1000_SUCCESS)
3163 e1000_i2c_bus_clear(hw);
3165 if (retry < max_retry)
3166 DEBUGOUT("I2C byte write error - Retrying.\n");
3168 DEBUGOUT("I2C byte write error.\n");
3169 } while (retry < max_retry);
3171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3179 * e1000_i2c_start - Sets I2C start condition
3180 * @hw: pointer to hardware structure
3182 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3184 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3186 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3188 DEBUGFUNC("e1000_i2c_start");
3190 /* Start condition must begin with data and clock high */
3191 e1000_set_i2c_data(hw, &i2cctl, 1);
3192 e1000_raise_i2c_clk(hw, &i2cctl);
3194 /* Setup time for start condition (4.7us) */
3195 usec_delay(E1000_I2C_T_SU_STA);
3197 e1000_set_i2c_data(hw, &i2cctl, 0);
3199 /* Hold time for start condition (4us) */
3200 usec_delay(E1000_I2C_T_HD_STA);
3202 e1000_lower_i2c_clk(hw, &i2cctl);
3204 /* Minimum low period of clock is 4.7 us */
3205 usec_delay(E1000_I2C_T_LOW);
3210 * e1000_i2c_stop - Sets I2C stop condition
3211 * @hw: pointer to hardware structure
3213 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3215 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3217 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3219 DEBUGFUNC("e1000_i2c_stop");
3221 /* Stop condition must begin with data low and clock high */
3222 e1000_set_i2c_data(hw, &i2cctl, 0);
3223 e1000_raise_i2c_clk(hw, &i2cctl);
3225 /* Setup time for stop condition (4us) */
3226 usec_delay(E1000_I2C_T_SU_STO);
3228 e1000_set_i2c_data(hw, &i2cctl, 1);
3230 /* bus free time between stop and start (4.7us)*/
3231 usec_delay(E1000_I2C_T_BUF);
3235 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3236 * @hw: pointer to hardware structure
3237 * @data: data byte to clock in
3239 * Clocks in one byte data via I2C data/clock
3241 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3246 DEBUGFUNC("e1000_clock_in_i2c_byte");
3249 for (i = 7; i >= 0; i--) {
3250 e1000_clock_in_i2c_bit(hw, &bit);
3254 return E1000_SUCCESS;
3258 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3259 * @hw: pointer to hardware structure
3260 * @data: data byte clocked out
3262 * Clocks out one byte data via I2C data/clock
3264 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3266 s32 status = E1000_SUCCESS;
3271 DEBUGFUNC("e1000_clock_out_i2c_byte");
3273 for (i = 7; i >= 0; i--) {
3274 bit = (data >> i) & 0x1;
3275 status = e1000_clock_out_i2c_bit(hw, bit);
3277 if (status != E1000_SUCCESS)
3281 /* Release SDA line (set high) */
3282 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3284 i2cctl |= E1000_I2C_DATA_OE_N;
3285 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3286 E1000_WRITE_FLUSH(hw);
3292 * e1000_get_i2c_ack - Polls for I2C ACK
3293 * @hw: pointer to hardware structure
3295 * Clocks in/out one bit via I2C data/clock
3297 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3299 s32 status = E1000_SUCCESS;
3301 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3305 DEBUGFUNC("e1000_get_i2c_ack");
3307 e1000_raise_i2c_clk(hw, &i2cctl);
3309 /* Minimum high period of clock is 4us */
3310 usec_delay(E1000_I2C_T_HIGH);
3312 /* Wait until SCL returns high */
3313 for (i = 0; i < timeout; i++) {
3315 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3316 if (i2cctl & E1000_I2C_CLK_IN)
3319 if (!(i2cctl & E1000_I2C_CLK_IN))
3320 return E1000_ERR_I2C;
3322 ack = e1000_get_i2c_data(&i2cctl);
3324 DEBUGOUT("I2C ack was not received.\n");
3325 status = E1000_ERR_I2C;
3328 e1000_lower_i2c_clk(hw, &i2cctl);
3330 /* Minimum low period of clock is 4.7 us */
3331 usec_delay(E1000_I2C_T_LOW);
3337 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3338 * @hw: pointer to hardware structure
3339 * @data: read data value
3341 * Clocks in one bit via I2C data/clock
3343 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3345 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3347 DEBUGFUNC("e1000_clock_in_i2c_bit");
3349 e1000_raise_i2c_clk(hw, &i2cctl);
3351 /* Minimum high period of clock is 4us */
3352 usec_delay(E1000_I2C_T_HIGH);
3354 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3355 *data = e1000_get_i2c_data(&i2cctl);
3357 e1000_lower_i2c_clk(hw, &i2cctl);
3359 /* Minimum low period of clock is 4.7 us */
3360 usec_delay(E1000_I2C_T_LOW);
3362 return E1000_SUCCESS;
3366 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3367 * @hw: pointer to hardware structure
3368 * @data: data value to write
3370 * Clocks out one bit via I2C data/clock
3372 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3375 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3377 DEBUGFUNC("e1000_clock_out_i2c_bit");
3379 status = e1000_set_i2c_data(hw, &i2cctl, data);
3380 if (status == E1000_SUCCESS) {
3381 e1000_raise_i2c_clk(hw, &i2cctl);
3383 /* Minimum high period of clock is 4us */
3384 usec_delay(E1000_I2C_T_HIGH);
3386 e1000_lower_i2c_clk(hw, &i2cctl);
3388 /* Minimum low period of clock is 4.7 us.
3389 * This also takes care of the data hold time.
3391 usec_delay(E1000_I2C_T_LOW);
3393 status = E1000_ERR_I2C;
3394 DEBUGOUT1("I2C data was not set to %X\n", data);
3400 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3401 * @hw: pointer to hardware structure
3402 * @i2cctl: Current value of I2CCTL register
3404 * Raises the I2C clock line '0'->'1'
3406 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3408 DEBUGFUNC("e1000_raise_i2c_clk");
3410 *i2cctl |= E1000_I2C_CLK_OUT;
3411 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3412 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3413 E1000_WRITE_FLUSH(hw);
3415 /* SCL rise time (1000ns) */
3416 usec_delay(E1000_I2C_T_RISE);
3420 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3421 * @hw: pointer to hardware structure
3422 * @i2cctl: Current value of I2CCTL register
3424 * Lowers the I2C clock line '1'->'0'
3426 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3429 DEBUGFUNC("e1000_lower_i2c_clk");
3431 *i2cctl &= ~E1000_I2C_CLK_OUT;
3432 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3433 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3434 E1000_WRITE_FLUSH(hw);
3436 /* SCL fall time (300ns) */
3437 usec_delay(E1000_I2C_T_FALL);
3441 * e1000_set_i2c_data - Sets the I2C data bit
3442 * @hw: pointer to hardware structure
3443 * @i2cctl: Current value of I2CCTL register
3444 * @data: I2C data value (0 or 1) to set
3446 * Sets the I2C data bit
3448 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3450 s32 status = E1000_SUCCESS;
3452 DEBUGFUNC("e1000_set_i2c_data");
3455 *i2cctl |= E1000_I2C_DATA_OUT;
3457 *i2cctl &= ~E1000_I2C_DATA_OUT;
3459 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3460 *i2cctl |= E1000_I2C_CLK_OE_N;
3461 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3462 E1000_WRITE_FLUSH(hw);
3464 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3465 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3467 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3468 if (data != e1000_get_i2c_data(i2cctl)) {
3469 status = E1000_ERR_I2C;
3470 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3477 * e1000_get_i2c_data - Reads the I2C SDA data bit
3478 * @hw: pointer to hardware structure
3479 * @i2cctl: Current value of I2CCTL register
3481 * Returns the I2C data bit value
3483 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3487 DEBUGFUNC("e1000_get_i2c_data");
3489 if (*i2cctl & E1000_I2C_DATA_IN)
3498 * e1000_i2c_bus_clear - Clears the I2C bus
3499 * @hw: pointer to hardware structure
3501 * Clears the I2C bus by sending nine clock pulses.
3502 * Used when data line is stuck low.
3504 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3506 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3509 DEBUGFUNC("e1000_i2c_bus_clear");
3511 e1000_i2c_start(hw);
3513 e1000_set_i2c_data(hw, &i2cctl, 1);
3515 for (i = 0; i < 9; i++) {
3516 e1000_raise_i2c_clk(hw, &i2cctl);
3518 /* Min high period of clock is 4us */
3519 usec_delay(E1000_I2C_T_HIGH);
3521 e1000_lower_i2c_clk(hw, &i2cctl);
3523 /* Min low period of clock is 4.7us*/
3524 usec_delay(E1000_I2C_T_LOW);
3527 e1000_i2c_start(hw);
3529 /* Put the i2c bus back to default state */