1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
37 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
38 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw);
39 STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
43 * @hw: pointer to the HW structure
45 * Setups up the function pointers to no-op functions
47 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
49 struct e1000_mac_info *mac = &hw->mac;
50 DEBUGFUNC("e1000_init_mac_ops_generic");
53 mac->ops.init_params = e1000_null_ops_generic;
54 mac->ops.init_hw = e1000_null_ops_generic;
55 mac->ops.reset_hw = e1000_null_ops_generic;
56 mac->ops.setup_physical_interface = e1000_null_ops_generic;
57 mac->ops.get_bus_info = e1000_null_ops_generic;
58 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
59 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
60 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
61 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
63 mac->ops.cleanup_led = e1000_null_ops_generic;
64 mac->ops.setup_led = e1000_null_ops_generic;
65 mac->ops.blink_led = e1000_null_ops_generic;
66 mac->ops.led_on = e1000_null_ops_generic;
67 mac->ops.led_off = e1000_null_ops_generic;
69 mac->ops.setup_link = e1000_null_ops_generic;
70 mac->ops.get_link_up_info = e1000_null_link_info;
71 mac->ops.check_for_link = e1000_null_ops_generic;
72 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
74 mac->ops.check_mng_mode = e1000_null_mng_mode;
75 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
76 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
77 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
79 mac->ops.update_mc_addr_list = e1000_null_update_mc;
80 mac->ops.clear_vfta = e1000_null_mac_generic;
81 mac->ops.write_vfta = e1000_null_write_vfta;
82 mac->ops.rar_set = e1000_rar_set_generic;
83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
87 * e1000_null_ops_generic - No-op function, returns 0
88 * @hw: pointer to the HW structure
90 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)
92 DEBUGFUNC("e1000_null_ops_generic");
93 UNREFERENCED_1PARAMETER(hw);
98 * e1000_null_mac_generic - No-op function, return void
99 * @hw: pointer to the HW structure
101 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)
103 DEBUGFUNC("e1000_null_mac_generic");
104 UNREFERENCED_1PARAMETER(hw);
109 * e1000_null_link_info - No-op function, return 0
110 * @hw: pointer to the HW structure
112 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,
113 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)
115 DEBUGFUNC("e1000_null_link_info");
116 UNREFERENCED_3PARAMETER(hw, s, d);
117 return E1000_SUCCESS;
121 * e1000_null_mng_mode - No-op function, return false
122 * @hw: pointer to the HW structure
124 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)
126 DEBUGFUNC("e1000_null_mng_mode");
127 UNREFERENCED_1PARAMETER(hw);
132 * e1000_null_update_mc - No-op function, return void
133 * @hw: pointer to the HW structure
135 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,
136 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
138 DEBUGFUNC("e1000_null_update_mc");
139 UNREFERENCED_3PARAMETER(hw, h, a);
144 * e1000_null_write_vfta - No-op function, return void
145 * @hw: pointer to the HW structure
147 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,
148 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)
150 DEBUGFUNC("e1000_null_write_vfta");
151 UNREFERENCED_3PARAMETER(hw, a, b);
156 * e1000_null_rar_set - No-op function, return void
157 * @hw: pointer to the HW structure
159 void e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
160 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)
162 DEBUGFUNC("e1000_null_rar_set");
163 UNREFERENCED_3PARAMETER(hw, h, a);
168 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
169 * @hw: pointer to the HW structure
171 * Determines and stores the system bus information for a particular
172 * network interface. The following bus information is determined and stored:
173 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
175 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
177 struct e1000_mac_info *mac = &hw->mac;
178 struct e1000_bus_info *bus = &hw->bus;
179 u32 status = E1000_READ_REG(hw, E1000_STATUS);
180 s32 ret_val = E1000_SUCCESS;
182 DEBUGFUNC("e1000_get_bus_info_pci_generic");
185 bus->type = (status & E1000_STATUS_PCIX_MODE)
186 ? e1000_bus_type_pcix
187 : e1000_bus_type_pci;
190 if (bus->type == e1000_bus_type_pci) {
191 bus->speed = (status & E1000_STATUS_PCI66)
193 : e1000_bus_speed_33;
195 switch (status & E1000_STATUS_PCIX_SPEED) {
196 case E1000_STATUS_PCIX_SPEED_66:
197 bus->speed = e1000_bus_speed_66;
199 case E1000_STATUS_PCIX_SPEED_100:
200 bus->speed = e1000_bus_speed_100;
202 case E1000_STATUS_PCIX_SPEED_133:
203 bus->speed = e1000_bus_speed_133;
206 bus->speed = e1000_bus_speed_reserved;
212 bus->width = (status & E1000_STATUS_BUS64)
214 : e1000_bus_width_32;
216 /* Which PCI(-X) function? */
217 mac->ops.set_lan_id(hw);
223 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
224 * @hw: pointer to the HW structure
226 * Determines and stores the system bus information for a particular
227 * network interface. The following bus information is determined and stored:
228 * bus speed, bus width, type (PCIe), and PCIe function.
230 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
232 struct e1000_mac_info *mac = &hw->mac;
233 struct e1000_bus_info *bus = &hw->bus;
235 u16 pcie_link_status;
237 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
239 bus->type = e1000_bus_type_pci_express;
241 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
244 bus->width = e1000_bus_width_unknown;
245 bus->speed = e1000_bus_speed_unknown;
247 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
248 case PCIE_LINK_SPEED_2500:
249 bus->speed = e1000_bus_speed_2500;
251 case PCIE_LINK_SPEED_5000:
252 bus->speed = e1000_bus_speed_5000;
255 bus->speed = e1000_bus_speed_unknown;
259 bus->width = (enum e1000_bus_width)((pcie_link_status &
260 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
263 mac->ops.set_lan_id(hw);
265 return E1000_SUCCESS;
269 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
271 * @hw: pointer to the HW structure
273 * Determines the LAN function id by reading memory-mapped registers
274 * and swaps the port value if requested.
276 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
278 struct e1000_bus_info *bus = &hw->bus;
281 /* The status register reports the correct function number
282 * for the device regardless of function swap state.
284 reg = E1000_READ_REG(hw, E1000_STATUS);
285 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
289 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
290 * @hw: pointer to the HW structure
292 * Determines the LAN function id by reading PCI config space.
294 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
296 struct e1000_bus_info *bus = &hw->bus;
300 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
301 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
302 status = E1000_READ_REG(hw, E1000_STATUS);
303 bus->func = (status & E1000_STATUS_FUNC_MASK)
304 >> E1000_STATUS_FUNC_SHIFT;
311 * e1000_set_lan_id_single_port - Set LAN id for a single port device
312 * @hw: pointer to the HW structure
314 * Sets the LAN function id to zero for a single port device.
316 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
318 struct e1000_bus_info *bus = &hw->bus;
324 * e1000_clear_vfta_generic - Clear VLAN filter table
325 * @hw: pointer to the HW structure
327 * Clears the register array which contains the VLAN filter table by
328 * setting all the values to 0.
330 void e1000_clear_vfta_generic(struct e1000_hw *hw)
334 DEBUGFUNC("e1000_clear_vfta_generic");
336 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
337 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
338 E1000_WRITE_FLUSH(hw);
343 * e1000_write_vfta_generic - Write value to VLAN filter table
344 * @hw: pointer to the HW structure
345 * @offset: register offset in VLAN filter table
346 * @value: register value written to VLAN filter table
348 * Writes value at the given offset in the register array which stores
349 * the VLAN filter table.
351 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
353 DEBUGFUNC("e1000_write_vfta_generic");
355 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
356 E1000_WRITE_FLUSH(hw);
360 * e1000_init_rx_addrs_generic - Initialize receive address's
361 * @hw: pointer to the HW structure
362 * @rar_count: receive address registers
364 * Setup the receive address registers by setting the base receive address
365 * register to the devices MAC address and clearing all the other receive
366 * address registers to 0.
368 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
371 u8 mac_addr[ETH_ADDR_LEN] = {0};
373 DEBUGFUNC("e1000_init_rx_addrs_generic");
375 /* Setup the receive address */
376 DEBUGOUT("Programming MAC Address into RAR[0]\n");
378 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
380 /* Zero out the other (rar_entry_count - 1) receive addresses */
381 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
382 for (i = 1; i < rar_count; i++)
383 hw->mac.ops.rar_set(hw, mac_addr, i);
387 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
388 * @hw: pointer to the HW structure
390 * Checks the nvm for an alternate MAC address. An alternate MAC address
391 * can be setup by pre-boot software and must be treated like a permanent
392 * address and must override the actual permanent MAC address. If an
393 * alternate MAC address is found it is programmed into RAR0, replacing
394 * the permanent address that was installed into RAR0 by the Si on reset.
395 * This function will return SUCCESS unless it encounters an error while
396 * reading the EEPROM.
398 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
402 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
403 u8 alt_mac_addr[ETH_ADDR_LEN];
405 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
407 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
411 /* not supported on older hardware or 82573 */
412 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
413 return E1000_SUCCESS;
415 /* Alternate MAC address is handled by the option ROM for 82580
416 * and newer. SW support not required.
418 if (hw->mac.type >= e1000_82580)
419 return E1000_SUCCESS;
421 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
422 &nvm_alt_mac_addr_offset);
424 DEBUGOUT("NVM Read Error\n");
428 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
429 (nvm_alt_mac_addr_offset == 0x0000))
430 /* There is no Alternate MAC Address */
431 return E1000_SUCCESS;
433 if (hw->bus.func == E1000_FUNC_1)
434 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
435 if (hw->bus.func == E1000_FUNC_2)
436 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
438 if (hw->bus.func == E1000_FUNC_3)
439 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
440 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
441 offset = nvm_alt_mac_addr_offset + (i >> 1);
442 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
444 DEBUGOUT("NVM Read Error\n");
448 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
449 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
452 /* if multicast bit is set, the alternate address will not be used */
453 if (alt_mac_addr[0] & 0x01) {
454 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
455 return E1000_SUCCESS;
458 /* We have a valid alternate MAC address, and we want to treat it the
459 * same as the normal permanent MAC address stored by the HW into the
460 * RAR. Do this by mapping this address into RAR0.
462 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
464 return E1000_SUCCESS;
468 * e1000_rar_set_generic - Set receive address register
469 * @hw: pointer to the HW structure
470 * @addr: pointer to the receive address
471 * @index: receive address array register
473 * Sets the receive address array register at index to the address passed
476 STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
478 u32 rar_low, rar_high;
480 DEBUGFUNC("e1000_rar_set_generic");
482 /* HW expects these in little endian so we reverse the byte order
483 * from network order (big endian) to little endian
485 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
486 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
488 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
490 /* If MAC address zero, no need to set the AV bit */
491 if (rar_low || rar_high)
492 rar_high |= E1000_RAH_AV;
494 /* Some bridges will combine consecutive 32-bit writes into
495 * a single burst write, which will malfunction on some parts.
496 * The flushes avoid this.
498 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
499 E1000_WRITE_FLUSH(hw);
500 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
501 E1000_WRITE_FLUSH(hw);
505 * e1000_hash_mc_addr_generic - Generate a multicast hash value
506 * @hw: pointer to the HW structure
507 * @mc_addr: pointer to a multicast address
509 * Generates a multicast address hash value which is used to determine
510 * the multicast filter table array address and new table value.
512 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
514 u32 hash_value, hash_mask;
517 DEBUGFUNC("e1000_hash_mc_addr_generic");
519 /* Register count multiplied by bits per register */
520 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
522 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
523 * where 0xFF would still fall within the hash mask.
525 while (hash_mask >> bit_shift != 0xFF)
528 /* The portion of the address that is used for the hash table
529 * is determined by the mc_filter_type setting.
530 * The algorithm is such that there is a total of 8 bits of shifting.
531 * The bit_shift for a mc_filter_type of 0 represents the number of
532 * left-shifts where the MSB of mc_addr[5] would still fall within
533 * the hash_mask. Case 0 does this exactly. Since there are a total
534 * of 8 bits of shifting, then mc_addr[4] will shift right the
535 * remaining number of bits. Thus 8 - bit_shift. The rest of the
536 * cases are a variation of this algorithm...essentially raising the
537 * number of bits to shift mc_addr[5] left, while still keeping the
538 * 8-bit shifting total.
540 * For example, given the following Destination MAC Address and an
541 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
542 * we can see that the bit_shift for case 0 is 4. These are the hash
543 * values resulting from each mc_filter_type...
544 * [0] [1] [2] [3] [4] [5]
548 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
549 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
550 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
551 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
553 switch (hw->mac.mc_filter_type) {
568 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
569 (((u16) mc_addr[5]) << bit_shift)));
575 * e1000_update_mc_addr_list_generic - Update Multicast addresses
576 * @hw: pointer to the HW structure
577 * @mc_addr_list: array of multicast addresses to program
578 * @mc_addr_count: number of multicast addresses to program
580 * Updates entire Multicast Table Array.
581 * The caller must have a packed mc_addr_list of multicast addresses.
583 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
584 u8 *mc_addr_list, u32 mc_addr_count)
586 u32 hash_value, hash_bit, hash_reg;
589 DEBUGFUNC("e1000_update_mc_addr_list_generic");
591 /* clear mta_shadow */
592 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
594 /* update mta_shadow from mc_addr_list */
595 for (i = 0; (u32) i < mc_addr_count; i++) {
596 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
598 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
599 hash_bit = hash_value & 0x1F;
601 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
602 mc_addr_list += (ETH_ADDR_LEN);
605 /* replace the entire MTA table */
606 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
607 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
608 E1000_WRITE_FLUSH(hw);
612 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
613 * @hw: pointer to the HW structure
615 * In certain situations, a system BIOS may report that the PCIx maximum
616 * memory read byte count (MMRBC) value is higher than than the actual
617 * value. We check the PCIx command register with the current PCIx status
620 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
624 u16 pcix_stat_hi_word;
627 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
629 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
630 if (hw->bus.type != e1000_bus_type_pcix)
633 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
634 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
635 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
636 PCIX_COMMAND_MMRBC_SHIFT;
637 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
638 PCIX_STATUS_HI_MMRBC_SHIFT;
639 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
640 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
641 if (cmd_mmrbc > stat_mmrbc) {
642 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
643 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
644 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
649 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
650 * @hw: pointer to the HW structure
652 * Clears the base hardware counters by reading the counter registers.
654 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
656 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
658 E1000_READ_REG(hw, E1000_CRCERRS);
659 E1000_READ_REG(hw, E1000_SYMERRS);
660 E1000_READ_REG(hw, E1000_MPC);
661 E1000_READ_REG(hw, E1000_SCC);
662 E1000_READ_REG(hw, E1000_ECOL);
663 E1000_READ_REG(hw, E1000_MCC);
664 E1000_READ_REG(hw, E1000_LATECOL);
665 E1000_READ_REG(hw, E1000_COLC);
666 E1000_READ_REG(hw, E1000_DC);
667 E1000_READ_REG(hw, E1000_SEC);
668 E1000_READ_REG(hw, E1000_RLEC);
669 E1000_READ_REG(hw, E1000_XONRXC);
670 E1000_READ_REG(hw, E1000_XONTXC);
671 E1000_READ_REG(hw, E1000_XOFFRXC);
672 E1000_READ_REG(hw, E1000_XOFFTXC);
673 E1000_READ_REG(hw, E1000_FCRUC);
674 E1000_READ_REG(hw, E1000_GPRC);
675 E1000_READ_REG(hw, E1000_BPRC);
676 E1000_READ_REG(hw, E1000_MPRC);
677 E1000_READ_REG(hw, E1000_GPTC);
678 E1000_READ_REG(hw, E1000_GORCL);
679 E1000_READ_REG(hw, E1000_GORCH);
680 E1000_READ_REG(hw, E1000_GOTCL);
681 E1000_READ_REG(hw, E1000_GOTCH);
682 E1000_READ_REG(hw, E1000_RNBC);
683 E1000_READ_REG(hw, E1000_RUC);
684 E1000_READ_REG(hw, E1000_RFC);
685 E1000_READ_REG(hw, E1000_ROC);
686 E1000_READ_REG(hw, E1000_RJC);
687 E1000_READ_REG(hw, E1000_TORL);
688 E1000_READ_REG(hw, E1000_TORH);
689 E1000_READ_REG(hw, E1000_TOTL);
690 E1000_READ_REG(hw, E1000_TOTH);
691 E1000_READ_REG(hw, E1000_TPR);
692 E1000_READ_REG(hw, E1000_TPT);
693 E1000_READ_REG(hw, E1000_MPTC);
694 E1000_READ_REG(hw, E1000_BPTC);
698 * e1000_check_for_copper_link_generic - Check for link (Copper)
699 * @hw: pointer to the HW structure
701 * Checks to see of the link status of the hardware has changed. If a
702 * change in link status has been detected, then we read the PHY registers
703 * to get the current speed/duplex if link exists.
705 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
707 struct e1000_mac_info *mac = &hw->mac;
711 DEBUGFUNC("e1000_check_for_copper_link");
713 /* We only want to go out to the PHY registers to see if Auto-Neg
714 * has completed and/or if our link status has changed. The
715 * get_link_status flag is set upon receiving a Link Status
716 * Change or Rx Sequence Error interrupt.
718 if (!mac->get_link_status)
719 return E1000_SUCCESS;
721 /* First we want to see if the MII Status Register reports
722 * link. If so, then we want to get the current speed/duplex
725 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
730 return E1000_SUCCESS; /* No link detected */
732 mac->get_link_status = false;
734 /* Check if there was DownShift, must be checked
735 * immediately after link-up
737 e1000_check_downshift_generic(hw);
739 /* If we are forcing speed/duplex, then we simply return since
740 * we have already determined whether we have link or not.
743 return -E1000_ERR_CONFIG;
745 /* Auto-Neg is enabled. Auto Speed Detection takes care
746 * of MAC speed/duplex configuration. So we only need to
747 * configure Collision Distance in the MAC.
749 mac->ops.config_collision_dist(hw);
751 /* Configure Flow Control now that Auto-Neg has completed.
752 * First, we need to restore the desired flow control
753 * settings because we may have had to re-autoneg with a
754 * different link partner.
756 ret_val = e1000_config_fc_after_link_up_generic(hw);
758 DEBUGOUT("Error configuring flow control\n");
764 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
765 * @hw: pointer to the HW structure
767 * Checks for link up on the hardware. If link is not up and we have
768 * a signal, then we need to force link up.
770 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
772 struct e1000_mac_info *mac = &hw->mac;
778 DEBUGFUNC("e1000_check_for_fiber_link_generic");
780 ctrl = E1000_READ_REG(hw, E1000_CTRL);
781 status = E1000_READ_REG(hw, E1000_STATUS);
782 rxcw = E1000_READ_REG(hw, E1000_RXCW);
784 /* If we don't have link (auto-negotiation failed or link partner
785 * cannot auto-negotiate), the cable is plugged in (we have signal),
786 * and our link partner is not trying to auto-negotiate with us (we
787 * are receiving idles or data), we need to force link up. We also
788 * need to give auto-negotiation time to complete, in case the cable
789 * was just plugged in. The autoneg_failed flag does this.
791 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
792 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
793 !(rxcw & E1000_RXCW_C)) {
794 if (!mac->autoneg_failed) {
795 mac->autoneg_failed = true;
796 return E1000_SUCCESS;
798 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
800 /* Disable auto-negotiation in the TXCW register */
801 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
803 /* Force link-up and also force full-duplex. */
804 ctrl = E1000_READ_REG(hw, E1000_CTRL);
805 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
806 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
808 /* Configure Flow Control after forcing link up. */
809 ret_val = e1000_config_fc_after_link_up_generic(hw);
811 DEBUGOUT("Error configuring flow control\n");
814 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
815 /* If we are forcing link and we are receiving /C/ ordered
816 * sets, re-enable auto-negotiation in the TXCW register
817 * and disable forced link in the Device Control register
818 * in an attempt to auto-negotiate with our link partner.
820 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
821 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
822 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
824 mac->serdes_has_link = true;
827 return E1000_SUCCESS;
831 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
832 * @hw: pointer to the HW structure
834 * Checks for link up on the hardware. If link is not up and we have
835 * a signal, then we need to force link up.
837 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
839 struct e1000_mac_info *mac = &hw->mac;
845 DEBUGFUNC("e1000_check_for_serdes_link_generic");
847 ctrl = E1000_READ_REG(hw, E1000_CTRL);
848 status = E1000_READ_REG(hw, E1000_STATUS);
849 rxcw = E1000_READ_REG(hw, E1000_RXCW);
851 /* If we don't have link (auto-negotiation failed or link partner
852 * cannot auto-negotiate), and our link partner is not trying to
853 * auto-negotiate with us (we are receiving idles or data),
854 * we need to force link up. We also need to give auto-negotiation
857 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
858 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
859 if (!mac->autoneg_failed) {
860 mac->autoneg_failed = true;
861 return E1000_SUCCESS;
863 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
865 /* Disable auto-negotiation in the TXCW register */
866 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
868 /* Force link-up and also force full-duplex. */
869 ctrl = E1000_READ_REG(hw, E1000_CTRL);
870 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
871 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
873 /* Configure Flow Control after forcing link up. */
874 ret_val = e1000_config_fc_after_link_up_generic(hw);
876 DEBUGOUT("Error configuring flow control\n");
879 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
880 /* If we are forcing link and we are receiving /C/ ordered
881 * sets, re-enable auto-negotiation in the TXCW register
882 * and disable forced link in the Device Control register
883 * in an attempt to auto-negotiate with our link partner.
885 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
886 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
887 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
889 mac->serdes_has_link = true;
890 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
891 /* If we force link for non-auto-negotiation switch, check
892 * link status based on MAC synchronization for internal
895 /* SYNCH bit and IV bit are sticky. */
897 rxcw = E1000_READ_REG(hw, E1000_RXCW);
898 if (rxcw & E1000_RXCW_SYNCH) {
899 if (!(rxcw & E1000_RXCW_IV)) {
900 mac->serdes_has_link = true;
901 DEBUGOUT("SERDES: Link up - forced.\n");
904 mac->serdes_has_link = false;
905 DEBUGOUT("SERDES: Link down - force failed.\n");
909 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
910 status = E1000_READ_REG(hw, E1000_STATUS);
911 if (status & E1000_STATUS_LU) {
912 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
914 rxcw = E1000_READ_REG(hw, E1000_RXCW);
915 if (rxcw & E1000_RXCW_SYNCH) {
916 if (!(rxcw & E1000_RXCW_IV)) {
917 mac->serdes_has_link = true;
918 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
920 mac->serdes_has_link = false;
921 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
924 mac->serdes_has_link = false;
925 DEBUGOUT("SERDES: Link down - no sync.\n");
928 mac->serdes_has_link = false;
929 DEBUGOUT("SERDES: Link down - autoneg failed\n");
933 return E1000_SUCCESS;
937 * e1000_set_default_fc_generic - Set flow control default values
938 * @hw: pointer to the HW structure
940 * Read the EEPROM for the default values for flow control and store the
943 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
948 DEBUGFUNC("e1000_set_default_fc_generic");
950 /* Read and store word 0x0F of the EEPROM. This word contains bits
951 * that determine the hardware's default PAUSE (flow control) mode,
952 * a bit that determines whether the HW defaults to enabling or
953 * disabling auto-negotiation, and the direction of the
954 * SW defined pins. If there is no SW over-ride of the flow
955 * control setting, then the variable hw->fc will
956 * be initialized based on a value in the EEPROM.
958 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
961 DEBUGOUT("NVM Read Error\n");
965 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
966 hw->fc.requested_mode = e1000_fc_none;
967 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
969 hw->fc.requested_mode = e1000_fc_tx_pause;
971 hw->fc.requested_mode = e1000_fc_full;
973 return E1000_SUCCESS;
977 * e1000_setup_link_generic - Setup flow control and link settings
978 * @hw: pointer to the HW structure
980 * Determines which flow control settings to use, then configures flow
981 * control. Calls the appropriate media-specific link configuration
982 * function. Assuming the adapter has a valid link partner, a valid link
983 * should be established. Assumes the hardware has previously been reset
984 * and the transmitter and receiver are not enabled.
986 s32 e1000_setup_link_generic(struct e1000_hw *hw)
990 DEBUGFUNC("e1000_setup_link_generic");
992 /* In the case of the phy reset being blocked, we already have a link.
993 * We do not need to set it up again.
995 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
996 return E1000_SUCCESS;
998 /* If requested flow control is set to default, set flow control
999 * based on the EEPROM flow control settings.
1001 if (hw->fc.requested_mode == e1000_fc_default) {
1002 ret_val = e1000_set_default_fc_generic(hw);
1007 /* Save off the requested flow control mode for use later. Depending
1008 * on the link partner's capabilities, we may or may not use this mode.
1010 hw->fc.current_mode = hw->fc.requested_mode;
1012 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1013 hw->fc.current_mode);
1015 /* Call the necessary media_type subroutine to configure the link. */
1016 ret_val = hw->mac.ops.setup_physical_interface(hw);
1020 /* Initialize the flow control address, type, and PAUSE timer
1021 * registers to their default values. This is done even if flow
1022 * control is disabled, because it does not hurt anything to
1023 * initialize these registers.
1025 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1026 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1027 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1028 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1030 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1032 return e1000_set_fc_watermarks_generic(hw);
1036 * e1000_commit_fc_settings_generic - Configure flow control
1037 * @hw: pointer to the HW structure
1039 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1040 * base on the flow control settings in e1000_mac_info.
1042 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1044 struct e1000_mac_info *mac = &hw->mac;
1047 DEBUGFUNC("e1000_commit_fc_settings_generic");
1049 /* Check for a software override of the flow control settings, and
1050 * setup the device accordingly. If auto-negotiation is enabled, then
1051 * software will have to set the "PAUSE" bits to the correct value in
1052 * the Transmit Config Word Register (TXCW) and re-start auto-
1053 * negotiation. However, if auto-negotiation is disabled, then
1054 * software will have to manually configure the two flow control enable
1055 * bits in the CTRL register.
1057 * The possible values of the "fc" parameter are:
1058 * 0: Flow control is completely disabled
1059 * 1: Rx flow control is enabled (we can receive pause frames,
1060 * but not send pause frames).
1061 * 2: Tx flow control is enabled (we can send pause frames but we
1062 * do not support receiving pause frames).
1063 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1065 switch (hw->fc.current_mode) {
1067 /* Flow control completely disabled by a software over-ride. */
1068 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1070 case e1000_fc_rx_pause:
1071 /* Rx Flow control is enabled and Tx Flow control is disabled
1072 * by a software over-ride. Since there really isn't a way to
1073 * advertise that we are capable of Rx Pause ONLY, we will
1074 * advertise that we support both symmetric and asymmetric Rx
1075 * PAUSE. Later, we will disable the adapter's ability to send
1078 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1080 case e1000_fc_tx_pause:
1081 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1082 * by a software over-ride.
1084 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1087 /* Flow control (both Rx and Tx) is enabled by a software
1090 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1093 DEBUGOUT("Flow control param set incorrectly\n");
1094 return -E1000_ERR_CONFIG;
1098 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1101 return E1000_SUCCESS;
1105 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1106 * @hw: pointer to the HW structure
1108 * Polls for link up by reading the status register, if link fails to come
1109 * up with auto-negotiation, then the link is forced if a signal is detected.
1111 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1113 struct e1000_mac_info *mac = &hw->mac;
1117 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1119 /* If we have a signal (the cable is plugged in, or assumed true for
1120 * serdes media) then poll for a "Link-Up" indication in the Device
1121 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1122 * seconds (Auto-negotiation should complete in less than 500
1123 * milliseconds even if the other end is doing it in SW).
1125 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1127 status = E1000_READ_REG(hw, E1000_STATUS);
1128 if (status & E1000_STATUS_LU)
1131 if (i == FIBER_LINK_UP_LIMIT) {
1132 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1133 mac->autoneg_failed = true;
1134 /* AutoNeg failed to achieve a link, so we'll call
1135 * mac->check_for_link. This routine will force the
1136 * link up if we detect a signal. This will allow us to
1137 * communicate with non-autonegotiating link partners.
1139 ret_val = mac->ops.check_for_link(hw);
1141 DEBUGOUT("Error while checking for link\n");
1144 mac->autoneg_failed = false;
1146 mac->autoneg_failed = false;
1147 DEBUGOUT("Valid Link Found\n");
1150 return E1000_SUCCESS;
1154 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1155 * @hw: pointer to the HW structure
1157 * Configures collision distance and flow control for fiber and serdes
1158 * links. Upon successful setup, poll for link.
1160 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1165 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1167 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1169 /* Take the link out of reset */
1170 ctrl &= ~E1000_CTRL_LRST;
1172 hw->mac.ops.config_collision_dist(hw);
1174 ret_val = e1000_commit_fc_settings_generic(hw);
1178 /* Since auto-negotiation is enabled, take the link out of reset (the
1179 * link will be in reset, because we previously reset the chip). This
1180 * will restart auto-negotiation. If auto-negotiation is successful
1181 * then the link-up status bit will be set and the flow control enable
1182 * bits (RFCE and TFCE) will be set according to their negotiated value.
1184 DEBUGOUT("Auto-negotiation enabled\n");
1186 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1187 E1000_WRITE_FLUSH(hw);
1190 /* For these adapters, the SW definable pin 1 is set when the optics
1191 * detect a signal. If we have a signal, then poll for a "Link-Up"
1194 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1195 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1196 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1198 DEBUGOUT("No signal detected\n");
1205 * e1000_config_collision_dist_generic - Configure collision distance
1206 * @hw: pointer to the HW structure
1208 * Configures the collision distance to the default value and is used
1209 * during link setup.
1211 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1215 DEBUGFUNC("e1000_config_collision_dist_generic");
1217 tctl = E1000_READ_REG(hw, E1000_TCTL);
1219 tctl &= ~E1000_TCTL_COLD;
1220 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1222 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1223 E1000_WRITE_FLUSH(hw);
1227 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1228 * @hw: pointer to the HW structure
1230 * Sets the flow control high/low threshold (watermark) registers. If
1231 * flow control XON frame transmission is enabled, then set XON frame
1232 * transmission as well.
1234 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1236 u32 fcrtl = 0, fcrth = 0;
1238 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1240 /* Set the flow control receive threshold registers. Normally,
1241 * these registers will be set to a default threshold that may be
1242 * adjusted later by the driver's runtime code. However, if the
1243 * ability to transmit pause frames is not enabled, then these
1244 * registers will be set to 0.
1246 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1247 /* We need to set up the Receive Threshold high and low water
1248 * marks as well as (optionally) enabling the transmission of
1251 fcrtl = hw->fc.low_water;
1252 if (hw->fc.send_xon)
1253 fcrtl |= E1000_FCRTL_XONE;
1255 fcrth = hw->fc.high_water;
1257 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1258 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1260 return E1000_SUCCESS;
1264 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1265 * @hw: pointer to the HW structure
1267 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1268 * device control register to reflect the adapter settings. TFCE and RFCE
1269 * need to be explicitly set by software when a copper PHY is used because
1270 * autonegotiation is managed by the PHY rather than the MAC. Software must
1271 * also configure these bits when link is forced on a fiber connection.
1273 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1277 DEBUGFUNC("e1000_force_mac_fc_generic");
1279 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1281 /* Because we didn't get link via the internal auto-negotiation
1282 * mechanism (we either forced link or we got link via PHY
1283 * auto-neg), we have to manually enable/disable transmit an
1284 * receive flow control.
1286 * The "Case" statement below enables/disable flow control
1287 * according to the "hw->fc.current_mode" parameter.
1289 * The possible values of the "fc" parameter are:
1290 * 0: Flow control is completely disabled
1291 * 1: Rx flow control is enabled (we can receive pause
1292 * frames but not send pause frames).
1293 * 2: Tx flow control is enabled (we can send pause frames
1294 * frames but we do not receive pause frames).
1295 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1296 * other: No other values should be possible at this point.
1298 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1300 switch (hw->fc.current_mode) {
1302 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1304 case e1000_fc_rx_pause:
1305 ctrl &= (~E1000_CTRL_TFCE);
1306 ctrl |= E1000_CTRL_RFCE;
1308 case e1000_fc_tx_pause:
1309 ctrl &= (~E1000_CTRL_RFCE);
1310 ctrl |= E1000_CTRL_TFCE;
1313 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1316 DEBUGOUT("Flow control param set incorrectly\n");
1317 return -E1000_ERR_CONFIG;
1320 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1322 return E1000_SUCCESS;
1326 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1327 * @hw: pointer to the HW structure
1329 * Checks the status of auto-negotiation after link up to ensure that the
1330 * speed and duplex were not forced. If the link needed to be forced, then
1331 * flow control needs to be forced also. If auto-negotiation is enabled
1332 * and did not fail, then we configure flow control based on our link
1335 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1337 struct e1000_mac_info *mac = &hw->mac;
1338 s32 ret_val = E1000_SUCCESS;
1339 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1340 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1343 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1345 /* Check for the case where we have fiber media and auto-neg failed
1346 * so we had to force link. In this case, we need to force the
1347 * configuration of the MAC to match the "fc" parameter.
1349 if (mac->autoneg_failed) {
1350 if (hw->phy.media_type == e1000_media_type_fiber ||
1351 hw->phy.media_type == e1000_media_type_internal_serdes)
1352 ret_val = e1000_force_mac_fc_generic(hw);
1354 if (hw->phy.media_type == e1000_media_type_copper)
1355 ret_val = e1000_force_mac_fc_generic(hw);
1359 DEBUGOUT("Error forcing flow control settings\n");
1363 /* Check for the case where we have copper media and auto-neg is
1364 * enabled. In this case, we need to check and see if Auto-Neg
1365 * has completed, and if so, how the PHY and link partner has
1366 * flow control configured.
1368 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1369 /* Read the MII Status Register and check to see if AutoNeg
1370 * has completed. We read this twice because this reg has
1371 * some "sticky" (latched) bits.
1373 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1380 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1381 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1385 /* The AutoNeg process has completed, so we now need to
1386 * read both the Auto Negotiation Advertisement
1387 * Register (Address 4) and the Auto_Negotiation Base
1388 * Page Ability Register (Address 5) to determine how
1389 * flow control was negotiated.
1391 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1395 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1396 &mii_nway_lp_ability_reg);
1400 /* Two bits in the Auto Negotiation Advertisement Register
1401 * (Address 4) and two bits in the Auto Negotiation Base
1402 * Page Ability Register (Address 5) determine flow control
1403 * for both the PHY and the link partner. The following
1404 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1405 * 1999, describes these PAUSE resolution bits and how flow
1406 * control is determined based upon these settings.
1407 * NOTE: DC = Don't Care
1409 * LOCAL DEVICE | LINK PARTNER
1410 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1411 *-------|---------|-------|---------|--------------------
1412 * 0 | 0 | DC | DC | e1000_fc_none
1413 * 0 | 1 | 0 | DC | e1000_fc_none
1414 * 0 | 1 | 1 | 0 | e1000_fc_none
1415 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1416 * 1 | 0 | 0 | DC | e1000_fc_none
1417 * 1 | DC | 1 | DC | e1000_fc_full
1418 * 1 | 1 | 0 | 0 | e1000_fc_none
1419 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1421 * Are both PAUSE bits set to 1? If so, this implies
1422 * Symmetric Flow Control is enabled at both ends. The
1423 * ASM_DIR bits are irrelevant per the spec.
1425 * For Symmetric Flow Control:
1427 * LOCAL DEVICE | LINK PARTNER
1428 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1429 *-------|---------|-------|---------|--------------------
1430 * 1 | DC | 1 | DC | E1000_fc_full
1433 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1434 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1435 /* Now we need to check if the user selected Rx ONLY
1436 * of pause frames. In this case, we had to advertise
1437 * FULL flow control because we could not advertise Rx
1438 * ONLY. Hence, we must now check to see if we need to
1439 * turn OFF the TRANSMISSION of PAUSE frames.
1441 if (hw->fc.requested_mode == e1000_fc_full) {
1442 hw->fc.current_mode = e1000_fc_full;
1443 DEBUGOUT("Flow Control = FULL.\n");
1445 hw->fc.current_mode = e1000_fc_rx_pause;
1446 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1449 /* For receiving PAUSE frames ONLY.
1451 * LOCAL DEVICE | LINK PARTNER
1452 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1453 *-------|---------|-------|---------|--------------------
1454 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1456 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1457 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1458 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1459 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1460 hw->fc.current_mode = e1000_fc_tx_pause;
1461 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1463 /* For transmitting PAUSE frames ONLY.
1465 * LOCAL DEVICE | LINK PARTNER
1466 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1467 *-------|---------|-------|---------|--------------------
1468 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1470 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1471 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1472 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1473 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1474 hw->fc.current_mode = e1000_fc_rx_pause;
1475 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1477 /* Per the IEEE spec, at this point flow control
1478 * should be disabled.
1480 hw->fc.current_mode = e1000_fc_none;
1481 DEBUGOUT("Flow Control = NONE.\n");
1484 /* Now we need to do one last check... If we auto-
1485 * negotiated to HALF DUPLEX, flow control should not be
1486 * enabled per IEEE 802.3 spec.
1488 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1490 DEBUGOUT("Error getting link speed and duplex\n");
1494 if (duplex == HALF_DUPLEX)
1495 hw->fc.current_mode = e1000_fc_none;
1497 /* Now we call a subroutine to actually force the MAC
1498 * controller to use the correct flow control settings.
1500 ret_val = e1000_force_mac_fc_generic(hw);
1502 DEBUGOUT("Error forcing flow control settings\n");
1507 /* Check for the case where we have SerDes media and auto-neg is
1508 * enabled. In this case, we need to check and see if Auto-Neg
1509 * has completed, and if so, how the PHY and link partner has
1510 * flow control configured.
1512 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
1514 /* Read the PCS_LSTS and check to see if AutoNeg
1517 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1519 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1520 DEBUGOUT("PCS Auto Neg has not completed.\n");
1524 /* The AutoNeg process has completed, so we now need to
1525 * read both the Auto Negotiation Advertisement
1526 * Register (PCS_ANADV) and the Auto_Negotiation Base
1527 * Page Ability Register (PCS_LPAB) to determine how
1528 * flow control was negotiated.
1530 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1531 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1533 /* Two bits in the Auto Negotiation Advertisement Register
1534 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1535 * Page Ability Register (PCS_LPAB) determine flow control
1536 * for both the PHY and the link partner. The following
1537 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1538 * 1999, describes these PAUSE resolution bits and how flow
1539 * control is determined based upon these settings.
1540 * NOTE: DC = Don't Care
1542 * LOCAL DEVICE | LINK PARTNER
1543 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1544 *-------|---------|-------|---------|--------------------
1545 * 0 | 0 | DC | DC | e1000_fc_none
1546 * 0 | 1 | 0 | DC | e1000_fc_none
1547 * 0 | 1 | 1 | 0 | e1000_fc_none
1548 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1549 * 1 | 0 | 0 | DC | e1000_fc_none
1550 * 1 | DC | 1 | DC | e1000_fc_full
1551 * 1 | 1 | 0 | 0 | e1000_fc_none
1552 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1554 * Are both PAUSE bits set to 1? If so, this implies
1555 * Symmetric Flow Control is enabled at both ends. The
1556 * ASM_DIR bits are irrelevant per the spec.
1558 * For Symmetric Flow Control:
1560 * LOCAL DEVICE | LINK PARTNER
1561 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1562 *-------|---------|-------|---------|--------------------
1563 * 1 | DC | 1 | DC | e1000_fc_full
1566 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1567 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1568 /* Now we need to check if the user selected Rx ONLY
1569 * of pause frames. In this case, we had to advertise
1570 * FULL flow control because we could not advertise Rx
1571 * ONLY. Hence, we must now check to see if we need to
1572 * turn OFF the TRANSMISSION of PAUSE frames.
1574 if (hw->fc.requested_mode == e1000_fc_full) {
1575 hw->fc.current_mode = e1000_fc_full;
1576 DEBUGOUT("Flow Control = FULL.\n");
1578 hw->fc.current_mode = e1000_fc_rx_pause;
1579 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1582 /* For receiving PAUSE frames ONLY.
1584 * LOCAL DEVICE | LINK PARTNER
1585 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1586 *-------|---------|-------|---------|--------------------
1587 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1589 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1590 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1591 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1592 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1593 hw->fc.current_mode = e1000_fc_tx_pause;
1594 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1596 /* For transmitting PAUSE frames ONLY.
1598 * LOCAL DEVICE | LINK PARTNER
1599 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1600 *-------|---------|-------|---------|--------------------
1601 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1603 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1604 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1605 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1606 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1607 hw->fc.current_mode = e1000_fc_rx_pause;
1608 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1610 /* Per the IEEE spec, at this point flow control
1611 * should be disabled.
1613 hw->fc.current_mode = e1000_fc_none;
1614 DEBUGOUT("Flow Control = NONE.\n");
1617 /* Now we call a subroutine to actually force the MAC
1618 * controller to use the correct flow control settings.
1620 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1621 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1622 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1624 ret_val = e1000_force_mac_fc_generic(hw);
1626 DEBUGOUT("Error forcing flow control settings\n");
1631 return E1000_SUCCESS;
1635 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1636 * @hw: pointer to the HW structure
1637 * @speed: stores the current speed
1638 * @duplex: stores the current duplex
1640 * Read the status register for the current speed/duplex and store the current
1641 * speed and duplex for copper connections.
1643 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1648 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1650 status = E1000_READ_REG(hw, E1000_STATUS);
1651 if (status & E1000_STATUS_SPEED_1000) {
1652 *speed = SPEED_1000;
1653 DEBUGOUT("1000 Mbs, ");
1654 } else if (status & E1000_STATUS_SPEED_100) {
1656 DEBUGOUT("100 Mbs, ");
1659 DEBUGOUT("10 Mbs, ");
1662 if (status & E1000_STATUS_FD) {
1663 *duplex = FULL_DUPLEX;
1664 DEBUGOUT("Full Duplex\n");
1666 *duplex = HALF_DUPLEX;
1667 DEBUGOUT("Half Duplex\n");
1670 return E1000_SUCCESS;
1674 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1675 * @hw: pointer to the HW structure
1676 * @speed: stores the current speed
1677 * @duplex: stores the current duplex
1679 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1680 * for fiber/serdes links.
1682 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,
1683 u16 *speed, u16 *duplex)
1685 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1686 UNREFERENCED_1PARAMETER(hw);
1688 *speed = SPEED_1000;
1689 *duplex = FULL_DUPLEX;
1691 return E1000_SUCCESS;
1695 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1696 * @hw: pointer to the HW structure
1698 * Acquire the HW semaphore to access the PHY or NVM
1700 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1703 s32 timeout = hw->nvm.word_size + 1;
1706 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1708 /* Get the SW semaphore */
1709 while (i < timeout) {
1710 swsm = E1000_READ_REG(hw, E1000_SWSM);
1711 if (!(swsm & E1000_SWSM_SMBI))
1719 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1720 return -E1000_ERR_NVM;
1723 /* Get the FW semaphore. */
1724 for (i = 0; i < timeout; i++) {
1725 swsm = E1000_READ_REG(hw, E1000_SWSM);
1726 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1728 /* Semaphore acquired if bit latched */
1729 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1736 /* Release semaphores */
1737 e1000_put_hw_semaphore_generic(hw);
1738 DEBUGOUT("Driver can't access the NVM\n");
1739 return -E1000_ERR_NVM;
1742 return E1000_SUCCESS;
1746 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1747 * @hw: pointer to the HW structure
1749 * Release hardware semaphore used to access the PHY or NVM
1751 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1755 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1757 swsm = E1000_READ_REG(hw, E1000_SWSM);
1759 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1761 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1765 * e1000_get_auto_rd_done_generic - Check for auto read completion
1766 * @hw: pointer to the HW structure
1768 * Check EEPROM for Auto Read done bit.
1770 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1774 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1776 while (i < AUTO_READ_DONE_TIMEOUT) {
1777 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1783 if (i == AUTO_READ_DONE_TIMEOUT) {
1784 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1785 return -E1000_ERR_RESET;
1788 return E1000_SUCCESS;
1792 * e1000_valid_led_default_generic - Verify a valid default LED config
1793 * @hw: pointer to the HW structure
1794 * @data: pointer to the NVM (EEPROM)
1796 * Read the EEPROM for the current default LED configuration. If the
1797 * LED configuration is not valid, set to a valid LED configuration.
1799 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1803 DEBUGFUNC("e1000_valid_led_default_generic");
1805 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1807 DEBUGOUT("NVM Read Error\n");
1811 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1812 *data = ID_LED_DEFAULT;
1814 return E1000_SUCCESS;
1818 * e1000_id_led_init_generic -
1819 * @hw: pointer to the HW structure
1822 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1824 struct e1000_mac_info *mac = &hw->mac;
1826 const u32 ledctl_mask = 0x000000FF;
1827 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1828 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1830 const u16 led_mask = 0x0F;
1832 DEBUGFUNC("e1000_id_led_init_generic");
1834 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1838 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1839 mac->ledctl_mode1 = mac->ledctl_default;
1840 mac->ledctl_mode2 = mac->ledctl_default;
1842 for (i = 0; i < 4; i++) {
1843 temp = (data >> (i << 2)) & led_mask;
1845 case ID_LED_ON1_DEF2:
1846 case ID_LED_ON1_ON2:
1847 case ID_LED_ON1_OFF2:
1848 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1849 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1851 case ID_LED_OFF1_DEF2:
1852 case ID_LED_OFF1_ON2:
1853 case ID_LED_OFF1_OFF2:
1854 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1855 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1862 case ID_LED_DEF1_ON2:
1863 case ID_LED_ON1_ON2:
1864 case ID_LED_OFF1_ON2:
1865 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1866 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1868 case ID_LED_DEF1_OFF2:
1869 case ID_LED_ON1_OFF2:
1870 case ID_LED_OFF1_OFF2:
1871 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1872 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1880 return E1000_SUCCESS;
1884 * e1000_setup_led_generic - Configures SW controllable LED
1885 * @hw: pointer to the HW structure
1887 * This prepares the SW controllable LED for use and saves the current state
1888 * of the LED so it can be later restored.
1890 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1894 DEBUGFUNC("e1000_setup_led_generic");
1896 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1897 return -E1000_ERR_CONFIG;
1899 if (hw->phy.media_type == e1000_media_type_fiber) {
1900 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1901 hw->mac.ledctl_default = ledctl;
1903 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1904 E1000_LEDCTL_LED0_MODE_MASK);
1905 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1906 E1000_LEDCTL_LED0_MODE_SHIFT);
1907 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1908 } else if (hw->phy.media_type == e1000_media_type_copper) {
1909 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1912 return E1000_SUCCESS;
1916 * e1000_cleanup_led_generic - Set LED config to default operation
1917 * @hw: pointer to the HW structure
1919 * Remove the current LED configuration and set the LED configuration
1920 * to the default value, saved from the EEPROM.
1922 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1924 DEBUGFUNC("e1000_cleanup_led_generic");
1926 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1927 return E1000_SUCCESS;
1931 * e1000_blink_led_generic - Blink LED
1932 * @hw: pointer to the HW structure
1934 * Blink the LEDs which are set to be on.
1936 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1938 u32 ledctl_blink = 0;
1941 DEBUGFUNC("e1000_blink_led_generic");
1943 if (hw->phy.media_type == e1000_media_type_fiber) {
1944 /* always blink LED0 for PCI-E fiber */
1945 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1946 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1949 * set the blink bit for each LED that's "on" (0x0E)
1952 ledctl_blink = hw->mac.ledctl_mode2;
1953 for (i = 0; i < 4; i++)
1954 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1955 E1000_LEDCTL_MODE_LED_ON)
1956 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1960 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1962 return E1000_SUCCESS;
1966 * e1000_led_on_generic - Turn LED on
1967 * @hw: pointer to the HW structure
1971 s32 e1000_led_on_generic(struct e1000_hw *hw)
1975 DEBUGFUNC("e1000_led_on_generic");
1977 switch (hw->phy.media_type) {
1978 case e1000_media_type_fiber:
1979 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1980 ctrl &= ~E1000_CTRL_SWDPIN0;
1981 ctrl |= E1000_CTRL_SWDPIO0;
1982 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1984 case e1000_media_type_copper:
1985 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1991 return E1000_SUCCESS;
1995 * e1000_led_off_generic - Turn LED off
1996 * @hw: pointer to the HW structure
2000 s32 e1000_led_off_generic(struct e1000_hw *hw)
2004 DEBUGFUNC("e1000_led_off_generic");
2006 switch (hw->phy.media_type) {
2007 case e1000_media_type_fiber:
2008 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2009 ctrl |= E1000_CTRL_SWDPIN0;
2010 ctrl |= E1000_CTRL_SWDPIO0;
2011 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2013 case e1000_media_type_copper:
2014 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2020 return E1000_SUCCESS;
2024 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2025 * @hw: pointer to the HW structure
2026 * @no_snoop: bitmap of snoop events
2028 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2030 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2034 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2036 if (hw->bus.type != e1000_bus_type_pci_express)
2040 gcr = E1000_READ_REG(hw, E1000_GCR);
2041 gcr &= ~(PCIE_NO_SNOOP_ALL);
2043 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2048 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2049 * @hw: pointer to the HW structure
2051 * Returns E1000_SUCCESS if successful, else returns -10
2052 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2053 * the master requests to be disabled.
2055 * Disables PCI-Express master access and verifies there are no pending
2058 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2061 s32 timeout = MASTER_DISABLE_TIMEOUT;
2063 DEBUGFUNC("e1000_disable_pcie_master_generic");
2065 if (hw->bus.type != e1000_bus_type_pci_express)
2066 return E1000_SUCCESS;
2068 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2069 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2070 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2073 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2074 E1000_STATUS_GIO_MASTER_ENABLE))
2081 DEBUGOUT("Master requests are pending.\n");
2082 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2085 return E1000_SUCCESS;
2089 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2090 * @hw: pointer to the HW structure
2092 * Reset the Adaptive Interframe Spacing throttle to default values.
2094 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2096 struct e1000_mac_info *mac = &hw->mac;
2098 DEBUGFUNC("e1000_reset_adaptive_generic");
2100 if (!mac->adaptive_ifs) {
2101 DEBUGOUT("Not in Adaptive IFS mode!\n");
2105 mac->current_ifs_val = 0;
2106 mac->ifs_min_val = IFS_MIN;
2107 mac->ifs_max_val = IFS_MAX;
2108 mac->ifs_step_size = IFS_STEP;
2109 mac->ifs_ratio = IFS_RATIO;
2111 mac->in_ifs_mode = false;
2112 E1000_WRITE_REG(hw, E1000_AIT, 0);
2116 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2117 * @hw: pointer to the HW structure
2119 * Update the Adaptive Interframe Spacing Throttle value based on the
2120 * time between transmitted packets and time between collisions.
2122 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2124 struct e1000_mac_info *mac = &hw->mac;
2126 DEBUGFUNC("e1000_update_adaptive_generic");
2128 if (!mac->adaptive_ifs) {
2129 DEBUGOUT("Not in Adaptive IFS mode!\n");
2133 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2134 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2135 mac->in_ifs_mode = true;
2136 if (mac->current_ifs_val < mac->ifs_max_val) {
2137 if (!mac->current_ifs_val)
2138 mac->current_ifs_val = mac->ifs_min_val;
2140 mac->current_ifs_val +=
2142 E1000_WRITE_REG(hw, E1000_AIT,
2143 mac->current_ifs_val);
2147 if (mac->in_ifs_mode &&
2148 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2149 mac->current_ifs_val = 0;
2150 mac->in_ifs_mode = false;
2151 E1000_WRITE_REG(hw, E1000_AIT, 0);
2157 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2158 * @hw: pointer to the HW structure
2160 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2161 * set, which is forced to MDI mode only.
2163 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2165 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2167 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2168 DEBUGOUT("Invalid MDI setting detected\n");
2170 return -E1000_ERR_CONFIG;
2173 return E1000_SUCCESS;
2177 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2178 * @hw: pointer to the HW structure
2180 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2183 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2185 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2186 UNREFERENCED_1PARAMETER(hw);
2188 return E1000_SUCCESS;
2192 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2193 * @hw: pointer to the HW structure
2194 * @reg: 32bit register offset such as E1000_SCTL
2195 * @offset: register offset to write to
2196 * @data: data to write at register offset
2198 * Writes an address/data control type register. There are several of these
2199 * and they all have the format address << 8 | data and bit 31 is polled for
2202 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2203 u32 offset, u8 data)
2205 u32 i, regvalue = 0;
2207 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2209 /* Set up the address and data */
2210 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2211 E1000_WRITE_REG(hw, reg, regvalue);
2213 /* Poll the ready bit to see if the MDI read completed */
2214 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2216 regvalue = E1000_READ_REG(hw, reg);
2217 if (regvalue & E1000_GEN_CTL_READY)
2220 if (!(regvalue & E1000_GEN_CTL_READY)) {
2221 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2222 return -E1000_ERR_PHY;
2225 return E1000_SUCCESS;