4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
50 #include <rte_tailq.h>
52 #include <rte_atomic.h>
53 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "e1000/e1000_api.h"
58 #include "e1000_ethdev.h"
60 #define EM_EIAC 0x000DC
62 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
65 static int eth_em_configure(struct rte_eth_dev *dev);
66 static int eth_em_start(struct rte_eth_dev *dev);
67 static void eth_em_stop(struct rte_eth_dev *dev);
68 static void eth_em_close(struct rte_eth_dev *dev);
69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
73 static int eth_em_link_update(struct rte_eth_dev *dev,
74 int wait_to_complete);
75 static void eth_em_stats_get(struct rte_eth_dev *dev,
76 struct rte_eth_stats *rte_stats);
77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
78 static void eth_em_infos_get(struct rte_eth_dev *dev,
79 struct rte_eth_dev_info *dev_info);
80 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
81 struct rte_eth_fc_conf *fc_conf);
82 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
83 struct rte_eth_fc_conf *fc_conf);
84 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
90 static int em_hw_init(struct e1000_hw *hw);
91 static int em_hardware_init(struct e1000_hw *hw);
92 static void em_hw_control_acquire(struct e1000_hw *hw);
93 static void em_hw_control_release(struct e1000_hw *hw);
94 static void em_init_manageability(struct e1000_hw *hw);
95 static void em_release_manageability(struct e1000_hw *hw);
97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
100 uint16_t vlan_id, int on);
101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
109 uint16_t vlan_id, int on);
111 static int eth_em_led_on(struct rte_eth_dev *dev);
112 static int eth_em_led_off(struct rte_eth_dev *dev);
114 static void em_intr_disable(struct e1000_hw *hw);
115 static int em_get_rx_buffer_size(struct e1000_hw *hw);
116 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
117 uint32_t index, uint32_t pool);
118 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
120 #define EM_FC_PAUSE_TIME 0x0680
121 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
122 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
124 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
127 * The set of PCI devices this driver supports
129 static struct rte_pci_id pci_id_em_map[] = {
131 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
132 #include "rte_pci_dev_ids.h"
137 static struct eth_dev_ops eth_em_ops = {
138 .dev_configure = eth_em_configure,
139 .dev_start = eth_em_start,
140 .dev_stop = eth_em_stop,
141 .dev_close = eth_em_close,
142 .promiscuous_enable = eth_em_promiscuous_enable,
143 .promiscuous_disable = eth_em_promiscuous_disable,
144 .allmulticast_enable = eth_em_allmulticast_enable,
145 .allmulticast_disable = eth_em_allmulticast_disable,
146 .link_update = eth_em_link_update,
147 .stats_get = eth_em_stats_get,
148 .stats_reset = eth_em_stats_reset,
149 .dev_infos_get = eth_em_infos_get,
150 .mtu_set = eth_em_mtu_set,
151 .vlan_filter_set = eth_em_vlan_filter_set,
152 .vlan_offload_set = eth_em_vlan_offload_set,
153 .rx_queue_setup = eth_em_rx_queue_setup,
154 .rx_queue_release = eth_em_rx_queue_release,
155 .rx_queue_count = eth_em_rx_queue_count,
156 .rx_descriptor_done = eth_em_rx_descriptor_done,
157 .tx_queue_setup = eth_em_tx_queue_setup,
158 .tx_queue_release = eth_em_tx_queue_release,
159 .dev_led_on = eth_em_led_on,
160 .dev_led_off = eth_em_led_off,
161 .flow_ctrl_get = eth_em_flow_ctrl_get,
162 .flow_ctrl_set = eth_em_flow_ctrl_set,
163 .mac_addr_add = eth_em_rar_set,
164 .mac_addr_remove = eth_em_rar_clear,
168 * Atomically reads the link status information from global
169 * structure rte_eth_dev.
172 * - Pointer to the structure rte_eth_dev to read from.
173 * - Pointer to the buffer to be saved with the link status.
176 * - On success, zero.
177 * - On failure, negative value.
180 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
181 struct rte_eth_link *link)
183 struct rte_eth_link *dst = link;
184 struct rte_eth_link *src = &(dev->data->dev_link);
186 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
187 *(uint64_t *)src) == 0)
194 * Atomically writes the link status information into global
195 * structure rte_eth_dev.
198 * - Pointer to the structure rte_eth_dev to read from.
199 * - Pointer to the buffer to be saved with the link status.
202 * - On success, zero.
203 * - On failure, negative value.
206 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
207 struct rte_eth_link *link)
209 struct rte_eth_link *dst = &(dev->data->dev_link);
210 struct rte_eth_link *src = link;
212 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
213 *(uint64_t *)src) == 0)
220 eth_em_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
221 struct rte_eth_dev *eth_dev)
223 struct rte_pci_device *pci_dev;
224 struct e1000_hw *hw =
225 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
226 struct e1000_vfta * shadow_vfta =
227 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
229 pci_dev = eth_dev->pci_dev;
230 eth_dev->dev_ops = ð_em_ops;
231 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
232 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
234 /* for secondary processes, we don't initialise any further as primary
235 * has already done this work. Only check we don't need a different
237 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
238 if (eth_dev->data->scattered_rx)
239 eth_dev->rx_pkt_burst =
240 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
244 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
245 hw->device_id = pci_dev->id.device_id;
247 /* For ICH8 support we'll need to map the flash memory BAR */
249 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
250 em_hw_init(hw) != 0) {
251 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
253 eth_dev->data->port_id, pci_dev->id.vendor_id,
254 pci_dev->id.device_id);
258 /* Allocate memory for storing MAC addresses */
259 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
260 hw->mac.rar_entry_count, 0);
261 if (eth_dev->data->mac_addrs == NULL) {
262 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
263 "store MAC addresses",
264 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
268 /* Copy the permanent MAC address */
269 ether_addr_copy((struct ether_addr *) hw->mac.addr,
270 eth_dev->data->mac_addrs);
272 /* initialize the vfta */
273 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
275 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
276 eth_dev->data->port_id, pci_dev->id.vendor_id,
277 pci_dev->id.device_id);
279 rte_intr_callback_register(&(pci_dev->intr_handle),
280 eth_em_interrupt_handler, (void *)eth_dev);
285 static struct eth_driver rte_em_pmd = {
287 .name = "rte_em_pmd",
288 .id_table = pci_id_em_map,
289 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
291 .eth_dev_init = eth_em_dev_init,
292 .dev_private_size = sizeof(struct e1000_adapter),
296 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
298 rte_eth_driver_register(&rte_em_pmd);
303 em_hw_init(struct e1000_hw *hw)
307 diag = hw->mac.ops.init_params(hw);
309 PMD_INIT_LOG(ERR, "MAC Initialization Error\n");
312 diag = hw->nvm.ops.init_params(hw);
314 PMD_INIT_LOG(ERR, "NVM Initialization Error\n");
317 diag = hw->phy.ops.init_params(hw);
319 PMD_INIT_LOG(ERR, "PHY Initialization Error\n");
322 (void) e1000_get_bus_info(hw);
325 hw->phy.autoneg_wait_to_complete = 0;
326 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
328 e1000_init_script_state_82541(hw, TRUE);
329 e1000_set_tbi_compatibility_82543(hw, TRUE);
332 if (hw->phy.media_type == e1000_media_type_copper) {
333 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
334 hw->phy.disable_polarity_correction = 0;
335 hw->phy.ms_type = e1000_ms_hw_default;
339 * Start from a known state, this is important in reading the nvm
344 /* Make sure we have a good EEPROM before we read from it */
345 if (e1000_validate_nvm_checksum(hw) < 0) {
347 * Some PCI-E parts fail the first check due to
348 * the link being in sleep state, call it again,
349 * if it fails a second time its a real issue.
351 diag = e1000_validate_nvm_checksum(hw);
353 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
358 /* Read the permanent MAC address out of the EEPROM */
359 diag = e1000_read_mac_addr(hw);
361 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
365 /* Now initialize the hardware */
366 diag = em_hardware_init(hw);
368 PMD_INIT_LOG(ERR, "Hardware initialization failed");
372 hw->mac.get_link_status = 1;
374 /* Indicate SOL/IDER usage */
375 diag = e1000_check_reset_block(hw);
377 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
383 em_hw_control_release(hw);
388 eth_em_configure(struct rte_eth_dev *dev)
390 struct e1000_interrupt *intr =
391 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
393 PMD_INIT_LOG(DEBUG, ">>");
395 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
397 PMD_INIT_LOG(DEBUG, "<<");
402 em_set_pba(struct e1000_hw *hw)
407 * Packet Buffer Allocation (PBA)
408 * Writing PBA sets the receive portion of the buffer
409 * the remainder is used for the transmit buffer.
410 * Devices before the 82547 had a Packet Buffer of 64K.
411 * After the 82547 the buffer was reduced to 40K.
413 switch (hw->mac.type) {
415 case e1000_82547_rev_2:
416 /* 82547: Total Packet Buffer is 40K */
417 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
421 case e1000_80003es2lan:
422 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
424 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
425 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
429 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
443 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
446 E1000_WRITE_REG(hw, E1000_PBA, pba);
450 eth_em_start(struct rte_eth_dev *dev)
452 struct e1000_hw *hw =
453 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
456 PMD_INIT_LOG(DEBUG, ">>");
460 e1000_power_up_phy(hw);
462 /* Set default PBA value */
465 /* Put the address into the Receive Address Array */
466 e1000_rar_set(hw, hw->mac.addr, 0);
469 * With the 82571 adapter, RAR[0] may be overwritten
470 * when the other port is reset, we make a duplicate
471 * in RAR[14] for that eventuality, this assures
472 * the interface continues to function.
474 if (hw->mac.type == e1000_82571) {
475 e1000_set_laa_state_82571(hw, TRUE);
476 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
479 /* Initialize the hardware */
480 if (em_hardware_init(hw)) {
481 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
485 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
487 /* Configure for OS presence */
488 em_init_manageability(hw);
492 ret = eth_em_rx_init(dev);
494 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
495 em_dev_clear_queues(dev);
499 e1000_clear_hw_cntrs_base_generic(hw);
501 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
502 ETH_VLAN_EXTEND_MASK;
503 eth_em_vlan_offload_set(dev, mask);
505 /* Set Interrupt Throttling Rate to maximum allowed value. */
506 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
508 /* Setup link speed and duplex */
509 switch (dev->data->dev_conf.link_speed) {
510 case ETH_LINK_SPEED_AUTONEG:
511 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
512 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
513 else if (dev->data->dev_conf.link_duplex ==
514 ETH_LINK_HALF_DUPLEX)
515 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
516 else if (dev->data->dev_conf.link_duplex ==
517 ETH_LINK_FULL_DUPLEX)
518 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
520 goto error_invalid_config;
522 case ETH_LINK_SPEED_10:
523 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
524 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
525 else if (dev->data->dev_conf.link_duplex ==
526 ETH_LINK_HALF_DUPLEX)
527 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
528 else if (dev->data->dev_conf.link_duplex ==
529 ETH_LINK_FULL_DUPLEX)
530 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
532 goto error_invalid_config;
534 case ETH_LINK_SPEED_100:
535 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
536 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
537 else if (dev->data->dev_conf.link_duplex ==
538 ETH_LINK_HALF_DUPLEX)
539 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
540 else if (dev->data->dev_conf.link_duplex ==
541 ETH_LINK_FULL_DUPLEX)
542 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
544 goto error_invalid_config;
546 case ETH_LINK_SPEED_1000:
547 if ((dev->data->dev_conf.link_duplex ==
548 ETH_LINK_AUTONEG_DUPLEX) ||
549 (dev->data->dev_conf.link_duplex ==
550 ETH_LINK_FULL_DUPLEX))
551 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
553 goto error_invalid_config;
555 case ETH_LINK_SPEED_10000:
557 goto error_invalid_config;
559 e1000_setup_link(hw);
561 /* check if lsc interrupt feature is enabled */
562 if (dev->data->dev_conf.intr_conf.lsc != 0) {
563 ret = eth_em_interrupt_setup(dev);
565 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
566 em_dev_clear_queues(dev);
571 PMD_INIT_LOG(DEBUG, "<<");
575 error_invalid_config:
576 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port "
577 "%u\n", dev->data->dev_conf.link_speed,
578 dev->data->dev_conf.link_duplex, dev->data->port_id);
579 em_dev_clear_queues(dev);
583 /*********************************************************************
585 * This routine disables all traffic on the adapter by issuing a
586 * global reset on the MAC.
588 **********************************************************************/
590 eth_em_stop(struct rte_eth_dev *dev)
592 struct rte_eth_link link;
593 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
597 if (hw->mac.type >= e1000_82544)
598 E1000_WRITE_REG(hw, E1000_WUC, 0);
600 /* Power down the phy. Needed to make the link go down */
601 e1000_power_down_phy(hw);
603 em_dev_clear_queues(dev);
605 /* clear the recorded link status */
606 memset(&link, 0, sizeof(link));
607 rte_em_dev_atomic_write_link_status(dev, &link);
611 eth_em_close(struct rte_eth_dev *dev)
613 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
616 e1000_phy_hw_reset(hw);
617 em_release_manageability(hw);
618 em_hw_control_release(hw);
622 em_get_rx_buffer_size(struct e1000_hw *hw)
624 uint32_t rx_buf_size;
626 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
630 /*********************************************************************
632 * Initialize the hardware
634 **********************************************************************/
636 em_hardware_init(struct e1000_hw *hw)
638 uint32_t rx_buf_size;
641 /* Issue a global reset */
644 /* Let the firmware know the OS is in control */
645 em_hw_control_acquire(hw);
648 * These parameters control the automatic generation (Tx) and
649 * response (Rx) to Ethernet PAUSE frames.
650 * - High water mark should allow for at least two standard size (1518)
651 * frames to be received after sending an XOFF.
652 * - Low water mark works best when it is very near the high water mark.
653 * This allows the receiver to restart by sending XON when it has
654 * drained a bit. Here we use an arbitrary value of 1500 which will
655 * restart after one full frame is pulled from the buffer. There
656 * could be several smaller frames in the buffer and if so they will
657 * not trigger the XON until their total number reduces the buffer
659 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
661 rx_buf_size = em_get_rx_buffer_size(hw);
663 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
664 hw->fc.low_water = hw->fc.high_water - 1500;
666 if (hw->mac.type == e1000_80003es2lan)
667 hw->fc.pause_time = UINT16_MAX;
669 hw->fc.pause_time = EM_FC_PAUSE_TIME;
673 /* Set Flow control, use the tunable location if sane */
674 if (em_fc_setting <= e1000_fc_full)
675 hw->fc.requested_mode = em_fc_setting;
677 hw->fc.requested_mode = e1000_fc_none;
679 /* Workaround: no TX flow ctrl for PCH */
680 if (hw->mac.type == e1000_pchlan)
681 hw->fc.requested_mode = e1000_fc_rx_pause;
683 /* Override - settings for PCH2LAN, ya its magic :) */
684 if (hw->mac.type == e1000_pch2lan) {
685 hw->fc.high_water = 0x5C20;
686 hw->fc.low_water = 0x5048;
687 hw->fc.pause_time = 0x0650;
688 hw->fc.refresh_time = 0x0400;
691 diag = e1000_init_hw(hw);
694 e1000_check_for_link(hw);
698 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
700 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
702 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
703 struct e1000_hw_stats *stats =
704 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
707 if(hw->phy.media_type == e1000_media_type_copper ||
708 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
709 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
710 stats->sec += E1000_READ_REG(hw, E1000_SEC);
713 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
714 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
715 stats->scc += E1000_READ_REG(hw, E1000_SCC);
716 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
718 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
719 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
720 stats->colc += E1000_READ_REG(hw, E1000_COLC);
721 stats->dc += E1000_READ_REG(hw, E1000_DC);
722 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
723 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
724 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
727 * For watchdog management we need to know if we have been
728 * paused during the last interval, so capture that here.
730 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
731 stats->xoffrxc += pause_frames;
732 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
733 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
734 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
735 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
736 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
737 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
738 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
739 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
740 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
741 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
742 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
743 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
746 * For the 64-bit byte counters the low dword must be read first.
747 * Both registers clear on the read of the high dword.
750 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
751 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
752 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
753 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
755 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
756 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
757 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
758 stats->roc += E1000_READ_REG(hw, E1000_ROC);
759 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
761 stats->tor += E1000_READ_REG(hw, E1000_TORH);
762 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
764 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
765 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
766 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
767 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
768 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
769 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
770 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
771 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
772 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
773 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
775 /* Interrupt Counts */
777 if (hw->mac.type >= e1000_82571) {
778 stats->iac += E1000_READ_REG(hw, E1000_IAC);
779 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
780 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
781 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
782 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
783 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
784 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
785 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
786 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
789 if (hw->mac.type >= e1000_82543) {
790 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
791 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
792 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
793 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
794 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
795 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
798 if (rte_stats == NULL)
802 rte_stats->ibadcrc = stats->crcerrs;
803 rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
804 rte_stats->imissed = stats->mpc;
805 rte_stats->ierrors = rte_stats->ibadcrc +
808 stats->rxerrc + stats->algnerrc + stats->cexterr;
811 rte_stats->oerrors = stats->ecol + stats->latecol;
813 rte_stats->ipackets = stats->gprc;
814 rte_stats->opackets = stats->gptc;
815 rte_stats->ibytes = stats->gorc;
816 rte_stats->obytes = stats->gotc;
818 /* XON/XOFF pause frames stats registers */
819 rte_stats->tx_pause_xon = stats->xontxc;
820 rte_stats->rx_pause_xon = stats->xonrxc;
821 rte_stats->tx_pause_xoff = stats->xofftxc;
822 rte_stats->rx_pause_xoff = stats->xoffrxc;
826 eth_em_stats_reset(struct rte_eth_dev *dev)
828 struct e1000_hw_stats *hw_stats =
829 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
831 /* HW registers are cleared on read */
832 eth_em_stats_get(dev, NULL);
834 /* Reset software totals */
835 memset(hw_stats, 0, sizeof(*hw_stats));
839 em_get_max_pktlen(const struct e1000_hw *hw)
841 switch (hw->mac.type) {
848 case e1000_80003es2lan: /* 9K Jumbo Frame size */
852 /* Adapters that do not support jumbo frames */
855 return (ETHER_MAX_LEN);
857 return (MAX_JUMBO_FRAME_SIZE);
862 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
864 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
866 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
867 dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
868 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
871 * Starting with 631xESB hw supports 2 TX/RX queues per port.
872 * Unfortunatelly, all these nics have just one TX context.
873 * So we have few choises for TX:
874 * - Use just one TX queue.
875 * - Allow cksum offload only for one TX queue.
876 * - Don't allow TX cksum offload at all.
877 * For now, option #1 was chosen.
878 * To use second RX queue we have to use extended RX descriptor
879 * (Multiple Receive Queues are mutually exclusive with UDP
880 * fragmentation and are not supported when a legacy receive
881 * descriptor format is used).
882 * Which means separate RX routinies - as legacy nics (82540, 82545)
883 * don't support extended RXD.
884 * To avoid it we support just one RX queue for now (no RSS).
887 dev_info->max_rx_queues = 1;
888 dev_info->max_tx_queues = 1;
891 /* return 0 means link status changed, -1 means not changed */
893 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
895 struct e1000_hw *hw =
896 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
897 struct rte_eth_link link, old;
898 int link_check, count;
901 hw->mac.get_link_status = 1;
903 /* possible wait-to-complete in up to 9 seconds */
904 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
905 /* Read the real link status */
906 switch (hw->phy.media_type) {
907 case e1000_media_type_copper:
908 /* Do the work to read phy */
909 e1000_check_for_link(hw);
910 link_check = !hw->mac.get_link_status;
913 case e1000_media_type_fiber:
914 e1000_check_for_link(hw);
915 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
919 case e1000_media_type_internal_serdes:
920 e1000_check_for_link(hw);
921 link_check = hw->mac.serdes_has_link;
927 if (link_check || wait_to_complete == 0)
929 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
931 memset(&link, 0, sizeof(link));
932 rte_em_dev_atomic_read_link_status(dev, &link);
935 /* Now we check if a transition has happened */
936 if (link_check && (link.link_status == 0)) {
937 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
939 link.link_status = 1;
940 } else if (!link_check && (link.link_status == 1)) {
942 link.link_duplex = 0;
943 link.link_status = 0;
945 rte_em_dev_atomic_write_link_status(dev, &link);
948 if (old.link_status == link.link_status)
956 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
957 * For ASF and Pass Through versions of f/w this means
958 * that the driver is loaded. For AMT version type f/w
959 * this means that the network i/f is open.
962 em_hw_control_acquire(struct e1000_hw *hw)
964 uint32_t ctrl_ext, swsm;
966 /* Let firmware know the driver has taken over */
967 if (hw->mac.type == e1000_82573) {
968 swsm = E1000_READ_REG(hw, E1000_SWSM);
969 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
972 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
973 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
974 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
979 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
980 * For ASF and Pass Through versions of f/w this means that the
981 * driver is no longer loaded. For AMT versions of the
982 * f/w this means that the network i/f is closed.
985 em_hw_control_release(struct e1000_hw *hw)
987 uint32_t ctrl_ext, swsm;
989 /* Let firmware taken over control of h/w */
990 if (hw->mac.type == e1000_82573) {
991 swsm = E1000_READ_REG(hw, E1000_SWSM);
992 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
994 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
995 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
996 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1001 * Bit of a misnomer, what this really means is
1002 * to enable OS management of the system... aka
1003 * to disable special hardware management features.
1006 em_init_manageability(struct e1000_hw *hw)
1008 if (e1000_enable_mng_pass_thru(hw)) {
1009 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1010 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1012 /* disable hardware interception of ARP */
1013 manc &= ~(E1000_MANC_ARP_EN);
1015 /* enable receiving management packets to the host */
1016 manc |= E1000_MANC_EN_MNG2HOST;
1017 manc2h |= 1 << 5; /* Mng Port 623 */
1018 manc2h |= 1 << 6; /* Mng Port 664 */
1019 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1020 E1000_WRITE_REG(hw, E1000_MANC, manc);
1025 * Give control back to hardware management
1026 * controller if there is one.
1029 em_release_manageability(struct e1000_hw *hw)
1033 if (e1000_enable_mng_pass_thru(hw)) {
1034 manc = E1000_READ_REG(hw, E1000_MANC);
1036 /* re-enable hardware interception of ARP */
1037 manc |= E1000_MANC_ARP_EN;
1038 manc &= ~E1000_MANC_EN_MNG2HOST;
1040 E1000_WRITE_REG(hw, E1000_MANC, manc);
1045 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1047 struct e1000_hw *hw =
1048 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051 rctl = E1000_READ_REG(hw, E1000_RCTL);
1052 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1053 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1057 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1059 struct e1000_hw *hw =
1060 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1063 rctl = E1000_READ_REG(hw, E1000_RCTL);
1064 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1065 if (dev->data->all_multicast == 1)
1066 rctl |= E1000_RCTL_MPE;
1068 rctl &= (~E1000_RCTL_MPE);
1069 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1073 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1075 struct e1000_hw *hw =
1076 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1079 rctl = E1000_READ_REG(hw, E1000_RCTL);
1080 rctl |= E1000_RCTL_MPE;
1081 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1085 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1087 struct e1000_hw *hw =
1088 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091 if (dev->data->promiscuous == 1)
1092 return; /* must remain in all_multicast mode */
1093 rctl = E1000_READ_REG(hw, E1000_RCTL);
1094 rctl &= (~E1000_RCTL_MPE);
1095 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1099 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1101 struct e1000_hw *hw =
1102 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103 struct e1000_vfta * shadow_vfta =
1104 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1109 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1110 E1000_VFTA_ENTRY_MASK);
1111 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1112 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1117 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1119 /* update local VFTA copy */
1120 shadow_vfta->vfta[vid_idx] = vfta;
1126 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1128 struct e1000_hw *hw =
1129 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1132 /* Filter Table Disable */
1133 reg = E1000_READ_REG(hw, E1000_RCTL);
1134 reg &= ~E1000_RCTL_CFIEN;
1135 reg &= ~E1000_RCTL_VFE;
1136 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1140 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1142 struct e1000_hw *hw =
1143 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1144 struct e1000_vfta * shadow_vfta =
1145 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1149 /* Filter Table Enable, CFI not used for packet acceptance */
1150 reg = E1000_READ_REG(hw, E1000_RCTL);
1151 reg &= ~E1000_RCTL_CFIEN;
1152 reg |= E1000_RCTL_VFE;
1153 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1155 /* restore vfta from local copy */
1156 for (i = 0; i < IGB_VFTA_SIZE; i++)
1157 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1161 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1163 struct e1000_hw *hw =
1164 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167 /* VLAN Mode Disable */
1168 reg = E1000_READ_REG(hw, E1000_CTRL);
1169 reg &= ~E1000_CTRL_VME;
1170 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1175 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1177 struct e1000_hw *hw =
1178 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181 /* VLAN Mode Enable */
1182 reg = E1000_READ_REG(hw, E1000_CTRL);
1183 reg |= E1000_CTRL_VME;
1184 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1188 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1190 if(mask & ETH_VLAN_STRIP_MASK){
1191 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1192 em_vlan_hw_strip_enable(dev);
1194 em_vlan_hw_strip_disable(dev);
1197 if(mask & ETH_VLAN_FILTER_MASK){
1198 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1199 em_vlan_hw_filter_enable(dev);
1201 em_vlan_hw_filter_disable(dev);
1206 em_intr_disable(struct e1000_hw *hw)
1208 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1212 * It enables the interrupt mask and then enable the interrupt.
1215 * Pointer to struct rte_eth_dev.
1218 * - On success, zero.
1219 * - On failure, a negative value.
1222 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1224 struct e1000_hw *hw =
1225 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1228 rte_intr_enable(&(dev->pci_dev->intr_handle));
1233 * It reads ICR and gets interrupt causes, check it and set a bit flag
1234 * to update link status.
1237 * Pointer to struct rte_eth_dev.
1240 * - On success, zero.
1241 * - On failure, a negative value.
1244 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1247 struct e1000_hw *hw =
1248 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249 struct e1000_interrupt *intr =
1250 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1252 /* read-on-clear nic registers here */
1253 icr = E1000_READ_REG(hw, E1000_ICR);
1254 if (icr & E1000_ICR_LSC) {
1255 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1262 * It executes link_update after knowing an interrupt is prsent.
1265 * Pointer to struct rte_eth_dev.
1268 * - On success, zero.
1269 * - On failure, a negative value.
1272 eth_em_interrupt_action(struct rte_eth_dev *dev)
1274 struct e1000_hw *hw =
1275 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 struct e1000_interrupt *intr =
1277 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1278 uint32_t tctl, rctl;
1279 struct rte_eth_link link;
1282 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1285 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1286 rte_intr_enable(&(dev->pci_dev->intr_handle));
1288 /* set get_link_status to check register later */
1289 hw->mac.get_link_status = 1;
1290 ret = eth_em_link_update(dev, 0);
1292 /* check if link has changed */
1296 memset(&link, 0, sizeof(link));
1297 rte_em_dev_atomic_read_link_status(dev, &link);
1298 if (link.link_status) {
1300 " Port %d: Link Up - speed %u Mbps - %s\n",
1301 dev->data->port_id, (unsigned)link.link_speed,
1302 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1303 "full-duplex" : "half-duplex");
1305 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1306 dev->data->port_id);
1308 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1309 dev->pci_dev->addr.domain,
1310 dev->pci_dev->addr.bus,
1311 dev->pci_dev->addr.devid,
1312 dev->pci_dev->addr.function);
1313 tctl = E1000_READ_REG(hw, E1000_TCTL);
1314 rctl = E1000_READ_REG(hw, E1000_RCTL);
1315 if (link.link_status) {
1317 tctl |= E1000_TCTL_EN;
1318 rctl |= E1000_RCTL_EN;
1321 tctl &= ~E1000_TCTL_EN;
1322 rctl &= ~E1000_RCTL_EN;
1324 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1325 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1326 E1000_WRITE_FLUSH(hw);
1332 * Interrupt handler which shall be registered at first.
1335 * Pointer to interrupt handle.
1337 * The address of parameter (struct rte_eth_dev *) regsitered before.
1343 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1346 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1348 eth_em_interrupt_get_status(dev);
1349 eth_em_interrupt_action(dev);
1350 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1354 eth_em_led_on(struct rte_eth_dev *dev)
1356 struct e1000_hw *hw;
1358 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1359 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1363 eth_em_led_off(struct rte_eth_dev *dev)
1365 struct e1000_hw *hw;
1367 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1372 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1374 struct e1000_hw *hw;
1379 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380 fc_conf->pause_time = hw->fc.pause_time;
1381 fc_conf->high_water = hw->fc.high_water;
1382 fc_conf->low_water = hw->fc.low_water;
1383 fc_conf->send_xon = hw->fc.send_xon;
1384 fc_conf->autoneg = hw->mac.autoneg;
1387 * Return rx_pause and tx_pause status according to actual setting of
1388 * the TFCE and RFCE bits in the CTRL register.
1390 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1391 if (ctrl & E1000_CTRL_TFCE)
1396 if (ctrl & E1000_CTRL_RFCE)
1401 if (rx_pause && tx_pause)
1402 fc_conf->mode = RTE_FC_FULL;
1404 fc_conf->mode = RTE_FC_RX_PAUSE;
1406 fc_conf->mode = RTE_FC_TX_PAUSE;
1408 fc_conf->mode = RTE_FC_NONE;
1414 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1416 struct e1000_hw *hw;
1418 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1424 uint32_t rx_buf_size;
1425 uint32_t max_high_water;
1428 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429 if (fc_conf->autoneg != hw->mac.autoneg)
1431 rx_buf_size = em_get_rx_buffer_size(hw);
1432 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1434 /* At least reserve one Ethernet frame for watermark */
1435 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1436 if ((fc_conf->high_water > max_high_water) ||
1437 (fc_conf->high_water < fc_conf->low_water)) {
1438 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1439 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1443 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1444 hw->fc.pause_time = fc_conf->pause_time;
1445 hw->fc.high_water = fc_conf->high_water;
1446 hw->fc.low_water = fc_conf->low_water;
1447 hw->fc.send_xon = fc_conf->send_xon;
1449 err = e1000_setup_link_generic(hw);
1450 if (err == E1000_SUCCESS) {
1452 /* check if we want to forward MAC frames - driver doesn't have native
1453 * capability to do that, so we'll write the registers ourselves */
1455 rctl = E1000_READ_REG(hw, E1000_RCTL);
1457 /* set or clear MFLCN.PMCF bit depending on configuration */
1458 if (fc_conf->mac_ctrl_frame_fwd != 0)
1459 rctl |= E1000_RCTL_PMCF;
1461 rctl &= ~E1000_RCTL_PMCF;
1463 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1464 E1000_WRITE_FLUSH(hw);
1469 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1474 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1475 uint32_t index, __rte_unused uint32_t pool)
1477 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1483 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1485 uint8_t addr[ETHER_ADDR_LEN];
1486 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488 memset(addr, 0, sizeof(addr));
1490 e1000_rar_set(hw, addr, index);
1494 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1496 struct rte_eth_dev_info dev_info;
1497 struct e1000_hw *hw;
1498 uint32_t frame_size;
1501 eth_em_infos_get(dev, &dev_info);
1502 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1504 /* check that mtu is within the allowed range */
1505 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1508 /* refuse mtu that requires the support of scattered packets when this
1509 * feature has not been enabled before. */
1510 if (!dev->data->scattered_rx &&
1511 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1514 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515 rctl = E1000_READ_REG(hw, E1000_RCTL);
1517 /* switch to jumbo mode if needed */
1518 if (frame_size > ETHER_MAX_LEN) {
1519 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1520 rctl |= E1000_RCTL_LPE;
1522 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1523 rctl &= ~E1000_RCTL_LPE;
1525 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1527 /* update max frame size */
1528 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1532 struct rte_driver em_pmd_drv = {
1534 .init = rte_em_pmd_init,
1537 PMD_REGISTER_DRIVER(em_pmd_drv);