1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0002
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
142 i40e_aqc_opc_set_cppm_configuration = 0x0103,
143 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
144 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
147 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
148 i40e_aqc_opc_mac_address_read = 0x0107,
149 i40e_aqc_opc_mac_address_write = 0x0108,
152 i40e_aqc_opc_clear_pxe_mode = 0x0110,
154 /* internal switch commands */
155 i40e_aqc_opc_get_switch_config = 0x0200,
156 i40e_aqc_opc_add_statistics = 0x0201,
157 i40e_aqc_opc_remove_statistics = 0x0202,
158 i40e_aqc_opc_set_port_parameters = 0x0203,
159 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
161 i40e_aqc_opc_add_vsi = 0x0210,
162 i40e_aqc_opc_update_vsi_parameters = 0x0211,
163 i40e_aqc_opc_get_vsi_parameters = 0x0212,
165 i40e_aqc_opc_add_pv = 0x0220,
166 i40e_aqc_opc_update_pv_parameters = 0x0221,
167 i40e_aqc_opc_get_pv_parameters = 0x0222,
169 i40e_aqc_opc_add_veb = 0x0230,
170 i40e_aqc_opc_update_veb_parameters = 0x0231,
171 i40e_aqc_opc_get_veb_parameters = 0x0232,
173 i40e_aqc_opc_delete_element = 0x0243,
175 i40e_aqc_opc_add_macvlan = 0x0250,
176 i40e_aqc_opc_remove_macvlan = 0x0251,
177 i40e_aqc_opc_add_vlan = 0x0252,
178 i40e_aqc_opc_remove_vlan = 0x0253,
179 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
180 i40e_aqc_opc_add_tag = 0x0255,
181 i40e_aqc_opc_remove_tag = 0x0256,
182 i40e_aqc_opc_add_multicast_etag = 0x0257,
183 i40e_aqc_opc_remove_multicast_etag = 0x0258,
184 i40e_aqc_opc_update_tag = 0x0259,
185 i40e_aqc_opc_add_control_packet_filter = 0x025A,
186 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
187 i40e_aqc_opc_add_cloud_filters = 0x025C,
188 i40e_aqc_opc_remove_cloud_filters = 0x025D,
190 i40e_aqc_opc_add_mirror_rule = 0x0260,
191 i40e_aqc_opc_delete_mirror_rule = 0x0261,
194 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
195 i40e_aqc_opc_dcb_updated = 0x0302,
198 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
199 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
200 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
201 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
202 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
203 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
205 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
206 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
207 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
208 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
209 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
210 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
211 i40e_aqc_opc_query_port_ets_config = 0x0419,
212 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
213 i40e_aqc_opc_suspend_port_tx = 0x041B,
214 i40e_aqc_opc_resume_port_tx = 0x041C,
215 i40e_aqc_opc_configure_partition_bw = 0x041D,
218 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
219 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
222 i40e_aqc_opc_get_phy_abilities = 0x0600,
223 i40e_aqc_opc_set_phy_config = 0x0601,
224 i40e_aqc_opc_set_mac_config = 0x0603,
225 i40e_aqc_opc_set_link_restart_an = 0x0605,
226 i40e_aqc_opc_get_link_status = 0x0607,
227 i40e_aqc_opc_set_phy_int_mask = 0x0613,
228 i40e_aqc_opc_get_local_advt_reg = 0x0614,
229 i40e_aqc_opc_set_local_advt_reg = 0x0615,
230 i40e_aqc_opc_get_partner_advt = 0x0616,
231 i40e_aqc_opc_set_lb_modes = 0x0618,
232 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
233 i40e_aqc_opc_set_phy_debug = 0x0622,
234 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
237 i40e_aqc_opc_nvm_read = 0x0701,
238 i40e_aqc_opc_nvm_erase = 0x0702,
239 i40e_aqc_opc_nvm_update = 0x0703,
240 i40e_aqc_opc_nvm_config_read = 0x0704,
241 i40e_aqc_opc_nvm_config_write = 0x0705,
243 /* virtualization commands */
244 i40e_aqc_opc_send_msg_to_pf = 0x0801,
245 i40e_aqc_opc_send_msg_to_vf = 0x0802,
246 i40e_aqc_opc_send_msg_to_peer = 0x0803,
248 /* alternate structure */
249 i40e_aqc_opc_alternate_write = 0x0900,
250 i40e_aqc_opc_alternate_write_indirect = 0x0901,
251 i40e_aqc_opc_alternate_read = 0x0902,
252 i40e_aqc_opc_alternate_read_indirect = 0x0903,
253 i40e_aqc_opc_alternate_write_done = 0x0904,
254 i40e_aqc_opc_alternate_set_mode = 0x0905,
255 i40e_aqc_opc_alternate_clear_port = 0x0906,
258 i40e_aqc_opc_lldp_get_mib = 0x0A00,
259 i40e_aqc_opc_lldp_update_mib = 0x0A01,
260 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
261 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
262 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
263 i40e_aqc_opc_lldp_stop = 0x0A05,
264 i40e_aqc_opc_lldp_start = 0x0A06,
266 /* Tunnel commands */
267 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
268 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
269 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
272 i40e_aqc_opc_event_lan_overflow = 0x1001,
275 i40e_aqc_opc_oem_parameter_change = 0xFE00,
276 i40e_aqc_opc_oem_device_status_change = 0xFE01,
279 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
280 i40e_aqc_opc_debug_set_mode = 0xFF01,
281 i40e_aqc_opc_debug_read_reg = 0xFF03,
282 i40e_aqc_opc_debug_write_reg = 0xFF04,
283 i40e_aqc_opc_debug_modify_reg = 0xFF07,
284 i40e_aqc_opc_debug_dump_internals = 0xFF08,
285 i40e_aqc_opc_debug_modify_internals = 0xFF09,
288 /* command structures and indirect data structures */
290 /* Structure naming conventions:
291 * - no suffix for direct command descriptor structures
292 * - _data for indirect sent data
293 * - _resp for indirect return data (data which is both will use _data)
294 * - _completion for direct return data
295 * - _element_ for repeated elements (may also be _data or _resp)
297 * Command structures are expected to overlay the params.raw member of the basic
298 * descriptor, and as such cannot exceed 16 bytes in length.
301 /* This macro is used to generate a compilation error if a structure
302 * is not exactly the correct length. It gives a divide by zero error if the
303 * structure is not of the correct size, otherwise it creates an enum that is
306 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
307 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
309 /* This macro is used extensively to ensure that command structures are 16
310 * bytes in length as they have to map to the raw array of that size.
312 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
314 /* internal (0x00XX) commands */
316 /* Get version (direct 0x0001) */
317 struct i40e_aqc_get_version {
326 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
328 /* Send driver version (indirect 0x0002) */
329 struct i40e_aqc_driver_version {
333 u8 driver_subbuild_ver;
339 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
341 /* Queue Shutdown (direct 0x0003) */
342 struct i40e_aqc_queue_shutdown {
343 __le32 driver_unloading;
344 #define I40E_AQ_DRIVER_UNLOADING 0x1
348 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
350 /* Set PF context (0x0004, direct) */
351 struct i40e_aqc_set_pf_context {
356 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
358 /* Request resource ownership (direct 0x0008)
359 * Release resource ownership (direct 0x0009)
361 #define I40E_AQ_RESOURCE_NVM 1
362 #define I40E_AQ_RESOURCE_SDP 2
363 #define I40E_AQ_RESOURCE_ACCESS_READ 1
364 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
365 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
366 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
368 struct i40e_aqc_request_resource {
372 __le32 resource_number;
376 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
378 /* Get function capabilities (indirect 0x000A)
379 * Get device capabilities (indirect 0x000B)
381 struct i40e_aqc_list_capabilites {
383 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
391 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
393 struct i40e_aqc_list_capabilities_element_resp {
405 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
406 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
407 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
408 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
409 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
410 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
411 #define I40E_AQ_CAP_ID_SRIOV 0x0012
412 #define I40E_AQ_CAP_ID_VF 0x0013
413 #define I40E_AQ_CAP_ID_VMDQ 0x0014
414 #define I40E_AQ_CAP_ID_8021QBG 0x0015
415 #define I40E_AQ_CAP_ID_8021QBR 0x0016
416 #define I40E_AQ_CAP_ID_VSI 0x0017
417 #define I40E_AQ_CAP_ID_DCB 0x0018
418 #define I40E_AQ_CAP_ID_FCOE 0x0021
419 #define I40E_AQ_CAP_ID_RSS 0x0040
420 #define I40E_AQ_CAP_ID_RXQ 0x0041
421 #define I40E_AQ_CAP_ID_TXQ 0x0042
422 #define I40E_AQ_CAP_ID_MSIX 0x0043
423 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
424 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
425 #define I40E_AQ_CAP_ID_1588 0x0046
426 #define I40E_AQ_CAP_ID_IWARP 0x0051
427 #define I40E_AQ_CAP_ID_LED 0x0061
428 #define I40E_AQ_CAP_ID_SDP 0x0062
429 #define I40E_AQ_CAP_ID_MDIO 0x0063
430 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
431 #define I40E_AQ_CAP_ID_CEM 0x00F2
433 /* Set CPPM Configuration (direct 0x0103) */
434 struct i40e_aqc_cppm_configuration {
435 __le16 command_flags;
436 #define I40E_AQ_CPPM_EN_LTRC 0x0800
437 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
438 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
439 #define I40E_AQ_CPPM_EN_HPTC 0x4000
440 #define I40E_AQ_CPPM_EN_DMARC 0x8000
449 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
451 /* Set ARP Proxy command / response (indirect 0x0104) */
452 struct i40e_aqc_arp_proxy_data {
453 __le16 command_flags;
454 #define I40E_AQ_ARP_INIT_IPV4 0x0008
455 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
456 #define I40E_AQ_ARP_ENA 0x0020
457 #define I40E_AQ_ARP_ADD_IPV4 0x0040
458 #define I40E_AQ_ARP_DEL_IPV4 0x0080
465 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
466 struct i40e_aqc_ns_proxy_data {
467 __le16 table_idx_mac_addr_0;
468 __le16 table_idx_mac_addr_1;
469 __le16 table_idx_ipv6_0;
470 __le16 table_idx_ipv6_1;
472 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
473 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
474 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
475 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
476 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
477 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
478 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
479 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
480 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
481 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
482 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
485 u8 local_mac_addr[6];
486 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
490 /* Manage LAA Command (0x0106) - obsolete */
491 struct i40e_aqc_mng_laa {
492 __le16 command_flags;
493 #define I40E_AQ_LAA_FLAG_WR 0x8000
500 /* Manage MAC Address Read Command (indirect 0x0107) */
501 struct i40e_aqc_mac_address_read {
502 __le16 command_flags;
503 #define I40E_AQC_LAN_ADDR_VALID 0x10
504 #define I40E_AQC_SAN_ADDR_VALID 0x20
505 #define I40E_AQC_PORT_ADDR_VALID 0x40
506 #define I40E_AQC_WOL_ADDR_VALID 0x80
507 #define I40E_AQC_ADDR_VALID_MASK 0xf0
513 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
515 struct i40e_aqc_mac_address_read_data {
522 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
524 /* Manage MAC Address Write Command (0x0108) */
525 struct i40e_aqc_mac_address_write {
526 __le16 command_flags;
527 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
528 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
529 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
530 #define I40E_AQC_WRITE_TYPE_MASK 0xc000
536 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
538 /* PXE commands (0x011x) */
540 /* Clear PXE Command and response (direct 0x0110) */
541 struct i40e_aqc_clear_pxe {
546 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
548 /* Switch configuration commands (0x02xx) */
550 /* Used by many indirect commands that only pass an seid and a buffer in the
553 struct i40e_aqc_switch_seid {
560 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
562 /* Get Switch Configuration command (indirect 0x0200)
563 * uses i40e_aqc_switch_seid for the descriptor
565 struct i40e_aqc_get_switch_config_header_resp {
571 struct i40e_aqc_switch_config_element_resp {
573 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
574 #define I40E_AQ_SW_ELEM_TYPE_PF 2
575 #define I40E_AQ_SW_ELEM_TYPE_VF 3
576 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
577 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
578 #define I40E_AQ_SW_ELEM_TYPE_PV 16
579 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
580 #define I40E_AQ_SW_ELEM_TYPE_PA 18
581 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
583 #define I40E_AQ_SW_ELEM_REV_1 1
586 __le16 downlink_seid;
589 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
590 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
591 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
596 /* Get Switch Configuration (indirect 0x0200)
597 * an array of elements are returned in the response buffer
598 * the first in the array is the header, remainder are elements
600 struct i40e_aqc_get_switch_config_resp {
601 struct i40e_aqc_get_switch_config_header_resp header;
602 struct i40e_aqc_switch_config_element_resp element[1];
605 /* Add Statistics (direct 0x0201)
606 * Remove Statistics (direct 0x0202)
608 struct i40e_aqc_add_remove_statistics {
615 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
617 /* Set Port Parameters command (direct 0x0203) */
618 struct i40e_aqc_set_port_parameters {
619 __le16 command_flags;
620 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
621 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
622 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
623 __le16 bad_frame_vsi;
624 __le16 default_seid; /* reserved for command */
628 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
630 /* Get Switch Resource Allocation (indirect 0x0204) */
631 struct i40e_aqc_get_switch_resource_alloc {
632 u8 num_entries; /* reserved for command */
638 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
640 /* expect an array of these structs in the response buffer */
641 struct i40e_aqc_switch_resource_alloc_element_resp {
643 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
644 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
645 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
646 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
647 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
648 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
649 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
650 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
651 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
652 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
653 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
654 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
655 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
656 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
657 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
658 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
659 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
660 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
661 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
666 __le16 total_unalloced;
670 /* Add VSI (indirect 0x0210)
671 * this indirect command uses struct i40e_aqc_vsi_properties_data
672 * as the indirect buffer (128 bytes)
674 * Update VSI (indirect 0x211)
675 * uses the same data structure as Add VSI
677 * Get VSI (indirect 0x0212)
678 * uses the same completion and data structure as Add VSI
680 struct i40e_aqc_add_get_update_vsi {
683 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
684 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
685 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
690 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
691 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
692 #define I40E_AQ_VSI_TYPE_VF 0x0
693 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
694 #define I40E_AQ_VSI_TYPE_PF 0x2
695 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
696 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
701 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
703 struct i40e_aqc_add_get_update_vsi_completion {
712 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
714 struct i40e_aqc_vsi_properties_data {
715 /* first 96 byte are written by SW */
716 __le16 valid_sections;
717 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
718 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
719 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
720 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
721 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
722 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
723 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
724 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
725 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
726 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
728 __le16 switch_id; /* 12bit id combined with flags below */
729 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
730 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
731 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
732 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
733 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
735 /* security section */
737 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
738 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
739 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
742 __le16 pvid; /* VLANS include priority bits */
745 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
746 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
747 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
748 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
749 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
750 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
751 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
752 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
753 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
754 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
755 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
756 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
757 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
758 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
759 u8 pvlan_reserved[3];
760 /* ingress egress up sections */
761 __le32 ingress_table; /* bitmap, 3 bits per up */
762 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
763 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
764 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
765 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
766 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
767 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
768 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
769 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
770 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
771 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
772 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
773 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
774 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
775 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
776 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
777 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
778 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
779 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
780 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
781 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
782 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
783 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
784 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
785 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
786 __le32 egress_table; /* same defines as for ingress table */
787 /* cascaded PV section */
790 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
791 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
792 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
793 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
794 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
795 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
796 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
797 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
798 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
800 /* queue mapping section */
801 __le16 mapping_flags;
802 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
803 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
804 __le16 queue_mapping[16];
805 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
806 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
807 __le16 tc_mapping[8];
808 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
809 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
810 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
811 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
812 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
813 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
814 /* queueing option section */
815 u8 queueing_opt_flags;
816 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
817 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
818 u8 queueing_opt_reserved[3];
819 /* scheduler section */
822 /* outer up section */
823 __le32 outer_up_table; /* same structure and defines as ingress table */
825 /* last 32 bytes are written by FW */
827 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
828 __le16 stat_counter_idx;
830 u8 resp_reserved[12];
833 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
835 /* Add Port Virtualizer (direct 0x0220)
836 * also used for update PV (direct 0x0221) but only flags are used
837 * (IS_CTRL_PORT only works on add PV)
839 struct i40e_aqc_add_update_pv {
840 __le16 command_flags;
841 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
842 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
843 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
844 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
846 __le16 connected_seid;
850 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
852 struct i40e_aqc_add_update_pv_completion {
853 /* reserved for update; for add also encodes error if rc == ENOSPC */
855 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
856 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
857 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
858 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
862 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
864 /* Get PV Params (direct 0x0222)
865 * uses i40e_aqc_switch_seid for the descriptor
868 struct i40e_aqc_get_pv_params_completion {
871 __le16 pv_flags; /* same flags as add_pv */
872 #define I40E_AQC_GET_PV_PV_TYPE 0x1
873 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
874 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
876 __le16 default_port_seid;
879 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
881 /* Add VEB (direct 0x0230) */
882 struct i40e_aqc_add_veb {
884 __le16 downlink_seid;
886 #define I40E_AQC_ADD_VEB_FLOATING 0x1
887 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
888 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
889 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
890 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
891 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
892 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
897 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
899 struct i40e_aqc_add_veb_completion {
902 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
904 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
905 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
906 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
907 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
908 __le16 statistic_index;
913 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
915 /* Get VEB Parameters (direct 0x0232)
916 * uses i40e_aqc_switch_seid for the descriptor
918 struct i40e_aqc_get_veb_parameters_completion {
921 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
922 __le16 statistic_index;
928 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
930 /* Delete Element (direct 0x0243)
931 * uses the generic i40e_aqc_switch_seid
934 /* Add MAC-VLAN (indirect 0x0250) */
936 /* used for the command for most vlan commands */
937 struct i40e_aqc_macvlan {
938 __le16 num_addresses;
940 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
941 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
942 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
943 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
948 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
950 /* indirect data for command and response */
951 struct i40e_aqc_add_macvlan_element_data {
955 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
956 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
957 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
958 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
960 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
961 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
962 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
963 /* response section */
965 #define I40E_AQC_MM_PERFECT_MATCH 0x01
966 #define I40E_AQC_MM_HASH_MATCH 0x02
967 #define I40E_AQC_MM_ERR_NO_RES 0xFF
971 struct i40e_aqc_add_remove_macvlan_completion {
972 __le16 perfect_mac_used;
973 __le16 perfect_mac_free;
974 __le16 unicast_hash_free;
975 __le16 multicast_hash_free;
980 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
982 /* Remove MAC-VLAN (indirect 0x0251)
983 * uses i40e_aqc_macvlan for the descriptor
984 * data points to an array of num_addresses of elements
987 struct i40e_aqc_remove_macvlan_element_data {
991 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
992 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
993 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
994 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
998 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
999 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1000 u8 reply_reserved[3];
1003 /* Add VLAN (indirect 0x0252)
1004 * Remove VLAN (indirect 0x0253)
1005 * use the generic i40e_aqc_macvlan for the command
1007 struct i40e_aqc_add_remove_vlan_element_data {
1010 /* flags for add VLAN */
1011 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1012 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1013 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1014 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1015 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1016 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1017 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1018 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1019 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1020 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1021 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1022 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1023 /* flags for remove VLAN */
1024 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1027 /* flags for add VLAN */
1028 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1029 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1030 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1031 /* flags for remove VLAN */
1032 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1033 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1037 struct i40e_aqc_add_remove_vlan_completion {
1045 /* Set VSI Promiscuous Modes (direct 0x0254) */
1046 struct i40e_aqc_set_vsi_promiscuous_modes {
1047 __le16 promiscuous_flags;
1049 /* flags used for both fields above */
1050 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1051 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1052 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1053 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1054 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1056 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1058 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1062 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1064 /* Add S/E-tag command (direct 0x0255)
1065 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1067 struct i40e_aqc_add_tag {
1069 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1071 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1072 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1073 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1075 __le16 queue_number;
1079 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1081 struct i40e_aqc_add_remove_tag_completion {
1087 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1089 /* Remove S/E-tag command (direct 0x0256)
1090 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1092 struct i40e_aqc_remove_tag {
1094 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1095 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1096 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1101 /* Add multicast E-Tag (direct 0x0257)
1102 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1103 * and no external data
1105 struct i40e_aqc_add_remove_mcast_etag {
1108 u8 num_unicast_etags;
1110 __le32 addr_high; /* address of array of 2-byte s-tags */
1114 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1116 struct i40e_aqc_add_remove_mcast_etag_completion {
1118 __le16 mcast_etags_used;
1119 __le16 mcast_etags_free;
1125 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1127 /* Update S/E-Tag (direct 0x0259) */
1128 struct i40e_aqc_update_tag {
1130 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1131 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1132 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1138 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1140 struct i40e_aqc_update_tag_completion {
1146 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1148 /* Add Control Packet filter (direct 0x025A)
1149 * Remove Control Packet filter (direct 0x025B)
1150 * uses the i40e_aqc_add_oveb_cloud,
1151 * and the generic direct completion structure
1153 struct i40e_aqc_add_remove_control_packet_filter {
1157 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1158 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1159 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1160 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1161 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1163 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1164 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1165 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1170 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1172 struct i40e_aqc_add_remove_control_packet_filter_completion {
1173 __le16 mac_etype_used;
1175 __le16 mac_etype_free;
1180 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1182 /* Add Cloud filters (indirect 0x025C)
1183 * Remove Cloud filters (indirect 0x025D)
1184 * uses the i40e_aqc_add_remove_cloud_filters,
1185 * and the generic indirect completion structure
1187 struct i40e_aqc_add_remove_cloud_filters {
1191 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1192 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1193 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1199 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1201 struct i40e_aqc_add_remove_cloud_filters_element_data {
1215 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1216 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1217 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1218 /* 0x0000 reserved */
1219 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1220 /* 0x0002 reserved */
1221 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1222 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1223 /* 0x0005 reserved */
1224 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1225 /* 0x0007 reserved */
1226 /* 0x0008 reserved */
1227 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1228 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1229 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1230 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1232 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1233 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1234 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1235 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1236 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1238 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1239 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1240 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1241 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1242 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1243 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1247 __le16 queue_number;
1248 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1249 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \
1250 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1252 /* response section */
1253 u8 allocation_result;
1254 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1255 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1256 u8 response_reserved[7];
1259 struct i40e_aqc_remove_cloud_filters_completion {
1260 __le16 perfect_ovlan_used;
1261 __le16 perfect_ovlan_free;
1268 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1270 /* Add Mirror Rule (indirect or direct 0x0260)
1271 * Delete Mirror Rule (indirect or direct 0x0261)
1272 * note: some rule types (4,5) do not use an external buffer.
1273 * take care to set the flags correctly.
1275 struct i40e_aqc_add_delete_mirror_rule {
1278 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1279 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1280 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1281 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1282 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1283 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1284 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1285 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1287 __le16 destination; /* VSI for add, rule id for delete */
1288 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1292 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1294 struct i40e_aqc_add_delete_mirror_rule_completion {
1296 __le16 rule_id; /* only used on add */
1297 __le16 mirror_rules_used;
1298 __le16 mirror_rules_free;
1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1307 /* PFC Ignore (direct 0x0301)
1308 * the command and response use the same descriptor structure
1310 struct i40e_aqc_pfc_ignore {
1312 u8 command_flags; /* unused on response */
1313 #define I40E_AQC_PFC_IGNORE_SET 0x80
1314 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1318 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1320 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1321 * with no parameters
1324 /* TX scheduler 0x04xx */
1326 /* Almost all the indirect commands use
1327 * this generic struct to pass the SEID in param0
1329 struct i40e_aqc_tx_sched_ind {
1336 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1338 /* Several commands respond with a set of queue set handles */
1339 struct i40e_aqc_qs_handles_resp {
1340 __le16 qs_handles[8];
1343 /* Configure VSI BW limits (direct 0x0400) */
1344 struct i40e_aqc_configure_vsi_bw_limit {
1349 u8 max_credit; /* 0-3, limit = 2^max */
1353 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1355 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1356 * responds with i40e_aqc_qs_handles_resp
1358 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1361 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1363 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1364 __le16 tc_bw_max[2];
1368 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1369 * responds with i40e_aqc_qs_handles_resp
1371 struct i40e_aqc_configure_vsi_tc_bw_data {
1374 u8 tc_bw_credits[8];
1376 __le16 qs_handles[8];
1379 /* Query vsi bw configuration (indirect 0x0408) */
1380 struct i40e_aqc_query_vsi_bw_config_resp {
1382 u8 tc_suspended_bits;
1384 __le16 qs_handles[8];
1386 __le16 port_bw_limit;
1388 u8 max_bw; /* 0-3, limit = 2^max */
1392 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1393 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1396 u8 share_credits[8];
1399 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1400 __le16 tc_bw_max[2];
1403 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1404 struct i40e_aqc_configure_switching_comp_bw_limit {
1409 u8 max_bw; /* 0-3, limit = 2^max */
1413 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1415 /* Enable Physical Port ETS (indirect 0x0413)
1416 * Modify Physical Port ETS (indirect 0x0414)
1417 * Disable Physical Port ETS (indirect 0x0415)
1419 struct i40e_aqc_configure_switching_comp_ets_data {
1423 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1424 u8 tc_strict_priority_flags;
1426 u8 tc_bw_share_credits[8];
1430 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1431 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1434 __le16 tc_bw_credit[8];
1436 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1437 __le16 tc_bw_max[2];
1441 /* Configure Switching Component Bandwidth Allocation per Tc
1444 struct i40e_aqc_configure_switching_comp_bw_config_data {
1447 u8 absolute_credits; /* bool */
1448 u8 tc_bw_share_credits[8];
1452 /* Query Switching Component Configuration (indirect 0x0418) */
1453 struct i40e_aqc_query_switching_comp_ets_config_resp {
1456 __le16 port_bw_limit;
1458 u8 tc_bw_max; /* 0-3, limit = 2^max */
1462 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1463 struct i40e_aqc_query_port_ets_config_resp {
1467 u8 tc_strict_priority_bits;
1469 u8 tc_bw_share_credits[8];
1470 __le16 tc_bw_limits[8];
1472 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1473 __le16 tc_bw_max[2];
1477 /* Query Switching Component Bandwidth Allocation per Traffic Type
1480 struct i40e_aqc_query_switching_comp_bw_config_resp {
1483 u8 absolute_credits_enable; /* bool */
1484 u8 tc_bw_share_credits[8];
1485 __le16 tc_bw_limits[8];
1487 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1488 __le16 tc_bw_max[2];
1491 /* Suspend/resume port TX traffic
1492 * (direct 0x041B and 0x041C) uses the generic SEID struct
1495 /* Configure partition BW
1498 struct i40e_aqc_configure_partition_bw_data {
1499 __le16 pf_valid_bits;
1500 u8 min_bw[16]; /* guaranteed bandwidth */
1501 u8 max_bw[16]; /* bandwidth limit */
1504 /* Get and set the active HMC resource profile and status.
1505 * (direct 0x0500) and (direct 0x0501)
1507 struct i40e_aq_get_set_hmc_resource_profile {
1513 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1515 enum i40e_aq_hmc_profile {
1516 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1517 I40E_HMC_PROFILE_DEFAULT = 1,
1518 I40E_HMC_PROFILE_FAVOR_VF = 2,
1519 I40E_HMC_PROFILE_EQUAL = 3,
1522 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1523 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1525 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1527 /* set in param0 for get phy abilities to report qualified modules */
1528 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1529 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1531 enum i40e_aq_phy_type {
1532 I40E_PHY_TYPE_SGMII = 0x0,
1533 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1534 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1535 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1536 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1537 I40E_PHY_TYPE_XAUI = 0x5,
1538 I40E_PHY_TYPE_XFI = 0x6,
1539 I40E_PHY_TYPE_SFI = 0x7,
1540 I40E_PHY_TYPE_XLAUI = 0x8,
1541 I40E_PHY_TYPE_XLPPI = 0x9,
1542 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1543 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1544 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1545 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1546 I40E_PHY_TYPE_100BASE_TX = 0x11,
1547 I40E_PHY_TYPE_1000BASE_T = 0x12,
1548 I40E_PHY_TYPE_10GBASE_T = 0x13,
1549 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1550 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1551 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1552 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1553 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1554 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1555 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1556 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1557 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1558 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1559 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1563 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1564 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1565 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1566 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1567 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1569 enum i40e_aq_link_speed {
1570 I40E_LINK_SPEED_UNKNOWN = 0,
1571 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1572 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1573 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1574 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1575 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1578 struct i40e_aqc_module_desc {
1586 struct i40e_aq_get_phy_abilities_resp {
1587 __le32 phy_type; /* bitmap using the above enum for offsets */
1588 u8 link_speed; /* bitmap using the above enum bit patterns */
1590 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1591 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1592 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1593 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1594 #define I40E_AQ_PHY_AN_ENABLED 0x10
1595 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1596 __le16 eee_capability;
1597 #define I40E_AQ_EEE_100BASE_TX 0x0002
1598 #define I40E_AQ_EEE_1000BASE_T 0x0004
1599 #define I40E_AQ_EEE_10GBASE_T 0x0008
1600 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1601 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1602 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1605 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1609 u8 qualified_module_count;
1610 #define I40E_AQ_PHY_MAX_QMS 16
1611 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1614 /* Set PHY Config (direct 0x0601) */
1615 struct i40e_aq_set_phy_config { /* same bits as above in all */
1619 /* bits 0-2 use the values from get_phy_abilities_resp */
1620 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1621 #define I40E_AQ_PHY_ENABLE_AN 0x10
1622 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1623 __le16 eee_capability;
1629 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1631 /* Set MAC Config command data structure (direct 0x0603) */
1632 struct i40e_aq_set_mac_config {
1633 __le16 max_frame_size;
1635 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1636 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1637 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1638 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1639 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1640 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1641 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1642 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1643 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1644 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1645 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1646 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1647 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1648 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1649 u8 tx_timer_priority; /* bitmap */
1650 __le16 tx_timer_value;
1651 __le16 fc_refresh_threshold;
1655 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1657 /* Restart Auto-Negotiation (direct 0x605) */
1658 struct i40e_aqc_set_link_restart_an {
1660 #define I40E_AQ_PHY_RESTART_AN 0x02
1661 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1665 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1667 /* Get Link Status cmd & response data structure (direct 0x0607) */
1668 struct i40e_aqc_get_link_status {
1669 __le16 command_flags; /* only field set on command */
1670 #define I40E_AQ_LSE_MASK 0x3
1671 #define I40E_AQ_LSE_NOP 0x0
1672 #define I40E_AQ_LSE_DISABLE 0x2
1673 #define I40E_AQ_LSE_ENABLE 0x3
1674 /* only response uses this flag */
1675 #define I40E_AQ_LSE_IS_ENABLED 0x1
1676 u8 phy_type; /* i40e_aq_phy_type */
1677 u8 link_speed; /* i40e_aq_link_speed */
1679 #define I40E_AQ_LINK_UP 0x01
1680 #define I40E_AQ_LINK_FAULT 0x02
1681 #define I40E_AQ_LINK_FAULT_TX 0x04
1682 #define I40E_AQ_LINK_FAULT_RX 0x08
1683 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1684 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1685 #define I40E_AQ_SIGNAL_DETECT 0x80
1687 #define I40E_AQ_AN_COMPLETED 0x01
1688 #define I40E_AQ_LP_AN_ABILITY 0x02
1689 #define I40E_AQ_PD_FAULT 0x04
1690 #define I40E_AQ_FEC_EN 0x08
1691 #define I40E_AQ_PHY_LOW_POWER 0x10
1692 #define I40E_AQ_LINK_PAUSE_TX 0x20
1693 #define I40E_AQ_LINK_PAUSE_RX 0x40
1694 #define I40E_AQ_QUALIFIED_MODULE 0x80
1696 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1697 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1698 #define I40E_AQ_LINK_TX_SHIFT 0x02
1699 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1700 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1701 #define I40E_AQ_LINK_TX_DRAINED 0x01
1702 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1703 #define I40E_AQ_LINK_FORCED_40G 0x10
1704 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1705 __le16 max_frame_size;
1707 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1708 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1712 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1714 /* Set event mask command (direct 0x613) */
1715 struct i40e_aqc_set_phy_int_mask {
1718 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1719 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1720 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1721 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1722 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1723 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1724 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1725 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1726 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1730 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1732 /* Get Local AN advt register (direct 0x0614)
1733 * Set Local AN advt register (direct 0x0615)
1734 * Get Link Partner AN advt register (direct 0x0616)
1736 struct i40e_aqc_an_advt_reg {
1737 __le32 local_an_reg0;
1738 __le16 local_an_reg1;
1742 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1744 /* Set Loopback mode (0x0618) */
1745 struct i40e_aqc_set_lb_mode {
1747 #define I40E_AQ_LB_PHY_LOCAL 0x01
1748 #define I40E_AQ_LB_PHY_REMOTE 0x02
1749 #define I40E_AQ_LB_MAC_LOCAL 0x04
1753 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1755 /* Set PHY Debug command (0x0622) */
1756 struct i40e_aqc_set_phy_debug {
1758 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1759 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1760 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1761 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1762 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1763 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1764 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1765 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1769 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1771 enum i40e_aq_phy_reg_type {
1772 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1773 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1774 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1777 /* NVM Read command (indirect 0x0701)
1778 * NVM Erase commands (direct 0x0702)
1779 * NVM Update commands (indirect 0x0703)
1781 struct i40e_aqc_nvm_update {
1783 #define I40E_AQ_NVM_LAST_CMD 0x01
1784 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1792 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1794 /* NVM Config Read (indirect 0x0704) */
1795 struct i40e_aqc_nvm_config_read {
1797 #define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1798 #define ANVM_READ_SINGLE_FEATURE 0
1799 #define ANVM_READ_MULTIPLE_FEATURES 1
1800 __le16 element_count;
1801 __le16 element_id; /* Feature/field ID */
1803 __le32 address_high;
1807 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1809 /* NVM Config Write (indirect 0x0705) */
1810 struct i40e_aqc_nvm_config_write {
1812 __le16 element_count;
1814 __le32 address_high;
1818 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1820 struct i40e_aqc_nvm_config_data_feature {
1823 __le16 feature_options;
1824 __le16 feature_selection;
1827 struct i40e_aqc_nvm_config_data_immediate_field {
1828 #define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
1831 __le16 field_options;
1835 /* Send to PF command (indirect 0x0801) id is only used by PF
1836 * Send to VF command (indirect 0x0802) id is only used by PF
1837 * Send to Peer PF command (indirect 0x0803)
1839 struct i40e_aqc_pf_vf_message {
1846 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1848 /* Alternate structure */
1850 /* Direct write (direct 0x0900)
1851 * Direct read (direct 0x0902)
1853 struct i40e_aqc_alternate_write {
1860 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1862 /* Indirect write (indirect 0x0901)
1863 * Indirect read (indirect 0x0903)
1866 struct i40e_aqc_alternate_ind_write {
1873 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1875 /* Done alternate write (direct 0x0904)
1878 struct i40e_aqc_alternate_write_done {
1880 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1881 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1882 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1883 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1887 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1889 /* Set OEM mode (direct 0x0905) */
1890 struct i40e_aqc_alternate_set_mode {
1892 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1893 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1897 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1899 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1901 /* async events 0x10xx */
1903 /* Lan Queue Overflow Event (direct, 0x1001) */
1904 struct i40e_aqc_lan_overflow {
1905 __le32 prtdcb_rupto;
1910 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1912 /* Get LLDP MIB (indirect 0x0A00) */
1913 struct i40e_aqc_lldp_get_mib {
1916 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1917 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1918 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1919 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1920 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1921 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1922 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1923 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1924 #define I40E_AQ_LLDP_TX_SHIFT 0x4
1925 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1926 /* TX pause flags use I40E_AQ_LINK_TX_* above */
1934 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1936 /* Configure LLDP MIB Change Event (direct 0x0A01)
1937 * also used for the event (with type in the command field)
1939 struct i40e_aqc_lldp_update_mib {
1941 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1942 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1948 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1950 /* Add LLDP TLV (indirect 0x0A02)
1951 * Delete LLDP TLV (indirect 0x0A04)
1953 struct i40e_aqc_lldp_add_tlv {
1954 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1962 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1964 /* Update LLDP TLV (indirect 0x0A03) */
1965 struct i40e_aqc_lldp_update_tlv {
1966 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1975 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1977 /* Stop LLDP (direct 0x0A05) */
1978 struct i40e_aqc_lldp_stop {
1980 #define I40E_AQ_LLDP_AGENT_STOP 0x0
1981 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1985 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1987 /* Start LLDP (direct 0x0A06) */
1989 struct i40e_aqc_lldp_start {
1991 #define I40E_AQ_LLDP_AGENT_START 0x1
1995 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1997 /* Apply MIB changes (0x0A07)
1998 * uses the generic struc as it contains no data
2001 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2002 struct i40e_aqc_add_udp_tunnel {
2006 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2007 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2008 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2012 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2014 struct i40e_aqc_add_udp_tunnel_completion {
2016 u8 filter_entry_index;
2018 #define I40E_AQC_SINGLE_PF 0x0
2019 #define I40E_AQC_MULTIPLE_PFS 0x1
2024 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2026 /* remove UDP Tunnel command (0x0B01) */
2027 struct i40e_aqc_remove_udp_tunnel {
2029 u8 index; /* 0 to 15 */
2033 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2035 struct i40e_aqc_del_udp_tunnel_completion {
2037 u8 index; /* 0 to 15 */
2039 u8 total_filters_used;
2043 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2045 /* tunnel key structure 0x0B10 */
2047 struct i40e_aqc_tunnel_key_structure {
2050 u8 key1_len; /* 0 to 15 */
2051 u8 key2_len; /* 0 to 15 */
2053 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2054 /* response flags */
2055 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2056 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2057 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2058 u8 network_key_index;
2059 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2060 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2061 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2062 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2066 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2068 /* OEM mode commands (direct 0xFE0x) */
2069 struct i40e_aqc_oem_param_change {
2071 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2072 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2073 #define I40E_AQ_OEM_PARAM_MAC 2
2074 __le32 param_value1;
2078 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2080 struct i40e_aqc_oem_state_change {
2082 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2083 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2087 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2089 /* debug commands */
2091 /* get device id (0xFF00) uses the generic structure */
2093 /* set test more (0xFF01, internal) */
2095 struct i40e_acq_set_test_mode {
2097 #define I40E_AQ_TEST_PARTIAL 0
2098 #define I40E_AQ_TEST_FULL 1
2099 #define I40E_AQ_TEST_NVM 2
2102 #define I40E_AQ_TEST_OPEN 0
2103 #define I40E_AQ_TEST_CLOSE 1
2104 #define I40E_AQ_TEST_INC 2
2106 __le32 address_high;
2110 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2112 /* Debug Read Register command (0xFF03)
2113 * Debug Write Register command (0xFF04)
2115 struct i40e_aqc_debug_reg_read_write {
2122 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2124 /* Scatter/gather Reg Read (indirect 0xFF05)
2125 * Scatter/gather Reg Write (indirect 0xFF06)
2128 /* i40e_aq_desc is used for the command */
2129 struct i40e_aqc_debug_reg_sg_element_data {
2134 /* Debug Modify register (direct 0xFF07) */
2135 struct i40e_aqc_debug_modify_reg {
2142 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2144 /* dump internal data (0xFF08, indirect) */
2146 #define I40E_AQ_CLUSTER_ID_AUX 0
2147 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2148 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2149 #define I40E_AQ_CLUSTER_ID_HMC 3
2150 #define I40E_AQ_CLUSTER_ID_MAC0 4
2151 #define I40E_AQ_CLUSTER_ID_MAC1 5
2152 #define I40E_AQ_CLUSTER_ID_MAC2 6
2153 #define I40E_AQ_CLUSTER_ID_MAC3 7
2154 #define I40E_AQ_CLUSTER_ID_DCB 8
2155 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2156 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2157 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2159 struct i40e_aqc_debug_dump_internals {
2164 __le32 address_high;
2168 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2170 struct i40e_aqc_debug_modify_internals {
2172 u8 cluster_specific_params[7];
2173 __le32 address_high;
2177 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);