1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
44 #define UNREFERENCED_XPARAMETER
45 #define UNREFERENCED_1PARAMETER(_p) (_p);
46 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
47 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
48 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
49 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
52 #define I40E_INTEL_VENDOR_ID 0x8086
55 #define I40E_DEV_ID_SFP_XL710 0x1572
56 #define I40E_DEV_ID_QEMU 0x1574
57 #define I40E_DEV_ID_KX_A 0x157F
58 #define I40E_DEV_ID_KX_B 0x1580
59 #define I40E_DEV_ID_KX_C 0x1581
60 #define I40E_DEV_ID_QSFP_A 0x1583
61 #define I40E_DEV_ID_QSFP_B 0x1584
62 #define I40E_DEV_ID_QSFP_C 0x1585
63 #define I40E_DEV_ID_10G_BASE_T 0x1586
64 #define I40E_DEV_ID_VF 0x154C
65 #define I40E_DEV_ID_VF_HV 0x1571
67 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
68 (d) == I40E_DEV_ID_QSFP_B || \
69 (d) == I40E_DEV_ID_QSFP_C)
72 /* I40E_MASK is a macro used on 32 bit registers */
73 #define I40E_MASK(mask, shift) (mask << shift)
76 #define I40E_MAX_PF 16
77 #define I40E_MAX_PF_VSI 64
78 #define I40E_MAX_PF_QP 128
79 #define I40E_MAX_VSI_QP 16
80 #define I40E_MAX_VF_VSI 3
81 #define I40E_MAX_CHAINED_RX_BUFFERS 5
82 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
84 /* something less than 1 minute */
85 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
87 /* Max default timeout in ms, */
88 #define I40E_MAX_NVM_TIMEOUT 18000
90 /* Check whether address is multicast. */
91 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
93 /* Check whether an address is broadcast. */
94 #define I40E_IS_BROADCAST(address) \
95 ((((u8 *)(address))[0] == ((u8)0xff)) && \
96 (((u8 *)(address))[1] == ((u8)0xff)))
98 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
99 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
101 /* forward declaration */
103 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
105 #define I40E_ETH_LENGTH_OF_ADDRESS 6
106 /* Data type manipulation macros. */
107 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
108 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
110 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
111 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
113 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
114 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
116 /* Number of Transmit Descriptors must be a multiple of 8. */
117 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
118 /* Number of Receive Descriptors must be a multiple of 32 if
119 * the number of descriptors is greater than 32.
121 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
123 #define I40E_DESC_UNUSED(R) \
124 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
125 (R)->next_to_clean - (R)->next_to_use - 1)
127 /* bitfields for Tx queue mapping in QTX_CTL */
128 #define I40E_QTX_CTL_VF_QUEUE 0x0
129 #define I40E_QTX_CTL_VM_QUEUE 0x1
130 #define I40E_QTX_CTL_PF_QUEUE 0x2
132 /* debug masks - set these bits in hw->debug_mask to control output */
133 enum i40e_debug_mask {
134 I40E_DEBUG_INIT = 0x00000001,
135 I40E_DEBUG_RELEASE = 0x00000002,
137 I40E_DEBUG_LINK = 0x00000010,
138 I40E_DEBUG_PHY = 0x00000020,
139 I40E_DEBUG_HMC = 0x00000040,
140 I40E_DEBUG_NVM = 0x00000080,
141 I40E_DEBUG_LAN = 0x00000100,
142 I40E_DEBUG_FLOW = 0x00000200,
143 I40E_DEBUG_DCB = 0x00000400,
144 I40E_DEBUG_DIAG = 0x00000800,
145 I40E_DEBUG_FD = 0x00001000,
147 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
148 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
149 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
150 I40E_DEBUG_AQ_COMMAND = 0x06000000,
151 I40E_DEBUG_AQ = 0x0F000000,
153 I40E_DEBUG_USER = 0xF0000000,
155 I40E_DEBUG_ALL = 0xFFFFFFFF
159 #define I40E_PCI_LINK_STATUS 0xB2
160 #define I40E_PCI_LINK_WIDTH 0x3F0
161 #define I40E_PCI_LINK_WIDTH_1 0x10
162 #define I40E_PCI_LINK_WIDTH_2 0x20
163 #define I40E_PCI_LINK_WIDTH_4 0x40
164 #define I40E_PCI_LINK_WIDTH_8 0x80
165 #define I40E_PCI_LINK_SPEED 0xF
166 #define I40E_PCI_LINK_SPEED_2500 0x1
167 #define I40E_PCI_LINK_SPEED_5000 0x2
168 #define I40E_PCI_LINK_SPEED_8000 0x3
171 enum i40e_memset_type {
177 enum i40e_memcpy_type {
178 I40E_NONDMA_TO_NONDMA = 0,
184 /* These are structs for managing the hardware information and the operations.
185 * The structures of function pointers are filled out at init time when we
186 * know for sure exactly which hardware we're working with. This gives us the
187 * flexibility of using the same main driver code but adapting to slightly
188 * different hardware needs as new parts are developed. For this architecture,
189 * the Firmware and AdminQ are intended to insulate the driver from most of the
190 * future changes, but these structures will also do part of the job.
193 I40E_MAC_UNKNOWN = 0,
200 enum i40e_media_type {
201 I40E_MEDIA_TYPE_UNKNOWN = 0,
202 I40E_MEDIA_TYPE_FIBER,
203 I40E_MEDIA_TYPE_BASET,
204 I40E_MEDIA_TYPE_BACKPLANE,
207 I40E_MEDIA_TYPE_VIRTUAL
219 enum i40e_set_fc_aq_failures {
220 I40E_SET_FC_AQ_FAIL_NONE = 0,
221 I40E_SET_FC_AQ_FAIL_GET = 1,
222 I40E_SET_FC_AQ_FAIL_SET = 2,
223 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
224 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
236 I40E_VSI_TYPE_UNKNOWN
239 enum i40e_queue_type {
240 I40E_QUEUE_TYPE_RX = 0,
242 I40E_QUEUE_TYPE_PE_CEQ,
243 I40E_QUEUE_TYPE_UNKNOWN
246 struct i40e_link_status {
247 enum i40e_aq_phy_type phy_type;
248 enum i40e_aq_link_speed link_speed;
254 /* is Link Status Event notification to SW enabled */
261 struct i40e_phy_info {
262 struct i40e_link_status link_info;
263 struct i40e_link_status link_info_old;
264 u32 autoneg_advertised;
268 enum i40e_media_type media_type;
271 #define I40E_HW_CAP_MAX_GPIO 30
272 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
273 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
275 /* Capabilities of a PF or a VF or the whole device */
276 struct i40e_hw_capabilities {
278 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
279 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
280 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
288 bool evb_802_1_qbg; /* Edge Virtual Bridging */
289 bool evb_802_1_qbh; /* Bridge Port Extension */
292 bool iscsi; /* Indicates iSCSI enabled */
298 u32 fd_filters_guaranteed;
299 u32 fd_filters_best_effort;
302 u32 rss_table_entry_width;
303 bool led[I40E_HW_CAP_MAX_GPIO];
304 bool sdp[I40E_HW_CAP_MAX_GPIO];
306 u32 num_flow_director_filters;
313 u32 num_msix_vectors;
314 u32 num_msix_vectors_vf;
324 struct i40e_mac_info {
325 enum i40e_mac_type type;
326 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
327 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
328 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
329 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
333 enum i40e_aq_resources_ids {
334 I40E_NVM_RESOURCE_ID = 1
337 enum i40e_aq_resource_access_type {
338 I40E_RESOURCE_READ = 1,
342 struct i40e_nvm_info {
343 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
344 u64 hw_semaphore_wait; /* - || - */
345 u32 timeout; /* [ms] */
346 u16 sr_size; /* Shadow RAM size in words */
347 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
348 u16 version; /* NVM package version */
349 u32 eetrack; /* NVM data version */
352 /* definitions used in NVM update support */
354 enum i40e_nvmupd_cmd {
356 I40E_NVMUPD_READ_CON,
357 I40E_NVMUPD_READ_SNT,
358 I40E_NVMUPD_READ_LCB,
360 I40E_NVMUPD_WRITE_ERA,
361 I40E_NVMUPD_WRITE_CON,
362 I40E_NVMUPD_WRITE_SNT,
363 I40E_NVMUPD_WRITE_LCB,
364 I40E_NVMUPD_WRITE_SA,
365 I40E_NVMUPD_CSUM_CON,
367 I40E_NVMUPD_CSUM_LCB,
370 enum i40e_nvmupd_state {
371 I40E_NVMUPD_STATE_INIT,
372 I40E_NVMUPD_STATE_READING,
373 I40E_NVMUPD_STATE_WRITING
376 /* nvm_access definition and its masks/shifts need to be accessible to
377 * application, core driver, and shared code. Where is the right file?
379 #define I40E_NVM_READ 0xB
380 #define I40E_NVM_WRITE 0xC
382 #define I40E_NVM_MOD_PNT_MASK 0xFF
384 #define I40E_NVM_TRANS_SHIFT 8
385 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
386 #define I40E_NVM_CON 0x0
387 #define I40E_NVM_SNT 0x1
388 #define I40E_NVM_LCB 0x2
389 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
390 #define I40E_NVM_ERA 0x4
391 #define I40E_NVM_CSUM 0x8
393 #define I40E_NVM_ADAPT_SHIFT 16
394 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
396 #define I40E_NVMUPD_MAX_DATA 4096
397 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
399 struct i40e_nvm_access {
402 u32 offset; /* in bytes */
403 u32 data_size; /* in bytes */
409 i40e_bus_type_unknown = 0,
412 i40e_bus_type_pci_express,
413 i40e_bus_type_reserved
417 enum i40e_bus_speed {
418 i40e_bus_speed_unknown = 0,
419 i40e_bus_speed_33 = 33,
420 i40e_bus_speed_66 = 66,
421 i40e_bus_speed_100 = 100,
422 i40e_bus_speed_120 = 120,
423 i40e_bus_speed_133 = 133,
424 i40e_bus_speed_2500 = 2500,
425 i40e_bus_speed_5000 = 5000,
426 i40e_bus_speed_8000 = 8000,
427 i40e_bus_speed_reserved
431 enum i40e_bus_width {
432 i40e_bus_width_unknown = 0,
433 i40e_bus_width_pcie_x1 = 1,
434 i40e_bus_width_pcie_x2 = 2,
435 i40e_bus_width_pcie_x4 = 4,
436 i40e_bus_width_pcie_x8 = 8,
437 i40e_bus_width_32 = 32,
438 i40e_bus_width_64 = 64,
439 i40e_bus_width_reserved
443 struct i40e_bus_info {
444 enum i40e_bus_speed speed;
445 enum i40e_bus_width width;
446 enum i40e_bus_type type;
453 /* Flow control (FC) parameters */
454 struct i40e_fc_info {
455 enum i40e_fc_mode current_mode; /* FC mode in effect */
456 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
459 #define I40E_MAX_TRAFFIC_CLASS 8
460 #define I40E_MAX_USER_PRIORITY 8
461 #define I40E_DCBX_MAX_APPS 32
462 #define I40E_LLDPDU_SIZE 1500
463 #define I40E_TLV_STATUS_OPER 0x1
464 #define I40E_TLV_STATUS_SYNC 0x2
465 #define I40E_TLV_STATUS_ERR 0x4
466 #define I40E_CEE_OPER_MAX_APPS 3
467 #define I40E_APP_PROTOID_FCOE 0x8906
468 #define I40E_APP_PROTOID_ISCSI 0x0cbc
469 #define I40E_APP_PROTOID_FIP 0x8914
470 #define I40E_APP_SEL_ETHTYPE 0x1
471 #define I40E_APP_SEL_TCPIP 0x2
473 /* CEE or IEEE 802.1Qaz ETS Configuration data */
474 struct i40e_dcb_ets_config {
478 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
479 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
480 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
483 /* CEE or IEEE 802.1Qaz PFC Configuration data */
484 struct i40e_dcb_pfc_config {
491 /* CEE or IEEE 802.1Qaz Application Priority data */
492 struct i40e_dcb_app_priority_table {
498 struct i40e_dcbx_config {
500 #define I40E_DCBX_MODE_CEE 0x1
501 #define I40E_DCBX_MODE_IEEE 0x2
503 struct i40e_dcb_ets_config etscfg;
504 struct i40e_dcb_ets_config etsrec;
505 struct i40e_dcb_pfc_config pfc;
506 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
509 /* Port hardware description */
514 /* function pointer structs */
515 struct i40e_phy_info phy;
516 struct i40e_mac_info mac;
517 struct i40e_bus_info bus;
518 struct i40e_nvm_info nvm;
519 struct i40e_fc_info fc;
524 u16 subsystem_device_id;
525 u16 subsystem_vendor_id;
528 bool adapter_stopped;
530 /* capabilities for entire device and PCI func */
531 struct i40e_hw_capabilities dev_caps;
532 struct i40e_hw_capabilities func_caps;
534 /* Flow Director shared filter space */
535 u16 fdir_shared_filter_count;
537 /* device profile info */
541 /* for multi-function MACs */
546 /* Closest numa node to the device */
549 /* Admin Queue info */
550 struct i40e_adminq_info aq;
552 /* state of nvm update process */
553 enum i40e_nvmupd_state nvmupd_state;
556 struct i40e_hmc_info hmc; /* HMC info struct */
558 /* LLDP/DCBX Status */
562 struct i40e_dcbx_config local_dcbx_config;
563 struct i40e_dcbx_config remote_dcbx_config;
569 static inline bool i40e_is_vf(struct i40e_hw *hw)
571 return hw->mac.type == I40E_MAC_VF;
574 struct i40e_driver_version {
579 u8 driver_string[32];
583 union i40e_16byte_rx_desc {
585 __le64 pkt_addr; /* Packet buffer address */
586 __le64 hdr_addr; /* Header buffer address */
592 __le16 mirroring_status;
598 __le32 rss; /* RSS Hash */
599 __le32 fd_id; /* Flow director filter id */
600 __le32 fcoe_param; /* FCoE DDP Context id */
604 /* ext status/error/pktype/length */
605 __le64 status_error_len;
607 } wb; /* writeback */
610 union i40e_32byte_rx_desc {
612 __le64 pkt_addr; /* Packet buffer address */
613 __le64 hdr_addr; /* Header buffer address */
614 /* bit 0 of hdr_buffer_addr is DD bit */
622 __le16 mirroring_status;
628 __le32 rss; /* RSS Hash */
629 __le32 fcoe_param; /* FCoE DDP Context id */
630 /* Flow director filter id in case of
631 * Programming status desc WB
637 /* status/error/pktype/length */
638 __le64 status_error_len;
641 __le16 ext_status; /* extended status */
648 __le32 flex_bytes_lo;
652 __le32 flex_bytes_hi;
656 } wb; /* writeback */
659 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
660 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
661 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
662 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
663 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
664 I40E_RXD_QW0_FCOEINDX_SHIFT)
666 enum i40e_rx_desc_status_bits {
667 /* Note: These are predefined bit offsets */
668 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
669 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
670 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
671 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
672 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
673 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
674 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
675 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
676 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
677 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
678 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
679 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
680 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
681 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
682 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
683 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
686 #define I40E_RXD_QW1_STATUS_SHIFT 0
687 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \
688 I40E_RXD_QW1_STATUS_SHIFT)
690 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
691 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
692 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
694 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
695 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
696 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
698 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
699 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
700 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
702 enum i40e_rx_desc_fltstat_values {
703 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
704 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
705 I40E_RX_DESC_FLTSTAT_RSV = 2,
706 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
709 #define I40E_RXD_PACKET_TYPE_UNICAST 0
710 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
711 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
712 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
714 #define I40E_RXD_QW1_ERROR_SHIFT 19
715 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
717 enum i40e_rx_desc_error_bits {
718 /* Note: These are predefined bit offsets */
719 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
720 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
721 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
722 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
723 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
724 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
725 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
726 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
727 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
730 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
731 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
732 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
733 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
734 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
735 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
738 #define I40E_RXD_QW1_PTYPE_SHIFT 30
739 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
741 /* Packet type non-ip values */
742 enum i40e_rx_l2_ptype {
743 I40E_RX_PTYPE_L2_RESERVED = 0,
744 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
745 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
746 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
747 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
748 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
749 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
750 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
751 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
752 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
753 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
754 I40E_RX_PTYPE_L2_ARP = 11,
755 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
756 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
757 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
758 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
759 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
760 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
761 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
762 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
763 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
764 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
765 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
766 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
767 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
768 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
771 struct i40e_rx_ptype_decoded {
778 u32 tunnel_end_prot:2;
779 u32 tunnel_end_frag:1;
784 enum i40e_rx_ptype_outer_ip {
785 I40E_RX_PTYPE_OUTER_L2 = 0,
786 I40E_RX_PTYPE_OUTER_IP = 1
789 enum i40e_rx_ptype_outer_ip_ver {
790 I40E_RX_PTYPE_OUTER_NONE = 0,
791 I40E_RX_PTYPE_OUTER_IPV4 = 0,
792 I40E_RX_PTYPE_OUTER_IPV6 = 1
795 enum i40e_rx_ptype_outer_fragmented {
796 I40E_RX_PTYPE_NOT_FRAG = 0,
797 I40E_RX_PTYPE_FRAG = 1
800 enum i40e_rx_ptype_tunnel_type {
801 I40E_RX_PTYPE_TUNNEL_NONE = 0,
802 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
803 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
804 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
805 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
808 enum i40e_rx_ptype_tunnel_end_prot {
809 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
810 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
811 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
814 enum i40e_rx_ptype_inner_prot {
815 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
816 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
817 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
818 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
819 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
820 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
823 enum i40e_rx_ptype_payload_layer {
824 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
825 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
826 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
827 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
830 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
831 #define I40E_RX_PTYPE_SHIFT 56
833 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
834 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
835 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
837 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
838 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
839 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
841 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
842 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
843 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
845 #define I40E_RXD_QW1_NEXTP_SHIFT 38
846 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
848 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
849 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
850 I40E_RXD_QW2_EXT_STATUS_SHIFT)
852 enum i40e_rx_desc_ext_status_bits {
853 /* Note: These are predefined bit offsets */
854 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
855 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
856 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
857 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
858 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
859 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
860 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
863 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
864 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
866 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
867 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
869 enum i40e_rx_desc_pe_status_bits {
870 /* Note: These are predefined bit offsets */
871 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
872 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
873 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
874 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
875 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
876 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
877 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
878 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
879 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
882 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
883 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
885 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
886 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
887 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
889 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
890 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
891 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
893 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
894 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
895 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
897 enum i40e_rx_prog_status_desc_status_bits {
898 /* Note: These are predefined bit offsets */
899 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
900 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
903 enum i40e_rx_prog_status_desc_prog_id_masks {
904 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
905 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
906 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
909 enum i40e_rx_prog_status_desc_error_bits {
910 /* Note: These are predefined bit offsets */
911 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
912 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
913 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
914 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
917 #define I40E_TWO_BIT_MASK 0x3
918 #define I40E_THREE_BIT_MASK 0x7
919 #define I40E_FOUR_BIT_MASK 0xF
920 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
923 struct i40e_tx_desc {
924 __le64 buffer_addr; /* Address of descriptor's data buf */
925 __le64 cmd_type_offset_bsz;
928 #define I40E_TXD_QW1_DTYPE_SHIFT 0
929 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
931 enum i40e_tx_desc_dtype_value {
932 I40E_TX_DESC_DTYPE_DATA = 0x0,
933 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
934 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
935 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
936 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
937 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
938 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
939 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
940 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
941 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
944 #define I40E_TXD_QW1_CMD_SHIFT 4
945 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
947 enum i40e_tx_desc_cmd_bits {
948 I40E_TX_DESC_CMD_EOP = 0x0001,
949 I40E_TX_DESC_CMD_RS = 0x0002,
950 I40E_TX_DESC_CMD_ICRC = 0x0004,
951 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
952 I40E_TX_DESC_CMD_DUMMY = 0x0010,
953 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
954 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
955 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
956 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
957 I40E_TX_DESC_CMD_FCOET = 0x0080,
958 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
959 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
960 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
961 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
962 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
963 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
964 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
965 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
968 #define I40E_TXD_QW1_OFFSET_SHIFT 16
969 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
970 I40E_TXD_QW1_OFFSET_SHIFT)
972 enum i40e_tx_desc_length_fields {
973 /* Note: These are predefined bit offsets */
974 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
975 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
976 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
979 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
980 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
981 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
982 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
984 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
985 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
986 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
988 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
989 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
991 /* Context descriptors */
992 struct i40e_tx_context_desc {
993 __le32 tunneling_params;
996 __le64 type_cmd_tso_mss;
999 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1000 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1002 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1003 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1005 enum i40e_tx_ctx_desc_cmd_bits {
1006 I40E_TX_CTX_DESC_TSO = 0x01,
1007 I40E_TX_CTX_DESC_TSYN = 0x02,
1008 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1009 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1010 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1011 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1012 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1013 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1014 I40E_TX_CTX_DESC_SWPE = 0x40
1017 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1018 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1019 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1021 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1022 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1023 I40E_TXD_CTX_QW1_MSS_SHIFT)
1025 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1026 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1028 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1029 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1030 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1032 enum i40e_tx_ctx_desc_eipt_offload {
1033 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1034 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1035 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1036 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1039 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1040 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1041 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1043 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1044 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1046 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1047 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1049 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1050 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
1051 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1053 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1055 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1056 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1057 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1059 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1060 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1061 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1063 struct i40e_nop_desc {
1068 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1069 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1071 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1072 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1074 enum i40e_tx_nop_desc_cmd_bits {
1075 /* Note: These are predefined bit offsets */
1076 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1077 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1078 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1081 struct i40e_filter_program_desc {
1082 __le32 qindex_flex_ptype_vsi;
1084 __le32 dtype_cmd_cntindex;
1087 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1088 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1089 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1090 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1091 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1092 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1093 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1094 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1095 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1097 /* Packet Classifier Types for filters */
1098 enum i40e_filter_pctype {
1099 /* Note: Values 0-30 are reserved for future use */
1100 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1101 /* Note: Value 32 is reserved for future use */
1102 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1103 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1104 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1105 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1106 /* Note: Values 37-40 are reserved for future use */
1107 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1108 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1109 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1110 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1111 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1112 /* Note: Value 47 is reserved for future use */
1113 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1114 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1115 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1116 /* Note: Values 51-62 are reserved for future use */
1117 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1120 enum i40e_filter_program_desc_dest {
1121 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1122 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1123 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1126 enum i40e_filter_program_desc_fd_status {
1127 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1128 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1129 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1130 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1133 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1134 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1135 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1137 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1138 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1140 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1141 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1142 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1144 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1145 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1147 enum i40e_filter_program_desc_pcmd {
1148 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1149 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1152 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1153 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1155 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1156 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
1157 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1159 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1160 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1161 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1162 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1164 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1165 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1166 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1168 enum i40e_filter_type {
1169 I40E_FLOW_DIRECTOR_FLTR = 0,
1170 I40E_PE_QUAD_HASH_FLTR = 1,
1171 I40E_ETHERTYPE_FLTR,
1177 struct i40e_vsi_context {
1182 u16 vsis_unallocated;
1187 struct i40e_aqc_vsi_properties_data info;
1190 struct i40e_veb_context {
1195 u16 vebs_unallocated;
1197 struct i40e_aqc_get_veb_parameters_completion info;
1200 /* Statistics collected by each port, VSI, VEB, and S-channel */
1201 struct i40e_eth_stats {
1202 u64 rx_bytes; /* gorc */
1203 u64 rx_unicast; /* uprc */
1204 u64 rx_multicast; /* mprc */
1205 u64 rx_broadcast; /* bprc */
1206 u64 rx_discards; /* rdpc */
1207 u64 rx_unknown_protocol; /* rupp */
1208 u64 tx_bytes; /* gotc */
1209 u64 tx_unicast; /* uptc */
1210 u64 tx_multicast; /* mptc */
1211 u64 tx_broadcast; /* bptc */
1212 u64 tx_discards; /* tdpc */
1213 u64 tx_errors; /* tepc */
1216 /* Statistics collected by the MAC */
1217 struct i40e_hw_port_stats {
1218 /* eth stats collected by the port */
1219 struct i40e_eth_stats eth;
1221 /* additional port specific stats */
1222 u64 tx_dropped_link_down; /* tdold */
1223 u64 crc_errors; /* crcerrs */
1224 u64 illegal_bytes; /* illerrc */
1225 u64 error_bytes; /* errbc */
1226 u64 mac_local_faults; /* mlfc */
1227 u64 mac_remote_faults; /* mrfc */
1228 u64 rx_length_errors; /* rlec */
1229 u64 link_xon_rx; /* lxonrxc */
1230 u64 link_xoff_rx; /* lxoffrxc */
1231 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1232 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1233 u64 link_xon_tx; /* lxontxc */
1234 u64 link_xoff_tx; /* lxofftxc */
1235 u64 priority_xon_tx[8]; /* pxontxc[8] */
1236 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1237 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1238 u64 rx_size_64; /* prc64 */
1239 u64 rx_size_127; /* prc127 */
1240 u64 rx_size_255; /* prc255 */
1241 u64 rx_size_511; /* prc511 */
1242 u64 rx_size_1023; /* prc1023 */
1243 u64 rx_size_1522; /* prc1522 */
1244 u64 rx_size_big; /* prc9522 */
1245 u64 rx_undersize; /* ruc */
1246 u64 rx_fragments; /* rfc */
1247 u64 rx_oversize; /* roc */
1248 u64 rx_jabber; /* rjc */
1249 u64 tx_size_64; /* ptc64 */
1250 u64 tx_size_127; /* ptc127 */
1251 u64 tx_size_255; /* ptc255 */
1252 u64 tx_size_511; /* ptc511 */
1253 u64 tx_size_1023; /* ptc1023 */
1254 u64 tx_size_1522; /* ptc1522 */
1255 u64 tx_size_big; /* ptc9522 */
1256 u64 mac_short_packet_dropped; /* mspdc */
1257 u64 checksum_error; /* xec */
1258 /* flow director stats */
1264 u64 tx_lpi_count; /* etlpic */
1265 u64 rx_lpi_count; /* erlpic */
1268 /* Checksum and Shadow RAM pointers */
1269 #define I40E_SR_NVM_CONTROL_WORD 0x00
1270 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1271 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1272 #define I40E_SR_OPTION_ROM_PTR 0x05
1273 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1274 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1275 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1276 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1277 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1278 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1279 #define I40E_SR_PE_IMAGE_PTR 0x0C
1280 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1281 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1282 #define I40E_SR_EMP_MODULE_PTR 0x0F
1283 #define I40E_SR_PBA_FLAGS 0x15
1284 #define I40E_SR_PBA_BLOCK_PTR 0x16
1285 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1286 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1287 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1288 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1289 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1290 #define I40E_SR_NVM_MAP_VERSION 0x29
1291 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1292 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1293 #define I40E_SR_NVM_EETRACK_LO 0x2D
1294 #define I40E_SR_NVM_EETRACK_HI 0x2E
1295 #define I40E_SR_VPD_PTR 0x2F
1296 #define I40E_SR_PXE_SETUP_PTR 0x30
1297 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1298 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1299 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1300 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1301 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1302 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1303 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1304 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1305 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1306 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1307 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1308 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1309 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1311 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1312 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1313 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1314 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1315 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1317 /* Shadow RAM related */
1318 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1319 #define I40E_SR_BUF_ALIGNMENT 4096
1320 #define I40E_SR_WORDS_IN_1KB 512
1321 /* Checksum should be calculated such that after adding all the words,
1322 * including the checksum word itself, the sum should be 0xBABA.
1324 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1326 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1328 enum i40e_switch_element_types {
1329 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1330 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1331 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1332 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1333 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1334 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1335 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1336 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1337 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1340 /* Supported EtherType filters */
1341 enum i40e_ether_type_index {
1342 I40E_ETHER_TYPE_1588 = 0,
1343 I40E_ETHER_TYPE_FIP = 1,
1344 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1345 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1346 I40E_ETHER_TYPE_LLDP = 4,
1347 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1348 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1349 I40E_ETHER_TYPE_QCN_CNM = 7,
1350 I40E_ETHER_TYPE_8021X = 8,
1351 I40E_ETHER_TYPE_ARP = 9,
1352 I40E_ETHER_TYPE_RSV1 = 10,
1353 I40E_ETHER_TYPE_RSV2 = 11,
1356 /* Filter context base size is 1K */
1357 #define I40E_HASH_FILTER_BASE_SIZE 1024
1358 /* Supported Hash filter values */
1359 enum i40e_hash_filter_size {
1360 I40E_HASH_FILTER_SIZE_1K = 0,
1361 I40E_HASH_FILTER_SIZE_2K = 1,
1362 I40E_HASH_FILTER_SIZE_4K = 2,
1363 I40E_HASH_FILTER_SIZE_8K = 3,
1364 I40E_HASH_FILTER_SIZE_16K = 4,
1365 I40E_HASH_FILTER_SIZE_32K = 5,
1366 I40E_HASH_FILTER_SIZE_64K = 6,
1367 I40E_HASH_FILTER_SIZE_128K = 7,
1368 I40E_HASH_FILTER_SIZE_256K = 8,
1369 I40E_HASH_FILTER_SIZE_512K = 9,
1370 I40E_HASH_FILTER_SIZE_1M = 10,
1373 /* DMA context base size is 0.5K */
1374 #define I40E_DMA_CNTX_BASE_SIZE 512
1375 /* Supported DMA context values */
1376 enum i40e_dma_cntx_size {
1377 I40E_DMA_CNTX_SIZE_512 = 0,
1378 I40E_DMA_CNTX_SIZE_1K = 1,
1379 I40E_DMA_CNTX_SIZE_2K = 2,
1380 I40E_DMA_CNTX_SIZE_4K = 3,
1381 I40E_DMA_CNTX_SIZE_8K = 4,
1382 I40E_DMA_CNTX_SIZE_16K = 5,
1383 I40E_DMA_CNTX_SIZE_32K = 6,
1384 I40E_DMA_CNTX_SIZE_64K = 7,
1385 I40E_DMA_CNTX_SIZE_128K = 8,
1386 I40E_DMA_CNTX_SIZE_256K = 9,
1389 /* Supported Hash look up table (LUT) sizes */
1390 enum i40e_hash_lut_size {
1391 I40E_HASH_LUT_SIZE_128 = 0,
1392 I40E_HASH_LUT_SIZE_512 = 1,
1395 /* Structure to hold a per PF filter control settings */
1396 struct i40e_filter_control_settings {
1397 /* number of PE Quad Hash filter buckets */
1398 enum i40e_hash_filter_size pe_filt_num;
1399 /* number of PE Quad Hash contexts */
1400 enum i40e_dma_cntx_size pe_cntx_num;
1401 /* number of FCoE filter buckets */
1402 enum i40e_hash_filter_size fcoe_filt_num;
1403 /* number of FCoE DDP contexts */
1404 enum i40e_dma_cntx_size fcoe_cntx_num;
1405 /* size of the Hash LUT */
1406 enum i40e_hash_lut_size hash_lut_size;
1407 /* enable FDIR filters for PF and its VFs */
1409 /* enable Ethertype filters for PF and its VFs */
1410 bool enable_ethtype;
1411 /* enable MAC/VLAN filters for PF and its VFs */
1412 bool enable_macvlan;
1415 /* Structure to hold device level control filter counts */
1416 struct i40e_control_filter_stats {
1417 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1418 u16 etype_used; /* Used perfect EtherType filters */
1419 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1420 u16 etype_free; /* Un-used perfect EtherType filters */
1423 enum i40e_reset_type {
1425 I40E_RESET_CORER = 1,
1426 I40E_RESET_GLOBR = 2,
1427 I40E_RESET_EMPR = 3,
1430 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1431 #define I40E_NVM_LLDP_CFG_PTR 0xD
1432 struct i40e_lldp_variables {
1442 /* Offsets into Alternate Ram */
1443 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1444 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1445 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1446 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1447 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1448 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1450 /* Alternate Ram Bandwidth Masks */
1451 #define I40E_ALT_BW_VALUE_MASK 0xFF
1452 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1453 #define I40E_ALT_BW_VALID_MASK 0x80000000
1455 /* RSS Hash Table Size */
1456 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1457 #endif /* _I40E_TYPE_H_ */