4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
52 #include "i40e_logs.h"
53 #include "i40e/i40e_register_x710_int.h"
54 #include "i40e/i40e_prototype.h"
55 #include "i40e/i40e_adminq_cmd.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
61 /* Maximun number of MAC addresses */
62 #define I40E_NUM_MACADDR_MAX 64
63 #define I40E_CLEAR_PXE_WAIT_MS 200
65 /* Maximun number of capability elements */
66 #define I40E_MAX_CAP_ELE_NUM 128
68 /* Wait count and inteval */
69 #define I40E_CHK_Q_ENA_COUNT 1000
70 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
72 /* Maximun number of VSI */
73 #define I40E_MAX_NUM_VSIS (384UL)
75 /* Bit shift and mask */
76 #define I40E_16_BIT_SHIFT 16
77 #define I40E_16_BIT_MASK 0xFFFF
78 #define I40E_32_BIT_SHIFT 32
79 #define I40E_32_BIT_MASK 0xFFFFFFFF
80 #define I40E_48_BIT_SHIFT 48
81 #define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL
83 /* Default queue interrupt throttling time in microseconds*/
84 #define I40E_ITR_INDEX_DEFAULT 0
85 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
86 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
88 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
90 #define I40E_RSS_OFFLOAD_ALL ( \
91 ETH_RSS_NONF_IPV4_UDP | \
92 ETH_RSS_NONF_IPV4_TCP | \
93 ETH_RSS_NONF_IPV4_SCTP | \
94 ETH_RSS_NONF_IPV4_OTHER | \
96 ETH_RSS_NONF_IPV6_UDP | \
97 ETH_RSS_NONF_IPV6_TCP | \
98 ETH_RSS_NONF_IPV6_SCTP | \
99 ETH_RSS_NONF_IPV6_OTHER | \
100 ETH_RSS_FRAG_IPV6 | \
103 /* All bits of RSS hash enable */
104 #define I40E_RSS_HENA_ALL ( \
105 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
106 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
107 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
108 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
109 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
110 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
111 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
112 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
113 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
114 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
115 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
116 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
117 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
118 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
120 static int eth_i40e_dev_init(\
121 __attribute__((unused)) struct eth_driver *eth_drv,
122 struct rte_eth_dev *eth_dev);
123 static int i40e_dev_configure(struct rte_eth_dev *dev);
124 static int i40e_dev_start(struct rte_eth_dev *dev);
125 static void i40e_dev_stop(struct rte_eth_dev *dev);
126 static void i40e_dev_close(struct rte_eth_dev *dev);
127 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
128 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
129 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
130 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
131 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
132 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
133 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
134 struct rte_eth_stats *stats);
135 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
136 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
140 static void i40e_dev_info_get(struct rte_eth_dev *dev,
141 struct rte_eth_dev_info *dev_info);
142 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
145 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
146 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
147 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
150 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
151 static int i40e_dev_led_on(struct rte_eth_dev *dev);
152 static int i40e_dev_led_off(struct rte_eth_dev *dev);
153 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
154 struct rte_eth_fc_conf *fc_conf);
155 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
156 struct rte_eth_pfc_conf *pfc_conf);
157 static void i40e_macaddr_add(struct rte_eth_dev *dev,
158 struct ether_addr *mac_addr,
161 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
162 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
163 struct rte_eth_rss_reta *reta_conf);
164 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
165 struct rte_eth_rss_reta *reta_conf);
167 static int i40e_get_cap(struct i40e_hw *hw);
168 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
169 static int i40e_pf_setup(struct i40e_pf *pf);
170 static int i40e_vsi_init(struct i40e_vsi *vsi);
171 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
172 bool offset_loaded, uint64_t *offset, uint64_t *stat);
173 static void i40e_stat_update_48(struct i40e_hw *hw,
179 static void i40e_pf_config_irq0(struct i40e_hw *hw);
180 static void i40e_dev_interrupt_handler(
181 __rte_unused struct rte_intr_handle *handle, void *param);
182 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
183 uint32_t base, uint32_t num);
184 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
185 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
187 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
189 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
190 static int i40e_veb_release(struct i40e_veb *veb);
191 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
192 struct i40e_vsi *vsi);
193 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
194 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
195 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
196 struct i40e_macvlan_filter *mv_f,
198 struct ether_addr *addr);
199 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
200 struct i40e_macvlan_filter *mv_f,
203 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
204 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
205 struct rte_eth_rss_conf *rss_conf);
206 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
207 struct rte_eth_rss_conf *rss_conf);
209 /* Default hash key buffer for RSS */
210 static uint32_t rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1];
212 static struct rte_pci_id pci_id_i40e_map[] = {
213 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
214 #include "rte_pci_dev_ids.h"
215 { .vendor_id = 0, /* sentinel */ },
218 static struct eth_dev_ops i40e_eth_dev_ops = {
219 .dev_configure = i40e_dev_configure,
220 .dev_start = i40e_dev_start,
221 .dev_stop = i40e_dev_stop,
222 .dev_close = i40e_dev_close,
223 .promiscuous_enable = i40e_dev_promiscuous_enable,
224 .promiscuous_disable = i40e_dev_promiscuous_disable,
225 .allmulticast_enable = i40e_dev_allmulticast_enable,
226 .allmulticast_disable = i40e_dev_allmulticast_disable,
227 .dev_set_link_up = i40e_dev_set_link_up,
228 .dev_set_link_down = i40e_dev_set_link_down,
229 .link_update = i40e_dev_link_update,
230 .stats_get = i40e_dev_stats_get,
231 .stats_reset = i40e_dev_stats_reset,
232 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
233 .dev_infos_get = i40e_dev_info_get,
234 .vlan_filter_set = i40e_vlan_filter_set,
235 .vlan_tpid_set = i40e_vlan_tpid_set,
236 .vlan_offload_set = i40e_vlan_offload_set,
237 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
238 .vlan_pvid_set = i40e_vlan_pvid_set,
239 .rx_queue_setup = i40e_dev_rx_queue_setup,
240 .rx_queue_release = i40e_dev_rx_queue_release,
241 .rx_queue_count = i40e_dev_rx_queue_count,
242 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
243 .tx_queue_setup = i40e_dev_tx_queue_setup,
244 .tx_queue_release = i40e_dev_tx_queue_release,
245 .dev_led_on = i40e_dev_led_on,
246 .dev_led_off = i40e_dev_led_off,
247 .flow_ctrl_set = i40e_flow_ctrl_set,
248 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
249 .mac_addr_add = i40e_macaddr_add,
250 .mac_addr_remove = i40e_macaddr_remove,
251 .reta_update = i40e_dev_rss_reta_update,
252 .reta_query = i40e_dev_rss_reta_query,
253 .rss_hash_update = i40e_dev_rss_hash_update,
254 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
257 static struct eth_driver rte_i40e_pmd = {
259 .name = "rte_i40e_pmd",
260 .id_table = pci_id_i40e_map,
261 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
263 .eth_dev_init = eth_i40e_dev_init,
264 .dev_private_size = sizeof(struct i40e_adapter),
268 i40e_prev_power_of_2(int n)
286 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
287 struct rte_eth_link *link)
289 struct rte_eth_link *dst = link;
290 struct rte_eth_link *src = &(dev->data->dev_link);
292 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
293 *(uint64_t *)src) == 0)
300 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
301 struct rte_eth_link *link)
303 struct rte_eth_link *dst = &(dev->data->dev_link);
304 struct rte_eth_link *src = link;
306 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
307 *(uint64_t *)src) == 0)
314 * Driver initialization routine.
315 * Invoked once at EAL init time.
316 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
319 rte_i40e_pmd_init(const char *name __rte_unused,
320 const char *params __rte_unused)
322 PMD_INIT_FUNC_TRACE();
323 rte_eth_driver_register(&rte_i40e_pmd);
328 static struct rte_driver rte_i40e_driver = {
330 .init = rte_i40e_pmd_init,
333 PMD_REGISTER_DRIVER(rte_i40e_driver);
336 eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
337 struct rte_eth_dev *dev)
339 struct rte_pci_device *pci_dev;
340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
342 struct i40e_vsi *vsi;
347 PMD_INIT_FUNC_TRACE();
349 dev->dev_ops = &i40e_eth_dev_ops;
350 dev->rx_pkt_burst = i40e_recv_pkts;
351 dev->tx_pkt_burst = i40e_xmit_pkts;
353 /* for secondary processes, we don't initialise any further as primary
354 * has already done this work. Only check we don't need a different
356 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
357 if (dev->data->scattered_rx)
358 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
361 pci_dev = dev->pci_dev;
362 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
363 pf->adapter->eth_dev = dev;
364 pf->dev_data = dev->data;
366 hw->back = I40E_PF_TO_ADAPTER(pf);
367 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
369 PMD_INIT_LOG(ERR, "Hardware is not available, "
370 "as address is NULL\n");
374 hw->vendor_id = pci_dev->id.vendor_id;
375 hw->device_id = pci_dev->id.device_id;
376 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
377 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
378 hw->bus.device = pci_dev->addr.devid;
379 hw->bus.func = pci_dev->addr.function;
381 /* Make sure all is clean before doing PF reset */
384 /* Reset here to make sure all is clean for each PF */
385 ret = i40e_pf_reset(hw);
387 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
391 /* Initialize the shared code (base driver) */
392 ret = i40e_init_shared_code(hw);
394 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
398 /* Initialize the parameters for adminq */
399 i40e_init_adminq_parameter(hw);
400 ret = i40e_init_adminq(hw);
401 if (ret != I40E_SUCCESS) {
402 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
405 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM "
406 "%02d.%02d.%02d eetrack %04x\n",
407 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
408 hw->aq.api_maj_ver, hw->aq.api_min_ver,
409 ((hw->nvm.version >> 12) & 0xf),
410 ((hw->nvm.version >> 4) & 0xff),
411 (hw->nvm.version & 0xf), hw->nvm.eetrack);
414 ret = i40e_aq_stop_lldp(hw, true, NULL);
415 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
416 PMD_INIT_LOG(INFO, "Failed to stop lldp\n");
419 i40e_clear_pxe_mode(hw);
421 /* Get hw capabilities */
422 ret = i40e_get_cap(hw);
423 if (ret != I40E_SUCCESS) {
424 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
425 goto err_get_capabilities;
428 /* Initialize parameters for PF */
429 ret = i40e_pf_parameter_init(dev);
431 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
432 goto err_parameter_init;
435 /* Initialize the queue management */
436 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
438 PMD_INIT_LOG(ERR, "Failed to init queue pool\n");
439 goto err_qp_pool_init;
441 ret = i40e_res_pool_init(&pf->msix_pool, 1,
442 hw->func_caps.num_msix_vectors - 1);
444 PMD_INIT_LOG(ERR, "Failed to init MSIX pool\n");
445 goto err_msix_pool_init;
448 /* Initialize lan hmc */
449 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
450 hw->func_caps.num_rx_qp, 0, 0);
451 if (ret != I40E_SUCCESS) {
452 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
453 goto err_init_lan_hmc;
456 /* Configure lan hmc */
457 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
458 if (ret != I40E_SUCCESS) {
459 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
460 goto err_configure_lan_hmc;
463 /* Get and check the mac address */
464 i40e_get_mac_addr(hw, hw->mac.addr);
465 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
466 PMD_INIT_LOG(ERR, "mac address is not valid");
468 goto err_get_mac_addr;
470 /* Copy the permanent MAC address */
471 ether_addr_copy((struct ether_addr *) hw->mac.addr,
472 (struct ether_addr *) hw->mac.perm_addr);
474 /* Disable flow control */
475 hw->fc.requested_mode = I40E_FC_NONE;
476 i40e_set_fc(hw, &aq_fail, TRUE);
478 /* PF setup, which includes VSI setup */
479 ret = i40e_pf_setup(pf);
481 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
482 goto err_setup_pf_switch;
487 /* Disable double vlan by default */
488 i40e_vsi_config_double_vlan(vsi, FALSE);
490 if (!vsi->max_macaddrs)
491 len = ETHER_ADDR_LEN;
493 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
495 /* Should be after VSI initialized */
496 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
497 if (!dev->data->mac_addrs) {
498 PMD_INIT_LOG(ERR, "Failed to allocated memory "
499 "for storing mac address");
500 goto err_get_mac_addr;
502 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
503 &dev->data->mac_addrs[0]);
505 /* initialize pf host driver to setup SRIOV resource if applicable */
506 i40e_pf_host_init(dev);
508 /* register callback func to eal lib */
509 rte_intr_callback_register(&(pci_dev->intr_handle),
510 i40e_dev_interrupt_handler, (void *)dev);
512 /* configure and enable device interrupt */
513 i40e_pf_config_irq0(hw);
514 i40e_pf_enable_irq0(hw);
516 /* enable uio intr after callback register */
517 rte_intr_enable(&(pci_dev->intr_handle));
522 rte_free(pf->main_vsi);
524 err_configure_lan_hmc:
525 (void)i40e_shutdown_lan_hmc(hw);
527 i40e_res_pool_destroy(&pf->msix_pool);
529 i40e_res_pool_destroy(&pf->qp_pool);
532 err_get_capabilities:
533 (void)i40e_shutdown_adminq(hw);
539 i40e_dev_configure(struct rte_eth_dev *dev)
541 return i40e_dev_init_vlan(dev);
545 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
547 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
548 uint16_t msix_vect = vsi->msix_intr;
551 for (i = 0; i < vsi->nb_qps; i++) {
552 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
553 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
557 if (vsi->type != I40E_VSI_SRIOV) {
558 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
559 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
563 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
564 vsi->user_param + (msix_vect - 1);
566 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
568 I40E_WRITE_FLUSH(hw);
571 static inline uint16_t
572 i40e_calc_itr_interval(int16_t interval)
574 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
575 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
577 /* Convert to hardware count, as writing each 1 represents 2 us */
582 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
585 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
586 uint16_t msix_vect = vsi->msix_intr;
587 uint16_t interval = i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
590 for (i = 0; i < vsi->nb_qps; i++)
591 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
593 /* Bind all RX queues to allocated MSIX interrupt */
594 for (i = 0; i < vsi->nb_qps; i++) {
595 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
596 (interval << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
597 ((vsi->base_queue + i + 1) <<
598 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
599 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
600 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
602 if (i == vsi->nb_qps - 1)
603 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
604 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
607 /* Write first RX queue to Link list register as the head element */
608 if (vsi->type != I40E_VSI_SRIOV) {
609 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
610 (vsi->base_queue << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
611 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
613 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
614 msix_vect - 1), interval);
616 /* Disable auto-mask on enabling of all none-zero interrupt */
617 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
618 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
622 /* num_msix_vectors_vf needs to minus irq0 */
623 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
624 vsi->user_param + (msix_vect - 1);
626 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
627 (vsi->base_queue << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
628 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
631 I40E_WRITE_FLUSH(hw);
635 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
637 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
638 uint16_t interval = i40e_calc_itr_interval(\
639 RTE_LIBRTE_I40E_ITR_INTERVAL);
641 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
642 I40E_PFINT_DYN_CTLN_INTENA_MASK |
643 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
644 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
645 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
649 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
651 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
653 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
656 static inline uint8_t
657 i40e_parse_link_speed(uint16_t eth_link_speed)
659 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
661 switch (eth_link_speed) {
662 case ETH_LINK_SPEED_40G:
663 link_speed = I40E_LINK_SPEED_40GB;
665 case ETH_LINK_SPEED_20G:
666 link_speed = I40E_LINK_SPEED_20GB;
668 case ETH_LINK_SPEED_10G:
669 link_speed = I40E_LINK_SPEED_10GB;
671 case ETH_LINK_SPEED_1000:
672 link_speed = I40E_LINK_SPEED_1GB;
674 case ETH_LINK_SPEED_100:
675 link_speed = I40E_LINK_SPEED_100MB;
683 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
685 enum i40e_status_code status;
686 struct i40e_aq_get_phy_abilities_resp phy_ab;
687 struct i40e_aq_set_phy_config phy_conf;
688 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
689 I40E_AQ_PHY_FLAG_PAUSE_RX |
690 I40E_AQ_PHY_FLAG_LOW_POWER;
691 const uint8_t advt = I40E_LINK_SPEED_40GB |
692 I40E_LINK_SPEED_10GB |
693 I40E_LINK_SPEED_1GB |
694 I40E_LINK_SPEED_100MB;
697 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
702 memset(&phy_conf, 0, sizeof(phy_conf));
704 /* bits 0-2 use the values from get_phy_abilities_resp */
706 abilities |= phy_ab.abilities & mask;
708 /* update ablities and speed */
709 if (abilities & I40E_AQ_PHY_AN_ENABLED)
710 phy_conf.link_speed = advt;
712 phy_conf.link_speed = force_speed;
714 phy_conf.abilities = abilities;
716 /* use get_phy_abilities_resp value for the rest */
717 phy_conf.phy_type = phy_ab.phy_type;
718 phy_conf.eee_capability = phy_ab.eee_capability;
719 phy_conf.eeer = phy_ab.eeer_val;
720 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
722 PMD_DRV_LOG(DEBUG, "\n\tCurrent: abilities %x, link_speed %x\n"
723 "\tConfig: abilities %x, link_speed %x",
724 phy_ab.abilities, phy_ab.link_speed,
725 phy_conf.abilities, phy_conf.link_speed);
727 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
735 i40e_apply_link_speed(struct rte_eth_dev *dev)
738 uint8_t abilities = 0;
739 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
740 struct rte_eth_conf *conf = &dev->data->dev_conf;
742 speed = i40e_parse_link_speed(conf->link_speed);
743 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
744 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
745 abilities |= I40E_AQ_PHY_AN_ENABLED;
747 abilities |= I40E_AQ_PHY_LINK_ENABLED;
749 return i40e_phy_conf_link(hw, abilities, speed);
753 i40e_dev_start(struct rte_eth_dev *dev)
755 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
757 struct i40e_vsi *vsi = pf->main_vsi;
760 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
761 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
762 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
763 dev->data->dev_conf.link_duplex,
769 ret = i40e_vsi_init(vsi);
770 if (ret != I40E_SUCCESS) {
771 PMD_DRV_LOG(ERR, "Failed to init VSI\n");
775 /* Map queues with MSIX interrupt */
776 i40e_vsi_queues_bind_intr(vsi);
777 i40e_vsi_enable_queues_intr(vsi);
779 /* Enable all queues which have been configured */
780 ret = i40e_vsi_switch_queues(vsi, TRUE);
781 if (ret != I40E_SUCCESS) {
782 PMD_DRV_LOG(ERR, "Failed to enable VSI\n");
786 /* Enable receiving broadcast packets */
787 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
788 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL);
789 if (ret != I40E_SUCCESS)
790 PMD_DRV_LOG(INFO, "fail to set vsi broadcast\n");
793 /* Apply link configure */
794 ret = i40e_apply_link_speed(dev);
795 if (I40E_SUCCESS != ret) {
796 PMD_DRV_LOG(ERR, "Fail to apply link setting\n");
803 i40e_vsi_switch_queues(vsi, FALSE);
804 i40e_dev_clear_queues(dev);
810 i40e_dev_stop(struct rte_eth_dev *dev)
812 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
813 struct i40e_vsi *vsi = pf->main_vsi;
815 /* Disable all queues */
816 i40e_vsi_switch_queues(vsi, FALSE);
818 /* Clear all queues and release memory */
819 i40e_dev_clear_queues(dev);
822 i40e_dev_set_link_down(dev);
824 /* un-map queues with interrupt registers */
825 i40e_vsi_disable_queues_intr(vsi);
826 i40e_vsi_queues_unbind_intr(vsi);
830 i40e_dev_close(struct rte_eth_dev *dev)
832 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
833 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
836 PMD_INIT_FUNC_TRACE();
840 /* Disable interrupt */
841 i40e_pf_disable_irq0(hw);
842 rte_intr_disable(&(dev->pci_dev->intr_handle));
844 /* shutdown and destroy the HMC */
845 i40e_shutdown_lan_hmc(hw);
847 /* release all the existing VSIs and VEBs */
848 i40e_vsi_release(pf->main_vsi);
850 /* shutdown the adminq */
851 i40e_aq_queue_shutdown(hw, true);
852 i40e_shutdown_adminq(hw);
854 i40e_res_pool_destroy(&pf->qp_pool);
855 i40e_res_pool_destroy(&pf->msix_pool);
857 /* force a PF reset to clean anything leftover */
858 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
859 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
860 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
861 I40E_WRITE_FLUSH(hw);
865 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
867 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
868 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
869 struct i40e_vsi *vsi = pf->main_vsi;
872 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
874 if (status != I40E_SUCCESS)
875 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous\n");
879 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
882 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
883 struct i40e_vsi *vsi = pf->main_vsi;
886 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
888 if (status != I40E_SUCCESS)
889 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous\n");
893 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
895 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
897 struct i40e_vsi *vsi = pf->main_vsi;
900 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
901 if (ret != I40E_SUCCESS)
902 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous\n");
906 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
910 struct i40e_vsi *vsi = pf->main_vsi;
913 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
914 vsi->seid, FALSE, NULL);
915 if (ret != I40E_SUCCESS)
916 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous\n");
920 * Set device link up.
923 i40e_dev_set_link_up(struct rte_eth_dev *dev)
925 /* re-apply link speed setting */
926 return i40e_apply_link_speed(dev);
930 * Set device link down.
933 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
935 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
936 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
939 return i40e_phy_conf_link(hw, abilities, speed);
943 i40e_dev_link_update(struct rte_eth_dev *dev,
944 __rte_unused int wait_to_complete)
946 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
947 struct i40e_link_status link_status;
948 struct rte_eth_link link, old;
951 memset(&link, 0, sizeof(link));
952 memset(&old, 0, sizeof(old));
953 memset(&link_status, 0, sizeof(link_status));
954 rte_i40e_dev_atomic_read_link_status(dev, &old);
956 /* Get link status information from hardware */
957 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
958 if (status != I40E_SUCCESS) {
959 link.link_speed = ETH_LINK_SPEED_100;
960 link.link_duplex = ETH_LINK_FULL_DUPLEX;
961 PMD_DRV_LOG(ERR, "Failed to get link info\n");
965 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
967 if (!link.link_status)
970 /* i40e uses full duplex only */
971 link.link_duplex = ETH_LINK_FULL_DUPLEX;
973 /* Parse the link status */
974 switch (link_status.link_speed) {
975 case I40E_LINK_SPEED_100MB:
976 link.link_speed = ETH_LINK_SPEED_100;
978 case I40E_LINK_SPEED_1GB:
979 link.link_speed = ETH_LINK_SPEED_1000;
981 case I40E_LINK_SPEED_10GB:
982 link.link_speed = ETH_LINK_SPEED_10G;
984 case I40E_LINK_SPEED_20GB:
985 link.link_speed = ETH_LINK_SPEED_20G;
987 case I40E_LINK_SPEED_40GB:
988 link.link_speed = ETH_LINK_SPEED_40G;
991 link.link_speed = ETH_LINK_SPEED_100;
996 rte_i40e_dev_atomic_write_link_status(dev, &link);
997 if (link.link_status == old.link_status)
1003 /* Get all the statistics of a VSI */
1005 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1007 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1008 struct i40e_eth_stats *nes = &vsi->eth_stats;
1009 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1010 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1012 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1013 vsi->offset_loaded, &oes->rx_bytes,
1015 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1016 vsi->offset_loaded, &oes->rx_unicast,
1018 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1019 vsi->offset_loaded, &oes->rx_multicast,
1020 &nes->rx_multicast);
1021 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1022 vsi->offset_loaded, &oes->rx_broadcast,
1023 &nes->rx_broadcast);
1024 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1025 &oes->rx_discards, &nes->rx_discards);
1026 /* GLV_REPC not supported */
1027 /* GLV_RMPC not supported */
1028 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1029 &oes->rx_unknown_protocol,
1030 &nes->rx_unknown_protocol);
1031 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1032 vsi->offset_loaded, &oes->tx_bytes,
1034 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1035 vsi->offset_loaded, &oes->tx_unicast,
1037 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1038 vsi->offset_loaded, &oes->tx_multicast,
1039 &nes->tx_multicast);
1040 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1041 vsi->offset_loaded, &oes->tx_broadcast,
1042 &nes->tx_broadcast);
1043 /* GLV_TDPC not supported */
1044 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1045 &oes->tx_errors, &nes->tx_errors);
1046 vsi->offset_loaded = true;
1048 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1049 printf("***************** VSI[%u] stats start *******************\n",
1051 printf("rx_bytes: %lu\n", nes->rx_bytes);
1052 printf("rx_unicast: %lu\n", nes->rx_unicast);
1053 printf("rx_multicast: %lu\n", nes->rx_multicast);
1054 printf("rx_broadcast: %lu\n", nes->rx_broadcast);
1055 printf("rx_discards: %lu\n", nes->rx_discards);
1056 printf("rx_unknown_protocol: %lu\n", nes->rx_unknown_protocol);
1057 printf("tx_bytes: %lu\n", nes->tx_bytes);
1058 printf("tx_unicast: %lu\n", nes->tx_unicast);
1059 printf("tx_multicast: %lu\n", nes->tx_multicast);
1060 printf("tx_broadcast: %lu\n", nes->tx_broadcast);
1061 printf("tx_discards: %lu\n", nes->tx_discards);
1062 printf("tx_errors: %lu\n", nes->tx_errors);
1063 printf("***************** VSI[%u] stats end *******************\n",
1065 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1068 /* Get all statistics of a port */
1070 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1073 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1074 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1075 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1076 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1078 /* Get statistics of struct i40e_eth_stats */
1079 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1080 I40E_GLPRT_GORCL(hw->port),
1081 pf->offset_loaded, &os->eth.rx_bytes,
1083 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1084 I40E_GLPRT_UPRCL(hw->port),
1085 pf->offset_loaded, &os->eth.rx_unicast,
1086 &ns->eth.rx_unicast);
1087 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1088 I40E_GLPRT_MPRCL(hw->port),
1089 pf->offset_loaded, &os->eth.rx_multicast,
1090 &ns->eth.rx_multicast);
1091 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1092 I40E_GLPRT_BPRCL(hw->port),
1093 pf->offset_loaded, &os->eth.rx_broadcast,
1094 &ns->eth.rx_broadcast);
1095 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1096 pf->offset_loaded, &os->eth.rx_discards,
1097 &ns->eth.rx_discards);
1098 /* GLPRT_REPC not supported */
1099 /* GLPRT_RMPC not supported */
1100 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1102 &os->eth.rx_unknown_protocol,
1103 &ns->eth.rx_unknown_protocol);
1104 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1105 I40E_GLPRT_GOTCL(hw->port),
1106 pf->offset_loaded, &os->eth.tx_bytes,
1108 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1109 I40E_GLPRT_UPTCL(hw->port),
1110 pf->offset_loaded, &os->eth.tx_unicast,
1111 &ns->eth.tx_unicast);
1112 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1113 I40E_GLPRT_MPTCL(hw->port),
1114 pf->offset_loaded, &os->eth.tx_multicast,
1115 &ns->eth.tx_multicast);
1116 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1117 I40E_GLPRT_BPTCL(hw->port),
1118 pf->offset_loaded, &os->eth.tx_broadcast,
1119 &ns->eth.tx_broadcast);
1120 i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port),
1121 pf->offset_loaded, &os->eth.tx_discards,
1122 &ns->eth.tx_discards);
1123 /* GLPRT_TEPC not supported */
1125 /* additional port specific stats */
1126 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1127 pf->offset_loaded, &os->tx_dropped_link_down,
1128 &ns->tx_dropped_link_down);
1129 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1130 pf->offset_loaded, &os->crc_errors,
1132 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1133 pf->offset_loaded, &os->illegal_bytes,
1134 &ns->illegal_bytes);
1135 /* GLPRT_ERRBC not supported */
1136 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1137 pf->offset_loaded, &os->mac_local_faults,
1138 &ns->mac_local_faults);
1139 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1140 pf->offset_loaded, &os->mac_remote_faults,
1141 &ns->mac_remote_faults);
1142 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1143 pf->offset_loaded, &os->rx_length_errors,
1144 &ns->rx_length_errors);
1145 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1146 pf->offset_loaded, &os->link_xon_rx,
1148 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1149 pf->offset_loaded, &os->link_xoff_rx,
1151 for (i = 0; i < 8; i++) {
1152 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1154 &os->priority_xon_rx[i],
1155 &ns->priority_xon_rx[i]);
1156 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1158 &os->priority_xoff_rx[i],
1159 &ns->priority_xoff_rx[i]);
1161 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1162 pf->offset_loaded, &os->link_xon_tx,
1164 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1165 pf->offset_loaded, &os->link_xoff_tx,
1167 for (i = 0; i < 8; i++) {
1168 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1170 &os->priority_xon_tx[i],
1171 &ns->priority_xon_tx[i]);
1172 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1174 &os->priority_xoff_tx[i],
1175 &ns->priority_xoff_tx[i]);
1176 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1178 &os->priority_xon_2_xoff[i],
1179 &ns->priority_xon_2_xoff[i]);
1181 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1182 I40E_GLPRT_PRC64L(hw->port),
1183 pf->offset_loaded, &os->rx_size_64,
1185 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1186 I40E_GLPRT_PRC127L(hw->port),
1187 pf->offset_loaded, &os->rx_size_127,
1189 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1190 I40E_GLPRT_PRC255L(hw->port),
1191 pf->offset_loaded, &os->rx_size_255,
1193 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1194 I40E_GLPRT_PRC511L(hw->port),
1195 pf->offset_loaded, &os->rx_size_511,
1197 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1198 I40E_GLPRT_PRC1023L(hw->port),
1199 pf->offset_loaded, &os->rx_size_1023,
1201 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1202 I40E_GLPRT_PRC1522L(hw->port),
1203 pf->offset_loaded, &os->rx_size_1522,
1205 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1206 I40E_GLPRT_PRC9522L(hw->port),
1207 pf->offset_loaded, &os->rx_size_big,
1209 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1210 pf->offset_loaded, &os->rx_undersize,
1212 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1213 pf->offset_loaded, &os->rx_fragments,
1215 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1216 pf->offset_loaded, &os->rx_oversize,
1218 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1219 pf->offset_loaded, &os->rx_jabber,
1221 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1222 I40E_GLPRT_PTC64L(hw->port),
1223 pf->offset_loaded, &os->tx_size_64,
1225 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1226 I40E_GLPRT_PTC127L(hw->port),
1227 pf->offset_loaded, &os->tx_size_127,
1229 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1230 I40E_GLPRT_PTC255L(hw->port),
1231 pf->offset_loaded, &os->tx_size_255,
1233 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1234 I40E_GLPRT_PTC511L(hw->port),
1235 pf->offset_loaded, &os->tx_size_511,
1237 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1238 I40E_GLPRT_PTC1023L(hw->port),
1239 pf->offset_loaded, &os->tx_size_1023,
1241 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1242 I40E_GLPRT_PTC1522L(hw->port),
1243 pf->offset_loaded, &os->tx_size_1522,
1245 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1246 I40E_GLPRT_PTC9522L(hw->port),
1247 pf->offset_loaded, &os->tx_size_big,
1249 /* GLPRT_MSPDC not supported */
1250 /* GLPRT_XEC not supported */
1252 pf->offset_loaded = true;
1254 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1255 ns->eth.rx_broadcast;
1256 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1257 ns->eth.tx_broadcast;
1258 stats->ibytes = ns->eth.rx_bytes;
1259 stats->obytes = ns->eth.tx_bytes;
1260 stats->oerrors = ns->eth.tx_errors;
1261 stats->imcasts = ns->eth.rx_multicast;
1264 i40e_update_vsi_stats(pf->main_vsi);
1266 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1267 printf("***************** PF stats start *******************\n");
1268 printf("rx_bytes: %lu\n", ns->eth.rx_bytes);
1269 printf("rx_unicast: %lu\n", ns->eth.rx_unicast);
1270 printf("rx_multicast: %lu\n", ns->eth.rx_multicast);
1271 printf("rx_broadcast: %lu\n", ns->eth.rx_broadcast);
1272 printf("rx_discards: %lu\n", ns->eth.rx_discards);
1273 printf("rx_unknown_protocol: %lu\n", ns->eth.rx_unknown_protocol);
1274 printf("tx_bytes: %lu\n", ns->eth.tx_bytes);
1275 printf("tx_unicast: %lu\n", ns->eth.tx_unicast);
1276 printf("tx_multicast: %lu\n", ns->eth.tx_multicast);
1277 printf("tx_broadcast: %lu\n", ns->eth.tx_broadcast);
1278 printf("tx_discards: %lu\n", ns->eth.tx_discards);
1279 printf("tx_errors: %lu\n", ns->eth.tx_errors);
1281 printf("tx_dropped_link_down: %lu\n", ns->tx_dropped_link_down);
1282 printf("crc_errors: %lu\n", ns->crc_errors);
1283 printf("illegal_bytes: %lu\n", ns->illegal_bytes);
1284 printf("error_bytes: %lu\n", ns->error_bytes);
1285 printf("mac_local_faults: %lu\n", ns->mac_local_faults);
1286 printf("mac_remote_faults: %lu\n", ns->mac_remote_faults);
1287 printf("rx_length_errors: %lu\n", ns->rx_length_errors);
1288 printf("link_xon_rx: %lu\n", ns->link_xon_rx);
1289 printf("link_xoff_rx: %lu\n", ns->link_xoff_rx);
1290 for (i = 0; i < 8; i++) {
1291 printf("priority_xon_rx[%d]: %lu\n",
1292 i, ns->priority_xon_rx[i]);
1293 printf("priority_xoff_rx[%d]: %lu\n",
1294 i, ns->priority_xoff_rx[i]);
1296 printf("link_xon_tx: %lu\n", ns->link_xon_tx);
1297 printf("link_xoff_tx: %lu\n", ns->link_xoff_tx);
1298 for (i = 0; i < 8; i++) {
1299 printf("priority_xon_tx[%d]: %lu\n",
1300 i, ns->priority_xon_tx[i]);
1301 printf("priority_xoff_tx[%d]: %lu\n",
1302 i, ns->priority_xoff_tx[i]);
1303 printf("priority_xon_2_xoff[%d]: %lu\n",
1304 i, ns->priority_xon_2_xoff[i]);
1306 printf("rx_size_64: %lu\n", ns->rx_size_64);
1307 printf("rx_size_127: %lu\n", ns->rx_size_127);
1308 printf("rx_size_255: %lu\n", ns->rx_size_255);
1309 printf("rx_size_511: %lu\n", ns->rx_size_511);
1310 printf("rx_size_1023: %lu\n", ns->rx_size_1023);
1311 printf("rx_size_1522: %lu\n", ns->rx_size_1522);
1312 printf("rx_size_big: %lu\n", ns->rx_size_big);
1313 printf("rx_undersize: %lu\n", ns->rx_undersize);
1314 printf("rx_fragments: %lu\n", ns->rx_fragments);
1315 printf("rx_oversize: %lu\n", ns->rx_oversize);
1316 printf("rx_jabber: %lu\n", ns->rx_jabber);
1317 printf("tx_size_64: %lu\n", ns->tx_size_64);
1318 printf("tx_size_127: %lu\n", ns->tx_size_127);
1319 printf("tx_size_255: %lu\n", ns->tx_size_255);
1320 printf("tx_size_511: %lu\n", ns->tx_size_511);
1321 printf("tx_size_1023: %lu\n", ns->tx_size_1023);
1322 printf("tx_size_1522: %lu\n", ns->tx_size_1522);
1323 printf("tx_size_big: %lu\n", ns->tx_size_big);
1324 printf("mac_short_packet_dropped: %lu\n",
1325 ns->mac_short_packet_dropped);
1326 printf("checksum_error: %lu\n", ns->checksum_error);
1327 printf("***************** PF stats end ********************\n");
1328 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1331 /* Reset the statistics */
1333 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1335 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1337 /* It results in reloading the start point of each counter */
1338 pf->offset_loaded = false;
1342 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1343 __rte_unused uint16_t queue_id,
1344 __rte_unused uint8_t stat_idx,
1345 __rte_unused uint8_t is_rx)
1347 PMD_INIT_FUNC_TRACE();
1353 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1356 struct i40e_vsi *vsi = pf->main_vsi;
1358 dev_info->max_rx_queues = vsi->nb_qps;
1359 dev_info->max_tx_queues = vsi->nb_qps;
1360 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1361 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1362 dev_info->max_mac_addrs = vsi->max_macaddrs;
1363 dev_info->max_vfs = dev->pci_dev->max_vfs;
1364 dev_info->rx_offload_capa =
1365 DEV_RX_OFFLOAD_VLAN_STRIP |
1366 DEV_RX_OFFLOAD_IPV4_CKSUM |
1367 DEV_RX_OFFLOAD_UDP_CKSUM |
1368 DEV_RX_OFFLOAD_TCP_CKSUM;
1369 dev_info->tx_offload_capa =
1370 DEV_TX_OFFLOAD_VLAN_INSERT |
1371 DEV_TX_OFFLOAD_IPV4_CKSUM |
1372 DEV_TX_OFFLOAD_UDP_CKSUM |
1373 DEV_TX_OFFLOAD_TCP_CKSUM |
1374 DEV_TX_OFFLOAD_SCTP_CKSUM;
1378 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1380 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1381 struct i40e_vsi *vsi = pf->main_vsi;
1382 PMD_INIT_FUNC_TRACE();
1385 return i40e_vsi_add_vlan(vsi, vlan_id);
1387 return i40e_vsi_delete_vlan(vsi, vlan_id);
1391 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1392 __rte_unused uint16_t tpid)
1394 PMD_INIT_FUNC_TRACE();
1398 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1400 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1401 struct i40e_vsi *vsi = pf->main_vsi;
1403 if (mask & ETH_VLAN_STRIP_MASK) {
1404 /* Enable or disable VLAN stripping */
1405 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1406 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1408 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1411 if (mask & ETH_VLAN_EXTEND_MASK) {
1412 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1413 i40e_vsi_config_double_vlan(vsi, TRUE);
1415 i40e_vsi_config_double_vlan(vsi, FALSE);
1420 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1421 __rte_unused uint16_t queue,
1422 __rte_unused int on)
1424 PMD_INIT_FUNC_TRACE();
1428 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431 struct i40e_vsi *vsi = pf->main_vsi;
1432 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1433 struct i40e_vsi_vlan_pvid_info info;
1435 memset(&info, 0, sizeof(info));
1438 info.config.pvid = pvid;
1440 info.config.reject.tagged =
1441 data->dev_conf.txmode.hw_vlan_reject_tagged;
1442 info.config.reject.untagged =
1443 data->dev_conf.txmode.hw_vlan_reject_untagged;
1446 return i40e_vsi_vlan_pvid_set(vsi, &info);
1450 i40e_dev_led_on(struct rte_eth_dev *dev)
1452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453 uint32_t mode = i40e_led_get(hw);
1456 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1462 i40e_dev_led_off(struct rte_eth_dev *dev)
1464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1465 uint32_t mode = i40e_led_get(hw);
1468 i40e_led_set(hw, 0, false);
1474 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1475 __rte_unused struct rte_eth_fc_conf *fc_conf)
1477 PMD_INIT_FUNC_TRACE();
1483 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1484 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1486 PMD_INIT_FUNC_TRACE();
1491 /* Add a MAC address, and update filters */
1493 i40e_macaddr_add(struct rte_eth_dev *dev,
1494 struct ether_addr *mac_addr,
1495 __attribute__((unused)) uint32_t index,
1496 __attribute__((unused)) uint32_t pool)
1498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1499 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1500 struct i40e_vsi *vsi = pf->main_vsi;
1501 struct ether_addr old_mac;
1504 if (!is_valid_assigned_ether_addr(mac_addr)) {
1505 PMD_DRV_LOG(ERR, "Invalid ethernet address\n");
1509 if (is_same_ether_addr(mac_addr, &(pf->dev_addr))) {
1510 PMD_DRV_LOG(INFO, "Ignore adding permanent mac address\n");
1514 /* Write mac address */
1515 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1516 mac_addr->addr_bytes, NULL);
1517 if (ret != I40E_SUCCESS) {
1518 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1522 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1523 (void)rte_memcpy(hw->mac.addr, mac_addr->addr_bytes,
1526 ret = i40e_vsi_add_mac(vsi, mac_addr);
1527 if (ret != I40E_SUCCESS) {
1528 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
1532 ether_addr_copy(mac_addr, &pf->dev_addr);
1533 i40e_vsi_delete_mac(vsi, &old_mac);
1536 /* Remove a MAC address, and update filters */
1538 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1540 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1541 struct i40e_vsi *vsi = pf->main_vsi;
1542 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1543 struct ether_addr *macaddr;
1545 struct i40e_hw *hw =
1546 I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1548 if (index >= vsi->max_macaddrs)
1551 macaddr = &(data->mac_addrs[index]);
1552 if (!is_valid_assigned_ether_addr(macaddr))
1555 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_ONLY,
1556 hw->mac.perm_addr, NULL);
1557 if (ret != I40E_SUCCESS) {
1558 PMD_DRV_LOG(ERR, "Failed to write mac address\n");
1562 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);
1564 ret = i40e_vsi_delete_mac(vsi, macaddr);
1565 if (ret != I40E_SUCCESS)
1568 /* Clear device address as it has been removed */
1569 if (is_same_ether_addr(&(pf->dev_addr), macaddr))
1570 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1574 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1575 struct rte_eth_rss_reta *reta_conf)
1577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1581 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1583 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1585 mask = (uint8_t)((reta_conf->mask_hi >>
1594 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1596 for (j = 0, lut = 0; j < 4; j++) {
1597 if (mask & (0x1 << j))
1598 lut |= reta_conf->reta[i + j] << (8 * j);
1600 lut |= l & (0xFF << (8 * j));
1602 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1609 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1610 struct rte_eth_rss_reta *reta_conf)
1612 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614 uint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;
1616 for (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
1618 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
1620 mask = (uint8_t)((reta_conf->mask_hi >>
1626 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1627 for (j = 0; j < 4; j++) {
1628 if (mask & (0x1 << j))
1629 reta_conf->reta[i + j] =
1630 (uint8_t)((lut >> (8 * j)) & 0xFF);
1638 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1639 * @hw: pointer to the HW structure
1640 * @mem: pointer to mem struct to fill out
1641 * @size: size of memory requested
1642 * @alignment: what to align the allocation to
1644 enum i40e_status_code
1645 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1646 struct i40e_dma_mem *mem,
1650 static uint64_t id = 0;
1651 const struct rte_memzone *mz = NULL;
1652 char z_name[RTE_MEMZONE_NAMESIZE];
1655 return I40E_ERR_PARAM;
1658 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1659 #ifdef RTE_LIBRTE_XEN_DOM0
1660 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1663 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
1666 return I40E_ERR_NO_MEMORY;
1671 #ifdef RTE_LIBRTE_XEN_DOM0
1672 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1674 mem->pa = mz->phys_addr;
1677 return I40E_SUCCESS;
1681 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
1682 * @hw: pointer to the HW structure
1683 * @mem: ptr to mem struct to free
1685 enum i40e_status_code
1686 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1687 struct i40e_dma_mem *mem)
1689 if (!mem || !mem->va)
1690 return I40E_ERR_PARAM;
1695 return I40E_SUCCESS;
1699 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
1700 * @hw: pointer to the HW structure
1701 * @mem: pointer to mem struct to fill out
1702 * @size: size of memory requested
1704 enum i40e_status_code
1705 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1706 struct i40e_virt_mem *mem,
1710 return I40E_ERR_PARAM;
1713 mem->va = rte_zmalloc("i40e", size, 0);
1716 return I40E_SUCCESS;
1718 return I40E_ERR_NO_MEMORY;
1722 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
1723 * @hw: pointer to the HW structure
1724 * @mem: pointer to mem struct to free
1726 enum i40e_status_code
1727 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1728 struct i40e_virt_mem *mem)
1731 return I40E_ERR_PARAM;
1736 return I40E_SUCCESS;
1740 i40e_init_spinlock_d(struct i40e_spinlock *sp)
1742 rte_spinlock_init(&sp->spinlock);
1746 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
1748 rte_spinlock_lock(&sp->spinlock);
1752 i40e_release_spinlock_d(struct i40e_spinlock *sp)
1754 rte_spinlock_unlock(&sp->spinlock);
1758 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
1764 * Get the hardware capabilities, which will be parsed
1765 * and saved into struct i40e_hw.
1768 i40e_get_cap(struct i40e_hw *hw)
1770 struct i40e_aqc_list_capabilities_element_resp *buf;
1771 uint16_t len, size = 0;
1774 /* Calculate a huge enough buff for saving response data temporarily */
1775 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
1776 I40E_MAX_CAP_ELE_NUM;
1777 buf = rte_zmalloc("i40e", len, 0);
1779 PMD_DRV_LOG(ERR, "Failed to allocate memory\n");
1780 return I40E_ERR_NO_MEMORY;
1783 /* Get, parse the capabilities and save it to hw */
1784 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
1785 i40e_aqc_opc_list_func_capabilities, NULL);
1786 if (ret != I40E_SUCCESS)
1787 PMD_DRV_LOG(ERR, "Failed to discover capabilities\n");
1789 /* Free the temporary buffer after being used */
1796 i40e_pf_parameter_init(struct rte_eth_dev *dev)
1798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1799 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1800 uint16_t sum_queues = 0, sum_vsis;
1802 /* First check if FW support SRIOV */
1803 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
1804 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV\n");
1808 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
1809 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
1810 PMD_INIT_LOG(INFO, "Max supported VSIs:%u\n", pf->max_num_vsi);
1811 /* Allocate queues for pf */
1812 if (hw->func_caps.rss) {
1813 pf->flags |= I40E_FLAG_RSS;
1814 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
1815 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
1816 pf->lan_nb_qps = i40e_prev_power_of_2(pf->lan_nb_qps);
1819 sum_queues = pf->lan_nb_qps;
1820 /* Default VSI is not counted in */
1822 PMD_INIT_LOG(INFO, "PF queue pairs:%u\n", pf->lan_nb_qps);
1824 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
1825 pf->flags |= I40E_FLAG_SRIOV;
1826 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
1827 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
1828 PMD_INIT_LOG(ERR, "Config VF number %u, "
1829 "max supported %u.\n", dev->pci_dev->max_vfs,
1830 hw->func_caps.num_vfs);
1833 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
1834 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
1835 "max support %u queues.\n", pf->vf_nb_qps,
1836 I40E_MAX_QP_NUM_PER_VF);
1839 pf->vf_num = dev->pci_dev->max_vfs;
1840 sum_queues += pf->vf_nb_qps * pf->vf_num;
1841 sum_vsis += pf->vf_num;
1842 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u\n",
1843 pf->vf_num, pf->vf_nb_qps);
1847 if (hw->func_caps.vmdq) {
1848 pf->flags |= I40E_FLAG_VMDQ;
1849 pf->vmdq_nb_qps = I40E_DEFAULT_QP_NUM_VMDQ;
1850 sum_queues += pf->vmdq_nb_qps;
1852 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u\n", pf->vmdq_nb_qps);
1855 if (hw->func_caps.fd) {
1856 pf->flags |= I40E_FLAG_FDIR;
1857 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
1859 * Each flow director consumes one VSI and one queue,
1860 * but can't calculate out predictably here.
1864 if (sum_vsis > pf->max_num_vsi ||
1865 sum_queues > hw->func_caps.num_rx_qp) {
1866 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied\n");
1867 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u\n",
1868 pf->max_num_vsi, sum_vsis);
1869 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u\n",
1870 hw->func_caps.num_rx_qp, sum_queues);
1874 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr cause */
1875 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
1876 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough\n",
1877 sum_vsis, hw->func_caps.num_msix_vectors);
1880 return I40E_SUCCESS;
1884 i40e_pf_get_switch_config(struct i40e_pf *pf)
1886 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1887 struct i40e_aqc_get_switch_config_resp *switch_config;
1888 struct i40e_aqc_switch_config_element_resp *element;
1889 uint16_t start_seid = 0, num_reported;
1892 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
1893 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
1894 if (!switch_config) {
1895 PMD_DRV_LOG(ERR, "Failed to allocated memory\n");
1899 /* Get the switch configurations */
1900 ret = i40e_aq_get_switch_config(hw, switch_config,
1901 I40E_AQ_LARGE_BUF, &start_seid, NULL);
1902 if (ret != I40E_SUCCESS) {
1903 PMD_DRV_LOG(ERR, "Failed to get switch configurations\n");
1906 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
1907 if (num_reported != 1) { /* The number should be 1 */
1908 PMD_DRV_LOG(ERR, "Wrong number of switch config reported\n");
1912 /* Parse the switch configuration elements */
1913 element = &(switch_config->element[0]);
1914 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
1915 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
1916 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
1918 PMD_DRV_LOG(INFO, "Unknown element type\n");
1921 rte_free(switch_config);
1927 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
1930 struct pool_entry *entry;
1932 if (pool == NULL || num == 0)
1935 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
1936 if (entry == NULL) {
1937 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1942 /* queue heap initialize */
1943 pool->num_free = num;
1944 pool->num_alloc = 0;
1946 LIST_INIT(&pool->alloc_list);
1947 LIST_INIT(&pool->free_list);
1949 /* Initialize element */
1953 LIST_INSERT_HEAD(&pool->free_list, entry, next);
1958 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
1960 struct pool_entry *entry;
1965 LIST_FOREACH(entry, &pool->alloc_list, next) {
1966 LIST_REMOVE(entry, next);
1970 LIST_FOREACH(entry, &pool->free_list, next) {
1971 LIST_REMOVE(entry, next);
1976 pool->num_alloc = 0;
1978 LIST_INIT(&pool->alloc_list);
1979 LIST_INIT(&pool->free_list);
1983 i40e_res_pool_free(struct i40e_res_pool_info *pool,
1986 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
1987 uint32_t pool_offset;
1991 PMD_DRV_LOG(ERR, "Invalid parameter\n");
1995 pool_offset = base - pool->base;
1996 /* Lookup in alloc list */
1997 LIST_FOREACH(entry, &pool->alloc_list, next) {
1998 if (entry->base == pool_offset) {
1999 valid_entry = entry;
2000 LIST_REMOVE(entry, next);
2005 /* Not find, return */
2006 if (valid_entry == NULL) {
2007 PMD_DRV_LOG(ERR, "Failed to find entry\n");
2012 * Found it, move it to free list and try to merge.
2013 * In order to make merge easier, always sort it by qbase.
2014 * Find adjacent prev and last entries.
2017 LIST_FOREACH(entry, &pool->free_list, next) {
2018 if (entry->base > valid_entry->base) {
2026 /* Try to merge with next one*/
2028 /* Merge with next one */
2029 if (valid_entry->base + valid_entry->len == next->base) {
2030 next->base = valid_entry->base;
2031 next->len += valid_entry->len;
2032 rte_free(valid_entry);
2039 /* Merge with previous one */
2040 if (prev->base + prev->len == valid_entry->base) {
2041 prev->len += valid_entry->len;
2042 /* If it merge with next one, remove next node */
2044 LIST_REMOVE(valid_entry, next);
2045 rte_free(valid_entry);
2047 rte_free(valid_entry);
2053 /* Not find any entry to merge, insert */
2056 LIST_INSERT_AFTER(prev, valid_entry, next);
2057 else if (next != NULL)
2058 LIST_INSERT_BEFORE(next, valid_entry, next);
2059 else /* It's empty list, insert to head */
2060 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2063 pool->num_free += valid_entry->len;
2064 pool->num_alloc -= valid_entry->len;
2070 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2073 struct pool_entry *entry, *valid_entry;
2075 if (pool == NULL || num == 0) {
2076 PMD_DRV_LOG(ERR, "Invalid parameter\n");
2080 if (pool->num_free < num) {
2081 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u\n",
2082 num, pool->num_free);
2087 /* Lookup in free list and find most fit one */
2088 LIST_FOREACH(entry, &pool->free_list, next) {
2089 if (entry->len >= num) {
2091 if (entry->len == num) {
2092 valid_entry = entry;
2095 if (valid_entry == NULL || valid_entry->len > entry->len)
2096 valid_entry = entry;
2100 /* Not find one to satisfy the request, return */
2101 if (valid_entry == NULL) {
2102 PMD_DRV_LOG(ERR, "No valid entry found\n");
2106 * The entry have equal queue number as requested,
2107 * remove it from alloc_list.
2109 if (valid_entry->len == num) {
2110 LIST_REMOVE(valid_entry, next);
2113 * The entry have more numbers than requested,
2114 * create a new entry for alloc_list and minus its
2115 * queue base and number in free_list.
2117 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2118 if (entry == NULL) {
2119 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2123 entry->base = valid_entry->base;
2125 valid_entry->base += num;
2126 valid_entry->len -= num;
2127 valid_entry = entry;
2130 /* Insert it into alloc list, not sorted */
2131 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2133 pool->num_free -= valid_entry->len;
2134 pool->num_alloc += valid_entry->len;
2136 return (valid_entry->base + pool->base);
2140 * bitmap_is_subset - Check whether src2 is subset of src1
2143 bitmap_is_subset(uint8_t src1, uint8_t src2)
2145 return !((src1 ^ src2) & src2);
2149 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2151 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2153 /* If DCB is not supported, only default TC is supported */
2154 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2155 PMD_DRV_LOG(ERR, "DCB is not enabled, "
2156 "only TC0 is supported\n");
2160 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2161 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2162 "HW support 0x%x\n", hw->func_caps.enabled_tcmap,
2166 return I40E_SUCCESS;
2170 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2171 struct i40e_vsi_vlan_pvid_info *info)
2174 struct i40e_vsi_context ctxt;
2175 uint8_t vlan_flags = 0;
2178 if (vsi == NULL || info == NULL) {
2179 PMD_DRV_LOG(ERR, "invalid parameters\n");
2180 return I40E_ERR_PARAM;
2184 vsi->info.pvid = info->config.pvid;
2186 * If insert pvid is enabled, only tagged pkts are
2187 * allowed to be sent out.
2189 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2190 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2193 if (info->config.reject.tagged == 0)
2194 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2196 if (info->config.reject.untagged == 0)
2197 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2199 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2200 I40E_AQ_VSI_PVLAN_MODE_MASK);
2201 vsi->info.port_vlan_flags |= vlan_flags;
2202 vsi->info.valid_sections =
2203 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2204 memset(&ctxt, 0, sizeof(ctxt));
2205 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2206 ctxt.seid = vsi->seid;
2208 hw = I40E_VSI_TO_HW(vsi);
2209 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2210 if (ret != I40E_SUCCESS)
2211 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2217 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2219 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2221 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2223 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2224 if (ret != I40E_SUCCESS)
2228 PMD_DRV_LOG(ERR, "seid not valid\n");
2232 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2233 tc_bw_data.tc_valid_bits = enabled_tcmap;
2234 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2235 tc_bw_data.tc_bw_credits[i] =
2236 (enabled_tcmap & (1 << i)) ? 1 : 0;
2238 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2239 if (ret != I40E_SUCCESS) {
2240 PMD_DRV_LOG(ERR, "Failed to configure TC BW\n");
2244 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2245 sizeof(vsi->info.qs_handle));
2246 return I40E_SUCCESS;
2250 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2251 struct i40e_aqc_vsi_properties_data *info,
2252 uint8_t enabled_tcmap)
2254 int ret, total_tc = 0, i;
2255 uint16_t qpnum_per_tc, bsf, qp_idx;
2257 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2258 if (ret != I40E_SUCCESS)
2261 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2262 if (enabled_tcmap & (1 << i))
2264 vsi->enabled_tc = enabled_tcmap;
2266 /* Number of queues per enabled TC */
2267 qpnum_per_tc = i40e_prev_power_of_2(vsi->nb_qps / total_tc);
2268 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2269 bsf = rte_bsf32(qpnum_per_tc);
2271 /* Adjust the queue number to actual queues that can be applied */
2272 vsi->nb_qps = qpnum_per_tc * total_tc;
2275 * Configure TC and queue mapping parameters, for enabled TC,
2276 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2277 * default queue will serve it.
2280 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2281 if (vsi->enabled_tc & (1 << i)) {
2282 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2283 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2284 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2285 qp_idx += qpnum_per_tc;
2287 info->tc_mapping[i] = 0;
2290 /* Associate queue number with VSI */
2291 if (vsi->type == I40E_VSI_SRIOV) {
2292 info->mapping_flags |=
2293 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2294 for (i = 0; i < vsi->nb_qps; i++)
2295 info->queue_mapping[i] =
2296 rte_cpu_to_le_16(vsi->base_queue + i);
2298 info->mapping_flags |=
2299 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2300 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2302 info->valid_sections =
2303 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2305 return I40E_SUCCESS;
2309 i40e_veb_release(struct i40e_veb *veb)
2311 struct i40e_vsi *vsi;
2314 if (veb == NULL || veb->associate_vsi == NULL)
2317 if (!TAILQ_EMPTY(&veb->head)) {
2318 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove\n");
2322 vsi = veb->associate_vsi;
2323 hw = I40E_VSI_TO_HW(vsi);
2325 vsi->uplink_seid = veb->uplink_seid;
2326 i40e_aq_delete_element(hw, veb->seid, NULL);
2329 return I40E_SUCCESS;
2333 static struct i40e_veb *
2334 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2336 struct i40e_veb *veb;
2340 if (NULL == pf || vsi == NULL) {
2341 PMD_DRV_LOG(ERR, "veb setup failed, "
2342 "associated VSI shouldn't null\n");
2345 hw = I40E_PF_TO_HW(pf);
2347 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2349 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb\n");
2353 veb->associate_vsi = vsi;
2354 TAILQ_INIT(&veb->head);
2355 veb->uplink_seid = vsi->uplink_seid;
2357 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2358 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2360 if (ret != I40E_SUCCESS) {
2361 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d\n",
2362 hw->aq.asq_last_status);
2366 /* get statistics index */
2367 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2368 &veb->stats_idx, NULL, NULL, NULL);
2369 if (ret != I40E_SUCCESS) {
2370 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d\n",
2371 hw->aq.asq_last_status);
2375 /* Get VEB bandwidth, to be implemented */
2376 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2377 vsi->uplink_seid = veb->seid;
2386 i40e_vsi_release(struct i40e_vsi *vsi)
2390 struct i40e_vsi_list *vsi_list;
2392 struct i40e_mac_filter *f;
2395 return I40E_SUCCESS;
2397 pf = I40E_VSI_TO_PF(vsi);
2398 hw = I40E_VSI_TO_HW(vsi);
2400 /* VSI has child to attach, release child first */
2402 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2403 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2405 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2407 i40e_veb_release(vsi->veb);
2410 /* Remove all macvlan filters of the VSI */
2411 i40e_vsi_remove_all_macvlan_filter(vsi);
2412 TAILQ_FOREACH(f, &vsi->mac_list, next)
2415 if (vsi->type != I40E_VSI_MAIN) {
2416 /* Remove vsi from parent's sibling list */
2417 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2418 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL\n");
2419 return I40E_ERR_PARAM;
2421 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2422 &vsi->sib_vsi_list, list);
2424 /* Remove all switch element of the VSI */
2425 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2426 if (ret != I40E_SUCCESS)
2427 PMD_DRV_LOG(ERR, "Failed to delete element\n");
2429 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2431 if (vsi->type != I40E_VSI_SRIOV)
2432 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2435 return I40E_SUCCESS;
2439 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2441 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2442 struct i40e_aqc_remove_macvlan_element_data def_filter;
2445 if (vsi->type != I40E_VSI_MAIN)
2446 return I40E_ERR_CONFIG;
2447 memset(&def_filter, 0, sizeof(def_filter));
2448 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2450 def_filter.vlan_tag = 0;
2451 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2452 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2453 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2454 if (ret != I40E_SUCCESS) {
2455 struct i40e_mac_filter *f;
2457 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2458 "macvlan filter\n");
2459 /* It needs to add the permanent mac into mac list */
2460 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2462 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
2463 return I40E_ERR_NO_MEMORY;
2465 (void)rte_memcpy(&f->macaddr.addr_bytes, hw->mac.perm_addr,
2467 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2473 return i40e_vsi_add_mac(vsi, (struct ether_addr *)(hw->mac.perm_addr));
2477 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2479 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2480 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2481 struct i40e_hw *hw = &vsi->adapter->hw;
2485 memset(&bw_config, 0, sizeof(bw_config));
2486 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2487 if (ret != I40E_SUCCESS) {
2488 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth "
2489 "configuration %u\n", hw->aq.asq_last_status);
2493 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2494 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2495 &ets_sla_config, NULL);
2496 if (ret != I40E_SUCCESS) {
2497 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2498 "configuration %u\n", hw->aq.asq_last_status);
2502 /* Not store the info yet, just print out */
2503 PMD_DRV_LOG(INFO, "VSI bw limit:%u\n", bw_config.port_bw_limit);
2504 PMD_DRV_LOG(INFO, "VSI max_bw:%u\n", bw_config.max_bw);
2505 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2506 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u\n", i,
2507 ets_sla_config.share_credits[i]);
2508 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u\n", i,
2509 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2510 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2511 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2520 i40e_vsi_setup(struct i40e_pf *pf,
2521 enum i40e_vsi_type type,
2522 struct i40e_vsi *uplink_vsi,
2523 uint16_t user_param)
2525 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2526 struct i40e_vsi *vsi;
2528 struct i40e_vsi_context ctxt;
2529 struct ether_addr broadcast =
2530 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2532 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2533 PMD_DRV_LOG(ERR, "VSI setup failed, "
2534 "VSI link shouldn't be NULL\n");
2538 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2539 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2540 "uplink VSI should be NULL\n");
2544 /* If uplink vsi didn't setup VEB, create one first */
2545 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2546 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2548 if (NULL == uplink_vsi->veb) {
2549 PMD_DRV_LOG(ERR, "VEB setup failed\n");
2554 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2556 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi\n");
2559 TAILQ_INIT(&vsi->mac_list);
2561 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2562 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2563 vsi->parent_vsi = uplink_vsi;
2564 vsi->user_param = user_param;
2565 /* Allocate queues */
2566 switch (vsi->type) {
2567 case I40E_VSI_MAIN :
2568 vsi->nb_qps = pf->lan_nb_qps;
2570 case I40E_VSI_SRIOV :
2571 vsi->nb_qps = pf->vf_nb_qps;
2576 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2578 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2582 vsi->base_queue = ret;
2584 /* VF has MSIX interrupt in VF range, don't allocate here */
2585 if (type != I40E_VSI_SRIOV) {
2586 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2588 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2589 goto fail_queue_alloc;
2591 vsi->msix_intr = ret;
2595 if (type == I40E_VSI_MAIN) {
2596 /* For main VSI, no need to add since it's default one */
2597 vsi->uplink_seid = pf->mac_seid;
2598 vsi->seid = pf->main_vsi_seid;
2599 /* Bind queues with specific MSIX interrupt */
2601 * Needs 2 interrupt at least, one for misc cause which will
2602 * enabled from OS side, Another for queues binding the
2603 * interrupt from device side only.
2606 /* Get default VSI parameters from hardware */
2607 memset(&ctxt, 0, sizeof(ctxt));
2608 ctxt.seid = vsi->seid;
2609 ctxt.pf_num = hw->pf_id;
2610 ctxt.uplink_seid = vsi->uplink_seid;
2612 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2613 if (ret != I40E_SUCCESS) {
2614 PMD_DRV_LOG(ERR, "Failed to get VSI params\n");
2615 goto fail_msix_alloc;
2617 (void)rte_memcpy(&vsi->info, &ctxt.info,
2618 sizeof(struct i40e_aqc_vsi_properties_data));
2619 vsi->vsi_id = ctxt.vsi_number;
2620 vsi->info.valid_sections = 0;
2622 /* Configure tc, enabled TC0 only */
2623 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
2625 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth\n");
2626 goto fail_msix_alloc;
2629 /* TC, queue mapping */
2630 memset(&ctxt, 0, sizeof(ctxt));
2631 vsi->info.valid_sections |=
2632 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2633 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2634 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2635 (void)rte_memcpy(&ctxt.info, &vsi->info,
2636 sizeof(struct i40e_aqc_vsi_properties_data));
2637 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2638 I40E_DEFAULT_TCMAP);
2639 if (ret != I40E_SUCCESS) {
2640 PMD_DRV_LOG(ERR, "Failed to configure "
2641 "TC queue mapping\n");
2642 goto fail_msix_alloc;
2644 ctxt.seid = vsi->seid;
2645 ctxt.pf_num = hw->pf_id;
2646 ctxt.uplink_seid = vsi->uplink_seid;
2649 /* Update VSI parameters */
2650 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2651 if (ret != I40E_SUCCESS) {
2652 PMD_DRV_LOG(ERR, "Failed to update VSI params\n");
2653 goto fail_msix_alloc;
2656 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
2657 sizeof(vsi->info.tc_mapping));
2658 (void)rte_memcpy(&vsi->info.queue_mapping,
2659 &ctxt.info.queue_mapping,
2660 sizeof(vsi->info.queue_mapping));
2661 vsi->info.mapping_flags = ctxt.info.mapping_flags;
2662 vsi->info.valid_sections = 0;
2664 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
2668 * Updating default filter settings are necessary to prevent
2669 * reception of tagged packets.
2670 * Some old firmware configurations load a default macvlan
2671 * filter which accepts both tagged and untagged packets.
2672 * The updating is to use a normal filter instead if needed.
2673 * For NVM 4.2.2 or after, the updating is not needed anymore.
2674 * The firmware with correct configurations load the default
2675 * macvlan filter which is expected and cannot be removed.
2677 i40e_update_default_filter_setting(vsi);
2678 } else if (type == I40E_VSI_SRIOV) {
2679 memset(&ctxt, 0, sizeof(ctxt));
2681 * For other VSI, the uplink_seid equals to uplink VSI's
2682 * uplink_seid since they share same VEB
2684 vsi->uplink_seid = uplink_vsi->uplink_seid;
2685 ctxt.pf_num = hw->pf_id;
2686 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
2687 ctxt.uplink_seid = vsi->uplink_seid;
2688 ctxt.connection_type = 0x1;
2689 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
2691 /* Configure switch ID */
2692 ctxt.info.valid_sections |=
2693 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
2694 ctxt.info.switch_id =
2695 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
2696 /* Configure port/vlan */
2697 ctxt.info.valid_sections |=
2698 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2699 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
2700 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
2701 I40E_DEFAULT_TCMAP);
2702 if (ret != I40E_SUCCESS) {
2703 PMD_DRV_LOG(ERR, "Failed to configure "
2704 "TC queue mapping\n");
2705 goto fail_msix_alloc;
2707 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
2708 ctxt.info.valid_sections |=
2709 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
2711 * Since VSI is not created yet, only configure parameter,
2712 * will add vsi below.
2716 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet\n");
2717 goto fail_msix_alloc;
2720 if (vsi->type != I40E_VSI_MAIN) {
2721 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
2723 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d\n",
2724 hw->aq.asq_last_status);
2725 goto fail_msix_alloc;
2727 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
2728 vsi->info.valid_sections = 0;
2729 vsi->seid = ctxt.seid;
2730 vsi->vsi_id = ctxt.vsi_number;
2731 vsi->sib_vsi_list.vsi = vsi;
2732 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
2733 &vsi->sib_vsi_list, list);
2736 /* MAC/VLAN configuration */
2737 ret = i40e_vsi_add_mac(vsi, &broadcast);
2738 if (ret != I40E_SUCCESS) {
2739 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter\n");
2740 goto fail_msix_alloc;
2743 /* Get VSI BW information */
2744 i40e_vsi_dump_bw_config(vsi);
2747 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
2749 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
2755 /* Configure vlan stripping on or off */
2757 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
2759 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2760 struct i40e_vsi_context ctxt;
2762 int ret = I40E_SUCCESS;
2764 /* Check if it has been already on or off */
2765 if (vsi->info.valid_sections &
2766 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
2768 if ((vsi->info.port_vlan_flags &
2769 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
2770 return 0; /* already on */
2772 if ((vsi->info.port_vlan_flags &
2773 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2774 I40E_AQ_VSI_PVLAN_EMOD_MASK)
2775 return 0; /* already off */
2780 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2782 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2783 vsi->info.valid_sections =
2784 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2785 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
2786 vsi->info.port_vlan_flags |= vlan_flags;
2787 ctxt.seid = vsi->seid;
2788 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2789 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2791 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping\n",
2792 on ? "enable" : "disable");
2798 i40e_dev_init_vlan(struct rte_eth_dev *dev)
2800 struct rte_eth_dev_data *data = dev->data;
2803 /* Apply vlan offload setting */
2804 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
2806 /* Apply double-vlan setting, not implemented yet */
2808 /* Apply pvid setting */
2809 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
2810 data->dev_conf.txmode.hw_vlan_insert_pvid);
2812 PMD_DRV_LOG(INFO, "Failed to update VSI params\n");
2818 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
2820 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2822 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
2826 i40e_update_flow_control(struct i40e_hw *hw)
2828 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
2829 struct i40e_link_status link_status;
2830 uint32_t rxfc = 0, txfc = 0, reg;
2834 memset(&link_status, 0, sizeof(link_status));
2835 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
2836 if (ret != I40E_SUCCESS) {
2837 PMD_DRV_LOG(ERR, "Failed to get link status information\n");
2838 goto write_reg; /* Disable flow control */
2841 an_info = hw->phy.link_info.an_info;
2842 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
2843 PMD_DRV_LOG(INFO, "Link auto negotiation not completed\n");
2844 ret = I40E_ERR_NOT_READY;
2845 goto write_reg; /* Disable flow control */
2848 * If link auto negotiation is enabled, flow control needs to
2849 * be configured according to it
2851 switch (an_info & I40E_LINK_PAUSE_RXTX) {
2852 case I40E_LINK_PAUSE_RXTX:
2855 hw->fc.current_mode = I40E_FC_FULL;
2857 case I40E_AQ_LINK_PAUSE_RX:
2859 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2861 case I40E_AQ_LINK_PAUSE_TX:
2863 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2866 hw->fc.current_mode = I40E_FC_NONE;
2871 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
2872 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
2873 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2874 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
2875 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
2876 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
2883 i40e_pf_setup(struct i40e_pf *pf)
2885 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2886 struct i40e_filter_control_settings settings;
2887 struct rte_eth_dev_data *dev_data = pf->dev_data;
2888 struct i40e_vsi *vsi;
2891 /* Clear all stats counters */
2892 pf->offset_loaded = FALSE;
2893 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
2894 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
2896 ret = i40e_pf_get_switch_config(pf);
2897 if (ret != I40E_SUCCESS) {
2898 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
2903 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
2905 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
2906 return I40E_ERR_NOT_READY;
2909 dev_data->nb_rx_queues = vsi->nb_qps;
2910 dev_data->nb_tx_queues = vsi->nb_qps;
2912 /* Configure filter control */
2913 memset(&settings, 0, sizeof(settings));
2914 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
2915 /* Enable ethtype and macvlan filters */
2916 settings.enable_ethtype = TRUE;
2917 settings.enable_macvlan = TRUE;
2918 ret = i40e_set_filter_control(hw, &settings);
2920 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2923 /* Update flow control according to the auto negotiation */
2924 i40e_update_flow_control(hw);
2926 return I40E_SUCCESS;
2930 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
2936 * Set or clear TX Queue Disable flags,
2937 * which is required by hardware.
2939 i40e_pre_tx_queue_cfg(hw, q_idx, on);
2940 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
2942 /* Wait until the request is finished */
2943 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2944 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2945 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2946 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
2947 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
2953 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
2954 return I40E_SUCCESS; /* already on, skip next steps */
2956 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
2957 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
2959 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2960 return I40E_SUCCESS; /* already off, skip next steps */
2961 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
2963 /* Write the register */
2964 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
2965 /* Check the result */
2966 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
2967 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
2968 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
2970 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2971 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
2974 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
2975 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
2979 /* Check if it is timeout */
2980 if (j >= I40E_CHK_Q_ENA_COUNT) {
2981 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]\n",
2982 (on ? "enable" : "disable"), q_idx);
2983 return I40E_ERR_TIMEOUT;
2986 return I40E_SUCCESS;
2989 /* Swith on or off the tx queues */
2991 i40e_vsi_switch_tx_queues(struct i40e_vsi *vsi, bool on)
2993 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
2994 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2995 struct i40e_tx_queue *txq;
2999 pf_q = vsi->base_queue;
3000 for (i = 0; i < dev_data->nb_tx_queues; i++, pf_q++) {
3001 txq = dev_data->tx_queues[i];
3003 continue; /* Queue not configured */
3004 ret = i40e_switch_tx_queue(hw, pf_q, on);
3005 if ( ret != I40E_SUCCESS)
3009 return I40E_SUCCESS;
3013 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3018 /* Wait until the request is finished */
3019 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3020 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3021 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3022 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3023 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3028 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3029 return I40E_SUCCESS; /* Already on, skip next steps */
3030 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3032 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3033 return I40E_SUCCESS; /* Already off, skip next steps */
3034 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3037 /* Write the register */
3038 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3039 /* Check the result */
3040 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3041 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3042 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3044 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3045 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3048 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3049 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3054 /* Check if it is timeout */
3055 if (j >= I40E_CHK_Q_ENA_COUNT) {
3056 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]\n",
3057 (on ? "enable" : "disable"), q_idx);
3058 return I40E_ERR_TIMEOUT;
3061 return I40E_SUCCESS;
3063 /* Switch on or off the rx queues */
3065 i40e_vsi_switch_rx_queues(struct i40e_vsi *vsi, bool on)
3067 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
3068 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3069 struct i40e_rx_queue *rxq;
3073 pf_q = vsi->base_queue;
3074 for (i = 0; i < dev_data->nb_rx_queues; i++, pf_q++) {
3075 rxq = dev_data->rx_queues[i];
3077 continue; /* Queue not configured */
3078 ret = i40e_switch_rx_queue(hw, pf_q, on);
3079 if ( ret != I40E_SUCCESS)
3083 return I40E_SUCCESS;
3086 /* Switch on or off all the rx/tx queues */
3088 i40e_vsi_switch_queues(struct i40e_vsi *vsi, bool on)
3093 /* enable rx queues before enabling tx queues */
3094 ret = i40e_vsi_switch_rx_queues(vsi, on);
3096 PMD_DRV_LOG(ERR, "Failed to switch rx queues\n");
3099 ret = i40e_vsi_switch_tx_queues(vsi, on);
3101 /* Stop tx queues before stopping rx queues */
3102 ret = i40e_vsi_switch_tx_queues(vsi, on);
3104 PMD_DRV_LOG(ERR, "Failed to switch tx queues\n");
3107 ret = i40e_vsi_switch_rx_queues(vsi, on);
3113 /* Initialize VSI for TX */
3115 i40e_vsi_tx_init(struct i40e_vsi *vsi)
3117 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3118 struct rte_eth_dev_data *data = pf->dev_data;
3120 uint32_t ret = I40E_SUCCESS;
3122 for (i = 0; i < data->nb_tx_queues; i++) {
3123 ret = i40e_tx_queue_init(data->tx_queues[i]);
3124 if (ret != I40E_SUCCESS)
3131 /* Initialize VSI for RX */
3133 i40e_vsi_rx_init(struct i40e_vsi *vsi)
3135 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3136 struct rte_eth_dev_data *data = pf->dev_data;
3137 int ret = I40E_SUCCESS;
3140 i40e_pf_config_mq_rx(pf);
3141 for (i = 0; i < data->nb_rx_queues; i++) {
3142 ret = i40e_rx_queue_init(data->rx_queues[i]);
3143 if (ret != I40E_SUCCESS) {
3144 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3145 "initialization\n");
3153 /* Initialize VSI */
3155 i40e_vsi_init(struct i40e_vsi *vsi)
3159 err = i40e_vsi_tx_init(vsi);
3161 PMD_DRV_LOG(ERR, "Failed to do vsi TX initialization\n");
3164 err = i40e_vsi_rx_init(vsi);
3166 PMD_DRV_LOG(ERR, "Failed to do vsi RX initialization\n");
3174 i40e_stat_update_32(struct i40e_hw *hw,
3182 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3186 if (new_data >= *offset)
3187 *stat = (uint64_t)(new_data - *offset);
3189 *stat = (uint64_t)((new_data +
3190 ((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);
3194 i40e_stat_update_48(struct i40e_hw *hw,
3203 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3204 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3205 I40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;
3210 if (new_data >= *offset)
3211 *stat = new_data - *offset;
3213 *stat = (uint64_t)((new_data +
3214 ((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);
3216 *stat &= I40E_48_BIT_MASK;
3221 i40e_pf_disable_irq0(struct i40e_hw *hw)
3223 /* Disable all interrupt types */
3224 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3225 I40E_WRITE_FLUSH(hw);
3230 i40e_pf_enable_irq0(struct i40e_hw *hw)
3232 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3233 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3234 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3235 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3236 I40E_WRITE_FLUSH(hw);
3240 i40e_pf_config_irq0(struct i40e_hw *hw)
3244 /* read pending request and disable first */
3245 i40e_pf_disable_irq0(hw);
3247 * Enable all interrupt error options to detect possible errors,
3248 * other informative int are ignored
3250 enable = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3251 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3252 I40E_PFINT_ICR0_ENA_GRST_MASK |
3253 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3254 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK |
3255 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3256 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3257 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3259 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3260 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3261 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3263 /* Link no queues with irq0 */
3264 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3265 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3269 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3271 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3275 uint32_t index, offset, val;
3280 * Try to find which VF trigger a reset, use absolute VF id to access
3281 * since the reg is global register.
3283 for (i = 0; i < pf->vf_num; i++) {
3284 abs_vf_id = hw->func_caps.vf_base_id + i;
3285 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3286 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3287 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3288 /* VFR event occured */
3289 if (val & (0x1 << offset)) {
3292 /* Clear the event first */
3293 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3295 PMD_DRV_LOG(INFO, "VF %u reset occured\n", abs_vf_id);
3297 * Only notify a VF reset event occured,
3298 * don't trigger another SW reset
3300 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3301 if (ret != I40E_SUCCESS)
3302 PMD_DRV_LOG(ERR, "Failed to do VF reset\n");
3308 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3310 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3311 struct i40e_arq_event_info info;
3312 uint16_t pending, opcode;
3315 info.msg_size = I40E_AQ_BUF_SZ;
3316 info.msg_buf = rte_zmalloc("msg_buffer", I40E_AQ_BUF_SZ, 0);
3317 if (!info.msg_buf) {
3318 PMD_DRV_LOG(ERR, "Failed to allocate mem\n");
3324 ret = i40e_clean_arq_element(hw, &info, &pending);
3326 if (ret != I40E_SUCCESS) {
3327 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3328 "aq_err: %u\n", hw->aq.asq_last_status);
3331 opcode = rte_le_to_cpu_16(info.desc.opcode);
3334 case i40e_aqc_opc_send_msg_to_pf:
3335 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3336 i40e_pf_host_handle_vf_msg(dev,
3337 rte_le_to_cpu_16(info.desc.retval),
3338 rte_le_to_cpu_32(info.desc.cookie_high),
3339 rte_le_to_cpu_32(info.desc.cookie_low),
3344 PMD_DRV_LOG(ERR, "Request %u is not supported yet\n",
3348 /* Reset the buffer after processing one */
3349 info.msg_size = I40E_AQ_BUF_SZ;
3351 rte_free(info.msg_buf);
3355 * Interrupt handler triggered by NIC for handling
3356 * specific interrupt.
3359 * Pointer to interrupt handle.
3361 * The address of parameter (struct rte_eth_dev *) regsitered before.
3367 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3370 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3371 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3372 uint32_t cause, enable;
3374 i40e_pf_disable_irq0(hw);
3376 cause = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3377 enable = I40E_READ_REG(hw, I40E_PFINT_ICR0_ENA);
3379 /* Shared IRQ case, return */
3380 if (!(cause & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3381 PMD_DRV_LOG(INFO, "Port%d INT0:share IRQ case, "
3382 "no INT event to process\n", hw->pf_id);
3386 if (cause & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
3387 PMD_DRV_LOG(INFO, "INT:Link status changed\n");
3388 i40e_dev_link_update(dev, 0);
3391 if (cause & I40E_PFINT_ICR0_ECC_ERR_MASK)
3392 PMD_DRV_LOG(INFO, "INT:Unrecoverable ECC Error\n");
3394 if (cause & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3395 PMD_DRV_LOG(INFO, "INT:Malicious programming detected\n");
3397 if (cause & I40E_PFINT_ICR0_GRST_MASK)
3398 PMD_DRV_LOG(INFO, "INT:Global Resets Requested\n");
3400 if (cause & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3401 PMD_DRV_LOG(INFO, "INT:PCI EXCEPTION occured\n");
3403 if (cause & I40E_PFINT_ICR0_HMC_ERR_MASK)
3404 PMD_DRV_LOG(INFO, "INT:HMC error occured\n");
3406 /* Add processing func to deal with VF reset vent */
3407 if (cause & I40E_PFINT_ICR0_VFLR_MASK) {
3408 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3409 i40e_dev_handle_vfr_event(dev);
3411 /* Find admin queue event */
3412 if (cause & I40E_PFINT_ICR0_ADMINQ_MASK) {
3413 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3414 i40e_dev_handle_aq_msg(dev);
3418 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, enable);
3419 /* Re-enable interrupt from device side */
3420 i40e_pf_enable_irq0(hw);
3421 /* Re-enable interrupt from host side */
3422 rte_intr_enable(&(dev->pci_dev->intr_handle));
3426 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
3427 struct i40e_macvlan_filter *filter,
3430 int ele_num, ele_buff_size;
3431 int num, actual_num, i;
3432 int ret = I40E_SUCCESS;
3433 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3434 struct i40e_aqc_add_macvlan_element_data *req_list;
3436 if (filter == NULL || total == 0)
3437 return I40E_ERR_PARAM;
3438 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3439 ele_buff_size = hw->aq.asq_buf_size;
3441 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
3442 if (req_list == NULL) {
3443 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3444 return I40E_ERR_NO_MEMORY;
3449 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3450 memset(req_list, 0, ele_buff_size);
3452 for (i = 0; i < actual_num; i++) {
3453 (void)rte_memcpy(req_list[i].mac_addr,
3454 &filter[num + i].macaddr, ETH_ADDR_LEN);
3455 req_list[i].vlan_tag =
3456 rte_cpu_to_le_16(filter[num + i].vlan_id);
3457 req_list[i].flags = rte_cpu_to_le_16(\
3458 I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
3459 req_list[i].queue_number = 0;
3462 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
3464 if (ret != I40E_SUCCESS) {
3465 PMD_DRV_LOG(ERR, "Failed to add macvlan filter\n");
3469 } while (num < total);
3477 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
3478 struct i40e_macvlan_filter *filter,
3481 int ele_num, ele_buff_size;
3482 int num, actual_num, i;
3483 int ret = I40E_SUCCESS;
3484 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3485 struct i40e_aqc_remove_macvlan_element_data *req_list;
3487 if (filter == NULL || total == 0)
3488 return I40E_ERR_PARAM;
3490 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
3491 ele_buff_size = hw->aq.asq_buf_size;
3493 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
3494 if (req_list == NULL) {
3495 PMD_DRV_LOG(ERR, "Fail to allocate memory\n");
3496 return I40E_ERR_NO_MEMORY;
3501 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
3502 memset(req_list, 0, ele_buff_size);
3504 for (i = 0; i < actual_num; i++) {
3505 (void)rte_memcpy(req_list[i].mac_addr,
3506 &filter[num + i].macaddr, ETH_ADDR_LEN);
3507 req_list[i].vlan_tag =
3508 rte_cpu_to_le_16(filter[num + i].vlan_id);
3509 req_list[i].flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
3512 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
3514 if (ret != I40E_SUCCESS) {
3515 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter\n");
3519 } while (num < total);
3526 /* Find out specific MAC filter */
3527 static struct i40e_mac_filter *
3528 i40e_find_mac_filter(struct i40e_vsi *vsi,
3529 struct ether_addr *macaddr)
3531 struct i40e_mac_filter *f;
3533 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3534 if (is_same_ether_addr(macaddr, &(f->macaddr)))
3542 i40e_find_vlan_filter(struct i40e_vsi *vsi,
3545 uint32_t vid_idx, vid_bit;
3547 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3548 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3550 if (vsi->vfta[vid_idx] & vid_bit)
3557 i40e_set_vlan_filter(struct i40e_vsi *vsi,
3558 uint16_t vlan_id, bool on)
3560 uint32_t vid_idx, vid_bit;
3562 #define UINT32_BIT_MASK 0x1F
3563 #define VALID_VLAN_BIT_MASK 0xFFF
3564 /* VFTA is 32-bits size array, each element contains 32 vlan bits, Find the
3565 * element first, then find the bits it belongs to
3567 vid_idx = (uint32_t) ((vlan_id & VALID_VLAN_BIT_MASK) >>
3569 vid_bit = (uint32_t) (1 << (vlan_id & UINT32_BIT_MASK));
3572 vsi->vfta[vid_idx] |= vid_bit;
3574 vsi->vfta[vid_idx] &= ~vid_bit;
3578 * Find all vlan options for specific mac addr,
3579 * return with actual vlan found.
3582 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
3583 struct i40e_macvlan_filter *mv_f,
3584 int num, struct ether_addr *addr)
3590 * Not to use i40e_find_vlan_filter to decrease the loop time,
3591 * although the code looks complex.
3593 if (num < vsi->vlan_num)
3594 return I40E_ERR_PARAM;
3597 for (j = 0; j < I40E_VFTA_SIZE; j++) {
3599 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
3600 if (vsi->vfta[j] & (1 << k)) {
3602 PMD_DRV_LOG(ERR, "vlan number "
3604 return I40E_ERR_PARAM;
3606 (void)rte_memcpy(&mv_f[i].macaddr,
3607 addr, ETH_ADDR_LEN);
3609 j * I40E_UINT32_BIT_SIZE + k;
3615 return I40E_SUCCESS;
3619 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
3620 struct i40e_macvlan_filter *mv_f,
3625 struct i40e_mac_filter *f;
3627 if (num < vsi->mac_num)
3628 return I40E_ERR_PARAM;
3630 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3632 PMD_DRV_LOG(ERR, "buffer number not match\n");
3633 return I40E_ERR_PARAM;
3635 (void)rte_memcpy(&mv_f[i].macaddr, &f->macaddr, ETH_ADDR_LEN);
3636 mv_f[i].vlan_id = vlan;
3640 return I40E_SUCCESS;
3644 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
3647 struct i40e_mac_filter *f;
3648 struct i40e_macvlan_filter *mv_f;
3649 int ret = I40E_SUCCESS;
3651 if (vsi == NULL || vsi->mac_num == 0)
3652 return I40E_ERR_PARAM;
3654 /* Case that no vlan is set */
3655 if (vsi->vlan_num == 0)
3658 num = vsi->mac_num * vsi->vlan_num;
3660 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
3662 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3663 return I40E_ERR_NO_MEMORY;
3667 if (vsi->vlan_num == 0) {
3668 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3669 (void)rte_memcpy(&mv_f[i].macaddr,
3670 &f->macaddr, ETH_ADDR_LEN);
3671 mv_f[i].vlan_id = 0;
3675 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3676 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
3677 vsi->vlan_num, &f->macaddr);
3678 if (ret != I40E_SUCCESS)
3684 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
3692 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3694 struct i40e_macvlan_filter *mv_f;
3696 int ret = I40E_SUCCESS;
3698 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
3699 return I40E_ERR_PARAM;
3701 /* If it's already set, just return */
3702 if (i40e_find_vlan_filter(vsi,vlan))
3703 return I40E_SUCCESS;
3705 mac_num = vsi->mac_num;
3708 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3709 return I40E_ERR_PARAM;
3712 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3715 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3716 return I40E_ERR_NO_MEMORY;
3719 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3721 if (ret != I40E_SUCCESS)
3724 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3726 if (ret != I40E_SUCCESS)
3729 i40e_set_vlan_filter(vsi, vlan, 1);
3739 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
3741 struct i40e_macvlan_filter *mv_f;
3743 int ret = I40E_SUCCESS;
3746 * Vlan 0 is the generic filter for untagged packets
3747 * and can't be removed.
3749 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
3750 return I40E_ERR_PARAM;
3752 /* If can't find it, just return */
3753 if (!i40e_find_vlan_filter(vsi, vlan))
3754 return I40E_ERR_PARAM;
3756 mac_num = vsi->mac_num;
3759 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr\n");
3760 return I40E_ERR_PARAM;
3763 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
3766 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3767 return I40E_ERR_NO_MEMORY;
3770 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
3772 if (ret != I40E_SUCCESS)
3775 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
3777 if (ret != I40E_SUCCESS)
3780 /* This is last vlan to remove, replace all mac filter with vlan 0 */
3781 if (vsi->vlan_num == 1) {
3782 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
3783 if (ret != I40E_SUCCESS)
3786 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
3787 if (ret != I40E_SUCCESS)
3791 i40e_set_vlan_filter(vsi, vlan, 0);
3801 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3803 struct i40e_mac_filter *f;
3804 struct i40e_macvlan_filter *mv_f;
3806 int ret = I40E_SUCCESS;
3808 /* If it's add and we've config it, return */
3809 f = i40e_find_mac_filter(vsi, addr);
3811 return I40E_SUCCESS;
3814 * If vlan_num is 0, that's the first time to add mac,
3815 * set mask for vlan_id 0.
3817 if (vsi->vlan_num == 0) {
3818 i40e_set_vlan_filter(vsi, 0, 1);
3822 vlan_num = vsi->vlan_num;
3824 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3826 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3827 return I40E_ERR_NO_MEMORY;
3830 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3831 if (ret != I40E_SUCCESS)
3834 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
3835 if (ret != I40E_SUCCESS)
3838 /* Add the mac addr into mac list */
3839 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3841 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3842 ret = I40E_ERR_NO_MEMORY;
3845 (void)rte_memcpy(&f->macaddr, addr, ETH_ADDR_LEN);
3846 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3857 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
3859 struct i40e_mac_filter *f;
3860 struct i40e_macvlan_filter *mv_f;
3862 int ret = I40E_SUCCESS;
3864 /* Can't find it, return an error */
3865 f = i40e_find_mac_filter(vsi, addr);
3867 return I40E_ERR_PARAM;
3869 vlan_num = vsi->vlan_num;
3870 if (vlan_num == 0) {
3871 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
3872 return I40E_ERR_PARAM;
3874 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
3876 PMD_DRV_LOG(ERR, "failed to allocate memory\n");
3877 return I40E_ERR_NO_MEMORY;
3880 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
3881 if (ret != I40E_SUCCESS)
3884 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
3885 if (ret != I40E_SUCCESS)
3888 /* Remove the mac addr into mac list */
3889 TAILQ_REMOVE(&vsi->mac_list, f, next);
3899 /* Configure hash enable flags for RSS */
3901 i40e_config_hena(uint64_t flags)
3908 if (flags & ETH_RSS_NONF_IPV4_UDP)
3909 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3910 if (flags & ETH_RSS_NONF_IPV4_TCP)
3911 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3912 if (flags & ETH_RSS_NONF_IPV4_SCTP)
3913 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3914 if (flags & ETH_RSS_NONF_IPV4_OTHER)
3915 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3916 if (flags & ETH_RSS_FRAG_IPV4)
3917 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
3918 if (flags & ETH_RSS_NONF_IPV6_UDP)
3919 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3920 if (flags & ETH_RSS_NONF_IPV6_TCP)
3921 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3922 if (flags & ETH_RSS_NONF_IPV6_SCTP)
3923 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3924 if (flags & ETH_RSS_NONF_IPV6_OTHER)
3925 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3926 if (flags & ETH_RSS_FRAG_IPV6)
3927 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
3928 if (flags & ETH_RSS_L2_PAYLOAD)
3929 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
3934 /* Parse the hash enable flags */
3936 i40e_parse_hena(uint64_t flags)
3938 uint64_t rss_hf = 0;
3943 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
3944 rss_hf |= ETH_RSS_NONF_IPV4_UDP;
3945 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
3946 rss_hf |= ETH_RSS_NONF_IPV4_TCP;
3947 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
3948 rss_hf |= ETH_RSS_NONF_IPV4_SCTP;
3949 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
3950 rss_hf |= ETH_RSS_NONF_IPV4_OTHER;
3951 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
3952 rss_hf |= ETH_RSS_FRAG_IPV4;
3953 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
3954 rss_hf |= ETH_RSS_NONF_IPV6_UDP;
3955 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
3956 rss_hf |= ETH_RSS_NONF_IPV6_TCP;
3957 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
3958 rss_hf |= ETH_RSS_NONF_IPV6_SCTP;
3959 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
3960 rss_hf |= ETH_RSS_NONF_IPV6_OTHER;
3961 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
3962 rss_hf |= ETH_RSS_FRAG_IPV6;
3963 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
3964 rss_hf |= ETH_RSS_L2_PAYLOAD;
3971 i40e_pf_disable_rss(struct i40e_pf *pf)
3973 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3976 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
3977 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
3978 hena &= ~I40E_RSS_HENA_ALL;
3979 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
3980 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
3981 I40E_WRITE_FLUSH(hw);
3985 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
3988 uint8_t hash_key_len;
3993 hash_key = (uint32_t *)(rss_conf->rss_key);
3994 hash_key_len = rss_conf->rss_key_len;
3995 if (hash_key != NULL && hash_key_len >=
3996 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
3997 /* Fill in RSS hash key */
3998 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
3999 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4002 rss_hf = rss_conf->rss_hf;
4003 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4004 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4005 hena &= ~I40E_RSS_HENA_ALL;
4006 hena |= i40e_config_hena(rss_hf);
4007 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4008 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4009 I40E_WRITE_FLUSH(hw);
4015 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4016 struct rte_eth_rss_conf *rss_conf)
4018 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4022 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4023 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4024 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4025 if (rss_hf != 0) /* Enable RSS */
4027 return 0; /* Nothing to do */
4030 if (rss_hf == 0) /* Disable RSS */
4033 return i40e_hw_rss_hash_set(hw, rss_conf);
4037 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4038 struct rte_eth_rss_conf *rss_conf)
4040 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4045 if (hash_key != NULL) {
4046 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4047 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4048 rss_conf->rss_key_len = i * sizeof(uint32_t);
4050 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4051 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4052 rss_conf->rss_hf = i40e_parse_hena(hena);
4059 i40e_pf_config_rss(struct i40e_pf *pf)
4061 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4062 struct rte_eth_rss_conf rss_conf;
4063 uint32_t i, lut = 0;
4064 uint16_t j, num = i40e_prev_power_of_2(pf->dev_data->nb_rx_queues);
4066 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
4069 lut = (lut << 8) | (j & ((0x1 <<
4070 hw->func_caps.rss_table_entry_width) - 1));
4072 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
4075 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
4076 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
4077 i40e_pf_disable_rss(pf);
4080 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
4081 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4082 /* Calculate the default hash key */
4083 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4084 rss_key_default[i] = (uint32_t)rte_rand();
4085 rss_conf.rss_key = (uint8_t *)rss_key_default;
4086 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
4090 return i40e_hw_rss_hash_set(hw, &rss_conf);
4094 i40e_pf_config_mq_rx(struct i40e_pf *pf)
4096 if (!pf->dev_data->sriov.active) {
4097 switch (pf->dev_data->dev_conf.rxmode.mq_mode) {
4099 i40e_pf_config_rss(pf);
4102 i40e_pf_disable_rss(pf);