4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <sys/queue.h>
45 #include <rte_string_fns.h>
46 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_ether.h>
50 #include <rte_ethdev.h>
55 #include "i40e_logs.h"
56 #include "i40e/i40e_prototype.h"
57 #include "i40e/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
61 #define I40E_MIN_RING_DESC 64
62 #define I40E_MAX_RING_DESC 4096
63 #define I40E_ALIGN 128
64 #define DEFAULT_TX_RS_THRESH 32
65 #define DEFAULT_TX_FREE_THRESH 32
66 #define I40E_MAX_PKT_TYPE 256
68 #define I40E_VLAN_TAG_SIZE 4
69 #define I40E_TX_MAX_BURST 32
71 #define I40E_DMA_MEM_ALIGN 4096
73 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
74 ETH_TXQ_FLAGS_NOOFFLOADS)
76 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
78 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
79 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
81 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
82 ((uint64_t)((mb)->buf_physaddr + \
83 (uint64_t)((char *)((mb)->pkt.data) - \
84 (char *)(mb)->buf_addr)))
86 static const struct rte_memzone *
87 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
88 const char *ring_name,
92 static void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
93 static void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
94 static void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
95 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
96 struct rte_mbuf **tx_pkts,
99 /* Translate the rx descriptor status to pkt flags */
100 static inline uint16_t
101 i40e_rxd_status_to_pkt_flags(uint64_t qword)
105 /* Check if VLAN packet */
106 flags = (uint16_t)(qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
107 PKT_RX_VLAN_PKT : 0);
109 /* Check if RSS_HASH */
110 flags |= (uint16_t)((((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
111 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
112 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0);
117 static inline uint16_t
118 i40e_rxd_error_to_pkt_flags(uint64_t qword)
121 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
123 #define I40E_RX_ERR_BITS 0x3f
124 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
126 /* If RXE bit set, all other status bits are meaningless */
127 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
128 flags |= PKT_RX_MAC_ERR;
132 /* If RECIPE bit set, all other status indications should be ignored */
133 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
134 flags |= PKT_RX_RECIP_ERR;
137 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
138 flags |= PKT_RX_HBUF_OVERFLOW;
139 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
140 flags |= PKT_RX_IP_CKSUM_BAD;
141 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
142 flags |= PKT_RX_L4_CKSUM_BAD;
143 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
144 flags |= PKT_RX_EIP_CKSUM_BAD;
145 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
146 flags |= PKT_RX_OVERSIZE;
151 /* Translate pkt types to pkt flags */
152 static inline uint16_t
153 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
155 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
156 I40E_RXD_QW1_PTYPE_SHIFT);
157 static const uint16_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
180 PKT_RX_IPV4_HDR, /* PTYPE 22 */
181 PKT_RX_IPV4_HDR, /* PTYPE 23 */
182 PKT_RX_IPV4_HDR, /* PTYPE 24 */
184 PKT_RX_IPV4_HDR, /* PTYPE 26 */
185 PKT_RX_IPV4_HDR, /* PTYPE 27 */
186 PKT_RX_IPV4_HDR, /* PTYPE 28 */
187 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
188 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
189 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
191 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
193 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
195 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
199 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
200 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
203 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
206 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
208 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
210 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
214 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
215 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 59 */
218 PKT_RX_IPV4_HDR_EXT, /* PTYPE 60 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 61 */
221 PKT_RX_IPV4_HDR_EXT, /* PTYPE 63 */
222 PKT_RX_IPV4_HDR_EXT, /* PTYPE 64 */
223 PKT_RX_IPV4_HDR_EXT, /* PTYPE 65 */
224 PKT_RX_IPV4_HDR_EXT, /* PTYPE 66 */
225 PKT_RX_IPV4_HDR_EXT, /* PTYPE 67 */
226 PKT_RX_IPV4_HDR_EXT, /* PTYPE 68 */
228 PKT_RX_IPV4_HDR_EXT, /* PTYPE 70 */
229 PKT_RX_IPV4_HDR_EXT, /* PTYPE 71 */
230 PKT_RX_IPV4_HDR_EXT, /* PTYPE 72 */
231 PKT_RX_IPV4_HDR_EXT, /* PTYPE 73 */
232 PKT_RX_IPV4_HDR_EXT, /* PTYPE 74 */
233 PKT_RX_IPV4_HDR_EXT, /* PTYPE 75 */
234 PKT_RX_IPV4_HDR_EXT, /* PTYPE 76 */
236 PKT_RX_IPV4_HDR_EXT, /* PTYPE 78 */
237 PKT_RX_IPV4_HDR_EXT, /* PTYPE 79 */
238 PKT_RX_IPV4_HDR_EXT, /* PTYPE 80 */
239 PKT_RX_IPV4_HDR_EXT, /* PTYPE 81 */
240 PKT_RX_IPV4_HDR_EXT, /* PTYPE 82 */
241 PKT_RX_IPV4_HDR_EXT, /* PTYPE 83 */
243 PKT_RX_IPV4_HDR_EXT, /* PTYPE 85 */
244 PKT_RX_IPV4_HDR_EXT, /* PTYPE 86 */
245 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
246 PKT_RX_IPV6_HDR, /* PTYPE 88 */
247 PKT_RX_IPV6_HDR, /* PTYPE 89 */
248 PKT_RX_IPV6_HDR, /* PTYPE 90 */
250 PKT_RX_IPV6_HDR, /* PTYPE 92 */
251 PKT_RX_IPV6_HDR, /* PTYPE 93 */
252 PKT_RX_IPV6_HDR, /* PTYPE 94 */
253 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
254 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
255 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
257 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
259 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
261 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
265 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
266 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
269 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
272 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
274 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
276 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
280 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
281 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 125 */
284 PKT_RX_IPV6_HDR_EXT, /* PTYPE 126 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 127 */
287 PKT_RX_IPV6_HDR_EXT, /* PTYPE 129 */
288 PKT_RX_IPV6_HDR_EXT, /* PTYPE 130 */
289 PKT_RX_IPV6_HDR_EXT, /* PTYPE 131 */
290 PKT_RX_IPV6_HDR_EXT, /* PTYPE 132 */
291 PKT_RX_IPV6_HDR_EXT, /* PTYPE 133 */
292 PKT_RX_IPV6_HDR_EXT, /* PTYPE 134 */
294 PKT_RX_IPV6_HDR_EXT, /* PTYPE 136 */
295 PKT_RX_IPV6_HDR_EXT, /* PTYPE 137 */
296 PKT_RX_IPV6_HDR_EXT, /* PTYPE 138 */
297 PKT_RX_IPV6_HDR_EXT, /* PTYPE 139 */
298 PKT_RX_IPV6_HDR_EXT, /* PTYPE 140 */
299 PKT_RX_IPV6_HDR_EXT, /* PTYPE 141 */
300 PKT_RX_IPV6_HDR_EXT, /* PTYPE 142 */
302 PKT_RX_IPV6_HDR_EXT, /* PTYPE 144 */
303 PKT_RX_IPV6_HDR_EXT, /* PTYPE 145 */
304 PKT_RX_IPV6_HDR_EXT, /* PTYPE 146 */
305 PKT_RX_IPV6_HDR_EXT, /* PTYPE 147 */
306 PKT_RX_IPV6_HDR_EXT, /* PTYPE 148 */
307 PKT_RX_IPV6_HDR_EXT, /* PTYPE 149 */
309 PKT_RX_IPV6_HDR_EXT, /* PTYPE 151 */
310 PKT_RX_IPV6_HDR_EXT, /* PTYPE 152 */
311 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
416 return ip_ptype_map[ptype];
420 i40e_txd_enable_checksum(uint32_t ol_flags,
427 PMD_DRV_LOG(DEBUG, "L2 length set to 0\n");
430 *td_offset |= (l2_len >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
433 PMD_DRV_LOG(DEBUG, "L3 length set to 0\n");
437 /* Enable L3 checksum offloads */
438 if (ol_flags & PKT_TX_IPV4_CSUM) {
439 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
440 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
441 } else if (ol_flags & PKT_TX_IPV4) {
442 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
443 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
444 } else if (ol_flags & PKT_TX_IPV6) {
445 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
446 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
449 /* Enable L4 checksum offloads */
450 switch (ol_flags & PKT_TX_L4_MASK) {
451 case PKT_TX_TCP_CKSUM:
452 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
453 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
454 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
456 case PKT_TX_SCTP_CKSUM:
457 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
458 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
459 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
461 case PKT_TX_UDP_CKSUM:
462 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
463 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
464 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
471 static inline struct rte_mbuf *
472 rte_rxmbuf_alloc(struct rte_mempool *mp)
476 m = __rte_mbuf_raw_alloc(mp);
477 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
482 /* Construct the tx flags */
483 static inline uint64_t
484 i40e_build_ctob(uint32_t td_cmd,
489 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
490 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
491 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
492 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
493 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
497 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
499 struct i40e_tx_entry *sw_ring = txq->sw_ring;
500 volatile struct i40e_tx_desc *txd = txq->tx_ring;
501 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
502 uint16_t nb_tx_desc = txq->nb_tx_desc;
503 uint16_t desc_to_clean_to;
504 uint16_t nb_tx_to_clean;
506 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
507 if (desc_to_clean_to >= nb_tx_desc)
508 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
510 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
511 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
512 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
513 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
514 "(port=%d queue=%d)", desc_to_clean_to,
515 txq->port_id, txq->queue_id);
519 if (last_desc_cleaned > desc_to_clean_to)
520 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
523 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
526 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
528 txq->last_desc_cleaned = desc_to_clean_to;
529 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
535 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
536 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
538 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
543 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
544 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST))
546 else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc))
548 else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)
550 else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
551 RTE_PMD_I40E_RX_MAX_BURST)))
560 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
561 #define I40E_LOOK_AHEAD 8
562 #if (I40E_LOOK_AHEAD != 8)
563 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
566 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
568 volatile union i40e_rx_desc *rxdp;
569 struct i40e_rx_entry *rxep;
574 int32_t s[I40E_LOOK_AHEAD], nb_dd;
575 int32_t i, j, nb_rx = 0;
578 rxdp = &rxq->rx_ring[rxq->rx_tail];
579 rxep = &rxq->sw_ring[rxq->rx_tail];
581 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
582 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
583 I40E_RXD_QW1_STATUS_SHIFT;
585 /* Make sure there is at least 1 packet to receive */
586 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
590 * Scan LOOK_AHEAD descriptors at a time to determine which
591 * descriptors reference packets that are ready to be received.
593 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
594 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
595 /* Read desc statuses backwards to avoid race condition */
596 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
597 qword1 = rte_le_to_cpu_64(\
598 rxdp[j].wb.qword1.status_error_len);
599 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
600 I40E_RXD_QW1_STATUS_SHIFT;
603 /* Compute how many status bits were set */
604 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
605 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
609 /* Translate descriptor info to mbuf parameters */
610 for (j = 0; j < nb_dd; j++) {
612 qword1 = rte_le_to_cpu_64(\
613 rxdp[j].wb.qword1.status_error_len);
614 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
615 I40E_RXD_QW1_STATUS_SHIFT;
616 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
617 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
618 mb->pkt.data_len = pkt_len;
619 mb->pkt.pkt_len = pkt_len;
620 mb->pkt.vlan_macip.f.vlan_tci = rx_status &
621 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
623 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
624 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
625 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
626 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
627 mb->ol_flags = pkt_flags;
628 if (pkt_flags & PKT_RX_RSS_HASH)
629 mb->pkt.hash.rss = rte_le_to_cpu_32(\
630 rxdp->wb.qword0.hi_dword.rss);
633 for (j = 0; j < I40E_LOOK_AHEAD; j++)
634 rxq->rx_stage[i + j] = rxep[j].mbuf;
636 if (nb_dd != I40E_LOOK_AHEAD)
640 /* Clear software ring entries */
641 for (i = 0; i < nb_rx; i++)
642 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
647 static inline uint16_t
648 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
649 struct rte_mbuf **rx_pkts,
653 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
655 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
657 for (i = 0; i < nb_pkts; i++)
658 rx_pkts[i] = stage[i];
660 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
661 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
667 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
669 volatile union i40e_rx_desc *rxdp;
670 struct i40e_rx_entry *rxep;
672 uint16_t alloc_idx, i;
676 /* Allocate buffers in bulk */
677 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
678 (rxq->rx_free_thresh - 1));
679 rxep = &(rxq->sw_ring[alloc_idx]);
680 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
681 rxq->rx_free_thresh);
682 if (unlikely(diag != 0)) {
683 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk\n");
687 rxdp = &rxq->rx_ring[alloc_idx];
688 for (i = 0; i < rxq->rx_free_thresh; i++) {
690 rte_mbuf_refcnt_set(mb, 1);
691 mb->type = RTE_MBUF_PKT;
693 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
695 mb->pkt.in_port = rxq->port_id;
696 dma_addr = rte_cpu_to_le_64(\
697 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
698 rxdp[i].read.hdr_addr = dma_addr;
699 rxdp[i].read.pkt_addr = dma_addr;
702 /* Update rx tail regsiter */
704 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
706 rxq->rx_free_trigger =
707 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
708 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
709 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
714 static inline uint16_t
715 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
717 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
723 if (rxq->rx_nb_avail)
724 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
726 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
727 rxq->rx_next_avail = 0;
728 rxq->rx_nb_avail = nb_rx;
729 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
731 if (rxq->rx_tail > rxq->rx_free_trigger) {
732 if (i40e_rx_alloc_bufs(rxq) != 0) {
735 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
736 "port_id=%u, queue_id=%u\n",
737 rxq->port_id, rxq->queue_id);
738 rxq->rx_nb_avail = 0;
739 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
740 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
741 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
747 if (rxq->rx_tail >= rxq->nb_rx_desc)
750 if (rxq->rx_nb_avail)
751 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
757 i40e_recv_pkts_bulk_alloc(void *rx_queue,
758 struct rte_mbuf **rx_pkts,
761 uint16_t nb_rx = 0, n, count;
763 if (unlikely(nb_pkts == 0))
766 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
767 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
770 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
771 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
772 nb_rx = (uint16_t)(nb_rx + count);
773 nb_pkts = (uint16_t)(nb_pkts - count);
780 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
783 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
785 struct i40e_rx_queue *rxq;
786 volatile union i40e_rx_desc *rx_ring;
787 volatile union i40e_rx_desc *rxdp;
788 union i40e_rx_desc rxd;
789 struct i40e_rx_entry *sw_ring;
790 struct i40e_rx_entry *rxe;
791 struct rte_mbuf *rxm;
792 struct rte_mbuf *nmb;
796 uint16_t rx_packet_len;
797 uint16_t rx_id, nb_hold;
804 rx_id = rxq->rx_tail;
805 rx_ring = rxq->rx_ring;
806 sw_ring = rxq->sw_ring;
808 while (nb_rx < nb_pkts) {
809 rxdp = &rx_ring[rx_id];
810 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
811 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
812 >> I40E_RXD_QW1_STATUS_SHIFT;
813 /* Check the DD bit first */
814 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
817 nmb = rte_rxmbuf_alloc(rxq->mp);
823 rxe = &sw_ring[rx_id];
825 if (unlikely(rx_id == rxq->nb_rx_desc))
828 /* Prefetch next mbuf */
829 rte_prefetch0(sw_ring[rx_id].mbuf);
832 * When next RX descriptor is on a cache line boundary,
833 * prefetch the next 4 RX descriptors and next 8 pointers
836 if ((rx_id & 0x3) == 0) {
837 rte_prefetch0(&rx_ring[rx_id]);
838 rte_prefetch0(&sw_ring[rx_id]);
843 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
844 rxdp->read.hdr_addr = dma_addr;
845 rxdp->read.pkt_addr = dma_addr;
847 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
848 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
850 rxm->pkt.data = (char *)rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
851 rte_prefetch0(rxm->pkt.data);
852 rxm->pkt.nb_segs = 1;
853 rxm->pkt.next = NULL;
854 rxm->pkt.pkt_len = rx_packet_len;
855 rxm->pkt.data_len = rx_packet_len;
856 rxm->pkt.in_port = rxq->port_id;
858 rxm->pkt.vlan_macip.f.vlan_tci = rx_status &
859 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
860 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
861 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
862 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
863 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
864 rxm->ol_flags = pkt_flags;
865 if (pkt_flags & PKT_RX_RSS_HASH)
867 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.rss);
869 rx_pkts[nb_rx++] = rxm;
871 rxq->rx_tail = rx_id;
874 * If the number of free RX descriptors is greater than the RX free
875 * threshold of the queue, advance the receive tail register of queue.
876 * Update that register with the value of the last processed RX
877 * descriptor minus 1.
879 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
880 if (nb_hold > rxq->rx_free_thresh) {
881 rx_id = (uint16_t) ((rx_id == 0) ?
882 (rxq->nb_rx_desc - 1) : (rx_id - 1));
883 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
886 rxq->nb_rx_hold = nb_hold;
892 i40e_recv_scattered_pkts(void *rx_queue,
893 struct rte_mbuf **rx_pkts,
896 struct i40e_rx_queue *rxq = rx_queue;
897 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
898 volatile union i40e_rx_desc *rxdp;
899 union i40e_rx_desc rxd;
900 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
901 struct i40e_rx_entry *rxe;
902 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
903 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
904 struct rte_mbuf *nmb, *rxm;
905 uint16_t rx_id = rxq->rx_tail;
906 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len, pkt_flags;
911 while (nb_rx < nb_pkts) {
912 rxdp = &rx_ring[rx_id];
913 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
914 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
915 I40E_RXD_QW1_STATUS_SHIFT;
916 /* Check the DD bit */
917 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
920 nmb = rte_rxmbuf_alloc(rxq->mp);
925 rxe = &sw_ring[rx_id];
927 if (rx_id == rxq->nb_rx_desc)
930 /* Prefetch next mbuf */
931 rte_prefetch0(sw_ring[rx_id].mbuf);
934 * When next RX descriptor is on a cache line boundary,
935 * prefetch the next 4 RX descriptors and next 8 pointers
938 if ((rx_id & 0x3) == 0) {
939 rte_prefetch0(&rx_ring[rx_id]);
940 rte_prefetch0(&sw_ring[rx_id]);
946 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
948 /* Set data buffer address and data length of the mbuf */
949 rxdp->read.hdr_addr = dma_addr;
950 rxdp->read.pkt_addr = dma_addr;
951 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
952 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
953 rxm->pkt.data_len = rx_packet_len;
954 rxm->pkt.data = (char *)rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
957 * If this is the first buffer of the received packet, set the
958 * pointer to the first mbuf of the packet and initialize its
959 * context. Otherwise, update the total length and the number
960 * of segments of the current scattered packet, and update the
961 * pointer to the last mbuf of the current packet.
965 first_seg->pkt.nb_segs = 1;
966 first_seg->pkt.pkt_len = rx_packet_len;
968 first_seg->pkt.pkt_len =
969 (uint16_t)(first_seg->pkt.pkt_len +
971 first_seg->pkt.nb_segs++;
972 last_seg->pkt.next = rxm;
976 * If this is not the last buffer of the received packet,
977 * update the pointer to the last mbuf of the current scattered
978 * packet and continue to parse the RX ring.
980 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
986 * This is the last buffer of the received packet. If the CRC
987 * is not stripped by the hardware:
988 * - Subtract the CRC length from the total packet length.
989 * - If the last buffer only contains the whole CRC or a part
990 * of it, free the mbuf associated to the last buffer. If part
991 * of the CRC is also contained in the previous mbuf, subtract
992 * the length of that CRC part from the data length of the
995 rxm->pkt.next = NULL;
996 if (unlikely(rxq->crc_len > 0)) {
997 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
998 if (rx_packet_len <= ETHER_CRC_LEN) {
999 rte_pktmbuf_free_seg(rxm);
1000 first_seg->pkt.nb_segs--;
1001 last_seg->pkt.data_len =
1002 (uint16_t)(last_seg->pkt.data_len -
1003 (ETHER_CRC_LEN - rx_packet_len));
1004 last_seg->pkt.next = NULL;
1006 rxm->pkt.data_len = (uint16_t)(rx_packet_len -
1010 first_seg->pkt.in_port = rxq->port_id;
1011 first_seg->pkt.vlan_macip.f.vlan_tci = (rx_status &
1012 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1013 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1014 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1015 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1016 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1017 first_seg->ol_flags = pkt_flags;
1018 if (pkt_flags & PKT_RX_RSS_HASH)
1020 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.rss);
1022 /* Prefetch data of first segment, if configured to do so. */
1023 rte_prefetch0(first_seg->pkt.data);
1024 rx_pkts[nb_rx++] = first_seg;
1028 /* Record index of the next RX descriptor to probe. */
1029 rxq->rx_tail = rx_id;
1030 rxq->pkt_first_seg = first_seg;
1031 rxq->pkt_last_seg = last_seg;
1034 * If the number of free RX descriptors is greater than the RX free
1035 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1036 * register. Update the RDT with the value of the last processed RX
1037 * descriptor minus 1, to guarantee that the RDT register is never
1038 * equal to the RDH register, which creates a "full" ring situtation
1039 * from the hardware point of view.
1041 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1042 if (nb_hold > rxq->rx_free_thresh) {
1043 rx_id = (uint16_t)(rx_id == 0 ?
1044 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1045 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1048 rxq->nb_rx_hold = nb_hold;
1053 /* Check if the context descriptor is needed for TX offloading */
1054 static inline uint16_t
1055 i40e_calc_context_desc(uint16_t flags)
1059 #ifdef RTE_LIBRTE_IEEE1588
1060 mask |= PKT_TX_IEEE1588_TMST;
1069 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1071 struct i40e_tx_queue *txq;
1072 struct i40e_tx_entry *sw_ring;
1073 struct i40e_tx_entry *txe, *txn;
1074 volatile struct i40e_tx_desc *txd;
1075 volatile struct i40e_tx_desc *txr;
1076 struct rte_mbuf *tx_pkt;
1077 struct rte_mbuf *m_seg;
1091 uint64_t buf_dma_addr;
1094 sw_ring = txq->sw_ring;
1096 tx_id = txq->tx_tail;
1097 txe = &sw_ring[tx_id];
1099 /* Check if the descriptor ring needs to be cleaned. */
1100 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1101 i40e_xmit_cleanup(txq);
1103 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1109 tx_pkt = *tx_pkts++;
1110 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1112 ol_flags = tx_pkt->ol_flags;
1113 l2_len = tx_pkt->pkt.vlan_macip.f.l2_len;
1114 l3_len = tx_pkt->pkt.vlan_macip.f.l3_len;
1116 /* Calculate the number of context descriptors needed. */
1117 nb_ctx = i40e_calc_context_desc(ol_flags);
1120 * The number of descriptors that must be allocated for
1121 * a packet equals to the number of the segments of that
1122 * packet plus 1 context descriptor if needed.
1124 nb_used = (uint16_t)(tx_pkt->pkt.nb_segs + nb_ctx);
1125 tx_last = (uint16_t)(tx_id + nb_used - 1);
1128 if (tx_last >= txq->nb_tx_desc)
1129 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1131 if (nb_used > txq->nb_tx_free) {
1132 if (i40e_xmit_cleanup(txq) != 0) {
1137 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1138 while (nb_used > txq->nb_tx_free) {
1139 if (i40e_xmit_cleanup(txq) != 0) {
1148 /* Descriptor based VLAN insertion */
1149 if (ol_flags & PKT_TX_VLAN_PKT) {
1150 tx_flags |= tx_pkt->pkt.vlan_macip.f.vlan_tci <<
1151 I40E_TX_FLAG_L2TAG1_SHIFT;
1152 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1153 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1154 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1155 I40E_TX_FLAG_L2TAG1_SHIFT;
1158 /* Always enable CRC offload insertion */
1159 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1161 /* Enable checksum offloading */
1162 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1165 if (unlikely(nb_ctx)) {
1166 /* Setup TX context descriptor if required */
1167 volatile struct i40e_tx_context_desc *ctx_txd =
1168 (volatile struct i40e_tx_context_desc *)\
1170 uint32_t cd_tunneling_params = 0;
1171 uint16_t cd_l2tag2 = 0;
1172 uint64_t cd_type_cmd_tso_mss =
1173 I40E_TX_DESC_DTYPE_CONTEXT;
1175 txn = &sw_ring[txe->next_id];
1176 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1177 if (txe->mbuf != NULL) {
1178 rte_pktmbuf_free_seg(txe->mbuf);
1181 #ifdef RTE_LIBRTE_IEEE1588
1182 if (ol_flags & PKT_TX_IEEE1588_TMST)
1183 cd_type_cmd_tso_mss |=
1184 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1185 I40E_TXD_CTX_QW1_CMD_SHIFT);
1187 ctx_txd->tunneling_params =
1188 rte_cpu_to_le_32(cd_tunneling_params);
1189 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1190 ctx_txd->type_cmd_tso_mss =
1191 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1192 txe->last_id = tx_last;
1193 tx_id = txe->next_id;
1200 txn = &sw_ring[txe->next_id];
1203 rte_pktmbuf_free_seg(txe->mbuf);
1206 /* Setup TX Descriptor */
1207 slen = m_seg->pkt.data_len;
1208 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1209 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1210 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1211 td_offset, slen, td_tag);
1212 txe->last_id = tx_last;
1213 tx_id = txe->next_id;
1215 m_seg = m_seg->pkt.next;
1216 } while (m_seg != NULL);
1218 /* The last packet data descriptor needs End Of Packet (EOP) */
1219 td_cmd |= I40E_TX_DESC_CMD_EOP;
1220 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1221 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1223 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1224 PMD_TX_FREE_LOG(DEBUG,
1225 "Setting RS bit on TXD id="
1226 "%4u (port=%d queue=%d)",
1227 tx_last, txq->port_id, txq->queue_id);
1229 td_cmd |= I40E_TX_DESC_CMD_RS;
1231 /* Update txq RS bit counters */
1232 txq->nb_tx_used = 0;
1235 txd->cmd_type_offset_bsz |=
1236 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1237 I40E_TXD_QW1_CMD_SHIFT);
1243 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1244 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1245 (unsigned) tx_id, (unsigned) nb_tx);
1247 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1248 txq->tx_tail = tx_id;
1253 static inline int __attribute__((always_inline))
1254 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1256 struct i40e_tx_entry *txep;
1259 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1260 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1263 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1265 for (i = 0; i < txq->tx_rs_thresh; i++)
1266 rte_prefetch0((txep + i)->mbuf);
1268 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1269 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1270 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1274 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1275 rte_pktmbuf_free_seg(txep->mbuf);
1280 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1281 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1282 if (txq->tx_next_dd >= txq->nb_tx_desc)
1283 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1285 return txq->tx_rs_thresh;
1288 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1289 I40E_TX_DESC_CMD_EOP)
1291 /* Populate 4 descriptors with data from 4 mbufs */
1293 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1298 for (i = 0; i < 4; i++, txdp++, pkts++) {
1299 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1300 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1301 txdp->cmd_type_offset_bsz =
1302 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1303 (*pkts)->pkt.data_len, 0);
1307 /* Populate 1 descriptor with data from 1 mbuf */
1309 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1313 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1314 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1315 txdp->cmd_type_offset_bsz =
1316 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1317 (*pkts)->pkt.data_len, 0);
1320 /* Fill hardware descriptor ring with mbuf data */
1322 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1323 struct rte_mbuf **pkts,
1326 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1327 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1328 const int N_PER_LOOP = 4;
1329 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1330 int mainpart, leftover;
1333 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1334 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1335 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1336 for (j = 0; j < N_PER_LOOP; ++j) {
1337 (txep + i + j)->mbuf = *(pkts + i + j);
1339 tx4(txdp + i, pkts + i);
1341 if (unlikely(leftover > 0)) {
1342 for (i = 0; i < leftover; ++i) {
1343 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1344 tx1(txdp + mainpart + i, pkts + mainpart + i);
1349 static inline uint16_t
1350 tx_xmit_pkts(struct i40e_tx_queue *txq,
1351 struct rte_mbuf **tx_pkts,
1354 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1358 * Begin scanning the H/W ring for done descriptors when the number
1359 * of available descriptors drops below tx_free_thresh. For each done
1360 * descriptor, free the associated buffer.
1362 if (txq->nb_tx_free < txq->tx_free_thresh)
1363 i40e_tx_free_bufs(txq);
1365 /* Use available descriptor only */
1366 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1367 if (unlikely(!nb_pkts))
1370 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1371 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1372 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1373 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1374 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1375 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1376 I40E_TXD_QW1_CMD_SHIFT);
1377 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1381 /* Fill hardware descriptor ring with mbuf data */
1382 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1383 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1385 /* Determin if RS bit needs to be set */
1386 if (txq->tx_tail > txq->tx_next_rs) {
1387 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1388 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1389 I40E_TXD_QW1_CMD_SHIFT);
1391 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1392 if (txq->tx_next_rs >= txq->nb_tx_desc)
1393 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1396 if (txq->tx_tail >= txq->nb_tx_desc)
1399 /* Update the tx tail register */
1401 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1407 i40e_xmit_pkts_simple(void *tx_queue,
1408 struct rte_mbuf **tx_pkts,
1413 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1414 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1418 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1421 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1422 &tx_pkts[nb_tx], num);
1423 nb_tx = (uint16_t)(nb_tx + ret);
1424 nb_pkts = (uint16_t)(nb_pkts - ret);
1433 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1436 unsigned int socket_id,
1437 const struct rte_eth_rxconf *rx_conf,
1438 struct rte_mempool *mp)
1440 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1441 struct i40e_rx_queue *rxq;
1442 const struct rte_memzone *rz;
1445 int use_def_burst_func = 1;
1447 if (!vsi || queue_idx >= vsi->nb_qps) {
1448 PMD_DRV_LOG(ERR, "VSI not available or queue "
1449 "index exceeds the maximum\n");
1450 return I40E_ERR_PARAM;
1452 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1453 (nb_desc > I40E_MAX_RING_DESC) ||
1454 (nb_desc < I40E_MIN_RING_DESC)) {
1455 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1456 "invalid\n", nb_desc);
1457 return I40E_ERR_PARAM;
1460 /* Free memory if needed */
1461 if (dev->data->rx_queues[queue_idx]) {
1462 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1463 dev->data->rx_queues[queue_idx] = NULL;
1466 /* Allocate the rx queue data structure */
1467 rxq = rte_zmalloc_socket("i40e rx queue",
1468 sizeof(struct i40e_rx_queue),
1472 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1473 "rx queue data structure\n");
1477 rxq->nb_rx_desc = nb_desc;
1478 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1479 rxq->queue_id = queue_idx;
1480 rxq->reg_idx = vsi->base_queue + queue_idx;
1481 rxq->port_id = dev->data->port_id;
1482 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1484 rxq->drop_en = rx_conf->rx_drop_en;
1487 /* Allocate the maximun number of RX ring hardware descriptor. */
1488 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1489 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1490 rz = i40e_ring_dma_zone_reserve(dev,
1496 i40e_dev_rx_queue_release(rxq);
1497 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX\n");
1501 /* Zero all the descriptors in the ring. */
1502 memset(rz->addr, 0, ring_size);
1504 #ifdef RTE_LIBRTE_XEN_DOM0
1505 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1507 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1510 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1512 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1513 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1518 /* Allocate the software ring. */
1520 rte_zmalloc_socket("i40e rx sw ring",
1521 sizeof(struct i40e_rx_entry) * len,
1524 if (!rxq->sw_ring) {
1525 i40e_dev_rx_queue_release(rxq);
1526 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring\n");
1530 i40e_reset_rx_queue(rxq);
1532 dev->data->rx_queues[queue_idx] = rxq;
1534 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1536 if (!use_def_burst_func && !dev->data->scattered_rx) {
1537 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1538 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1539 "satisfied. Rx Burst Bulk Alloc function will be "
1540 "used on port=%d, queue=%d.\n",
1541 rxq->port_id, rxq->queue_id);
1542 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1543 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1545 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1546 "not satisfied, Scattered Rx is requested, "
1547 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1548 "not enabled on port=%d, queue=%d.\n",
1549 rxq->port_id, rxq->queue_id);
1556 i40e_dev_rx_queue_release(void *rxq)
1558 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1561 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL\n");
1565 i40e_rx_queue_release_mbufs(q);
1566 rte_free(q->sw_ring);
1571 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1573 #define I40E_RXQ_SCAN_INTERVAL 4
1574 volatile union i40e_rx_desc *rxdp;
1575 struct i40e_rx_queue *rxq;
1578 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1579 PMD_DRV_LOG(ERR, "Invalid RX queue id %u\n", rx_queue_id);
1583 rxq = dev->data->rx_queues[rx_queue_id];
1584 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1585 while ((desc < rxq->nb_rx_desc) &&
1586 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1587 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1588 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1590 * Check the DD bit of a rx descriptor of each 4 in a group,
1591 * to avoid checking too frequently and downgrading performance
1594 desc += I40E_RXQ_SCAN_INTERVAL;
1595 rxdp += I40E_RXQ_SCAN_INTERVAL;
1596 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1597 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1598 desc - rxq->nb_rx_desc]);
1605 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1607 volatile union i40e_rx_desc *rxdp;
1608 struct i40e_rx_queue *rxq = rx_queue;
1612 if (unlikely(offset >= rxq->nb_rx_desc)) {
1613 PMD_DRV_LOG(ERR, "Invalid RX queue id %u\n", offset);
1617 desc = rxq->rx_tail + offset;
1618 if (desc >= rxq->nb_rx_desc)
1619 desc -= rxq->nb_rx_desc;
1621 rxdp = &(rxq->rx_ring[desc]);
1623 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1624 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1625 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1631 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1634 unsigned int socket_id,
1635 const struct rte_eth_txconf *tx_conf)
1637 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1638 struct i40e_tx_queue *txq;
1639 const struct rte_memzone *tz;
1641 uint16_t tx_rs_thresh, tx_free_thresh;
1643 if (!vsi || queue_idx >= vsi->nb_qps) {
1644 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1645 "exceeds the maximum\n", queue_idx);
1646 return I40E_ERR_PARAM;
1649 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1650 (nb_desc > I40E_MAX_RING_DESC) ||
1651 (nb_desc < I40E_MIN_RING_DESC)) {
1652 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1653 "invalid\n", nb_desc);
1654 return I40E_ERR_PARAM;
1658 * The following two parameters control the setting of the RS bit on
1659 * transmit descriptors. TX descriptors will have their RS bit set
1660 * after txq->tx_rs_thresh descriptors have been used. The TX
1661 * descriptor ring will be cleaned after txq->tx_free_thresh
1662 * descriptors are used or if the number of descriptors required to
1663 * transmit a packet is greater than the number of free TX descriptors.
1665 * The following constraints must be satisfied:
1666 * - tx_rs_thresh must be greater than 0.
1667 * - tx_rs_thresh must be less than the size of the ring minus 2.
1668 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1669 * - tx_rs_thresh must be a divisor of the ring size.
1670 * - tx_free_thresh must be greater than 0.
1671 * - tx_free_thresh must be less than the size of the ring minus 3.
1673 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1674 * race condition, hence the maximum threshold constraints. When set
1675 * to zero use default values.
1677 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1678 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1679 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1680 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1681 if (tx_rs_thresh >= (nb_desc - 2)) {
1682 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1683 "number of TX descriptors minus 2. "
1684 "(tx_rs_thresh=%u port=%d queue=%d)\n",
1685 (unsigned int)tx_rs_thresh,
1686 (int)dev->data->port_id,
1688 return I40E_ERR_PARAM;
1690 if (tx_free_thresh >= (nb_desc - 3)) {
1691 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1692 "tx_free_thresh must be less than the "
1693 "number of TX descriptors minus 3. "
1694 "(tx_free_thresh=%u port=%d queue=%d)\n",
1695 (unsigned int)tx_free_thresh,
1696 (int)dev->data->port_id,
1698 return I40E_ERR_PARAM;
1700 if (tx_rs_thresh > tx_free_thresh) {
1701 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or "
1702 "equal to tx_free_thresh. (tx_free_thresh=%u"
1703 " tx_rs_thresh=%u port=%d queue=%d)\n",
1704 (unsigned int)tx_free_thresh,
1705 (unsigned int)tx_rs_thresh,
1706 (int)dev->data->port_id,
1708 return I40E_ERR_PARAM;
1710 if ((nb_desc % tx_rs_thresh) != 0) {
1711 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1712 "number of TX descriptors. (tx_rs_thresh=%u"
1713 " port=%d queue=%d)\n",
1714 (unsigned int)tx_rs_thresh,
1715 (int)dev->data->port_id,
1717 return I40E_ERR_PARAM;
1719 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1720 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1721 "tx_rs_thresh is greater than 1. "
1722 "(tx_rs_thresh=%u port=%d queue=%d)\n",
1723 (unsigned int)tx_rs_thresh,
1724 (int)dev->data->port_id,
1726 return I40E_ERR_PARAM;
1729 /* Free memory if needed. */
1730 if (dev->data->tx_queues[queue_idx]) {
1731 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1732 dev->data->tx_queues[queue_idx] = NULL;
1735 /* Allocate the TX queue data structure. */
1736 txq = rte_zmalloc_socket("i40e tx queue",
1737 sizeof(struct i40e_tx_queue),
1741 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1742 "tx queue structure\n");
1746 /* Allocate TX hardware ring descriptors. */
1747 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1748 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1749 tz = i40e_ring_dma_zone_reserve(dev,
1755 i40e_dev_tx_queue_release(txq);
1756 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX\n");
1760 txq->nb_tx_desc = nb_desc;
1761 txq->tx_rs_thresh = tx_rs_thresh;
1762 txq->tx_free_thresh = tx_free_thresh;
1763 txq->pthresh = tx_conf->tx_thresh.pthresh;
1764 txq->hthresh = tx_conf->tx_thresh.hthresh;
1765 txq->wthresh = tx_conf->tx_thresh.wthresh;
1766 txq->queue_id = queue_idx;
1767 txq->reg_idx = vsi->base_queue + queue_idx;
1768 txq->port_id = dev->data->port_id;
1769 txq->txq_flags = tx_conf->txq_flags;
1772 #ifdef RTE_LIBRTE_XEN_DOM0
1773 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1775 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
1777 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
1779 /* Allocate software ring */
1781 rte_zmalloc_socket("i40e tx sw ring",
1782 sizeof(struct i40e_tx_entry) * nb_desc,
1785 if (!txq->sw_ring) {
1786 i40e_dev_tx_queue_release(txq);
1787 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring\n");
1791 i40e_reset_tx_queue(txq);
1793 dev->data->tx_queues[queue_idx] = txq;
1795 /* Use a simple TX queue without offloads or multi segs if possible */
1796 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
1797 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
1798 PMD_INIT_LOG(INFO, "Using simple tx path\n");
1799 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
1801 PMD_INIT_LOG(INFO, "Using full-featured tx path\n");
1802 dev->tx_pkt_burst = i40e_xmit_pkts;
1809 i40e_dev_tx_queue_release(void *txq)
1811 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
1814 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL\n");
1818 i40e_tx_queue_release_mbufs(q);
1819 rte_free(q->sw_ring);
1823 static const struct rte_memzone *
1824 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
1825 const char *ring_name,
1830 char z_name[RTE_MEMZONE_NAMESIZE];
1831 const struct rte_memzone *mz;
1833 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1834 dev->driver->pci_drv.name, ring_name,
1835 dev->data->port_id, queue_id);
1836 mz = rte_memzone_lookup(z_name);
1840 #ifdef RTE_LIBRTE_XEN_DOM0
1841 return rte_memzone_reserve_bounded(z_name, ring_size,
1842 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
1844 return rte_memzone_reserve_aligned(z_name, ring_size,
1845 socket_id, 0, I40E_ALIGN);
1850 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
1854 if (!rxq || !rxq->sw_ring) {
1855 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL\n");
1859 for (i = 0; i < rxq->nb_rx_desc; i++) {
1860 if (rxq->sw_ring[i].mbuf) {
1861 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1862 rxq->sw_ring[i].mbuf = NULL;
1865 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1866 if (rxq->rx_nb_avail == 0)
1868 for (i = 0; i < rxq->rx_nb_avail; i++) {
1869 struct rte_mbuf *mbuf;
1871 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
1872 rte_pktmbuf_free_seg(mbuf);
1874 rxq->rx_nb_avail = 0;
1875 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1879 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
1884 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1885 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
1886 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
1888 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1889 len = rxq->nb_rx_desc;
1891 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
1892 ((volatile char *)rxq->rx_ring)[i] = 0;
1894 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1895 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
1896 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
1897 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
1899 rxq->rx_nb_avail = 0;
1900 rxq->rx_next_avail = 0;
1901 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1902 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1904 rxq->nb_rx_hold = 0;
1905 rxq->pkt_first_seg = NULL;
1906 rxq->pkt_last_seg = NULL;
1910 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
1914 if (!txq || !txq->sw_ring) {
1915 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL\n");
1919 for (i = 0; i < txq->nb_tx_desc; i++) {
1920 if (txq->sw_ring[i].mbuf) {
1921 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1922 txq->sw_ring[i].mbuf = NULL;
1928 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
1930 struct i40e_tx_entry *txe;
1931 uint16_t i, prev, size;
1934 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL\n");
1939 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
1940 for (i = 0; i < size; i++)
1941 ((volatile char *)txq->tx_ring)[i] = 0;
1943 prev = (uint16_t)(txq->nb_tx_desc - 1);
1944 for (i = 0; i < txq->nb_tx_desc; i++) {
1945 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
1947 txd[i].cmd_type_offset_bsz =
1948 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
1951 txe[prev].next_id = i;
1955 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1956 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1959 txq->nb_tx_used = 0;
1961 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1962 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1965 /* Init the TX queue in hardware */
1967 i40e_tx_queue_init(struct i40e_tx_queue *txq)
1969 enum i40e_status_code err = I40E_SUCCESS;
1970 struct i40e_vsi *vsi = txq->vsi;
1971 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1972 uint16_t pf_q = txq->reg_idx;
1973 struct i40e_hmc_obj_txq tx_ctx;
1976 /* clear the context structure first */
1977 memset(&tx_ctx, 0, sizeof(tx_ctx));
1978 tx_ctx.new_context = 1;
1979 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
1980 tx_ctx.qlen = txq->nb_tx_desc;
1981 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
1983 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
1984 if (err != I40E_SUCCESS) {
1985 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context\n");
1989 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
1990 if (err != I40E_SUCCESS) {
1991 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context\n");
1995 /* Now associate this queue with this PCI function */
1996 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
1997 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
1998 I40E_QTX_CTL_PF_INDX_MASK);
1999 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2000 I40E_WRITE_FLUSH(hw);
2002 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2008 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2010 struct i40e_rx_entry *rxe = rxq->sw_ring;
2014 for (i = 0; i < rxq->nb_rx_desc; i++) {
2015 volatile union i40e_rx_desc *rxd;
2016 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2018 if (unlikely(!mbuf)) {
2019 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX\n");
2023 rte_mbuf_refcnt_set(mbuf, 1);
2024 mbuf->type = RTE_MBUF_PKT;
2025 mbuf->pkt.next = NULL;
2026 mbuf->pkt.data = (char *)mbuf->buf_addr + RTE_PKTMBUF_HEADROOM;
2027 mbuf->pkt.nb_segs = 1;
2028 mbuf->pkt.in_port = rxq->port_id;
2031 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2033 rxd = &rxq->rx_ring[i];
2034 rxd->read.pkt_addr = dma_addr;
2035 rxd->read.hdr_addr = dma_addr;
2036 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2037 rxd->read.rsvd1 = 0;
2038 rxd->read.rsvd2 = 0;
2039 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2048 * Calculate the buffer length, and check the jumbo frame
2049 * and maximum packet length.
2052 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2054 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2055 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2056 struct rte_eth_dev_data *data = pf->dev_data;
2057 struct rte_pktmbuf_pool_private *mbp_priv =
2058 rte_mempool_get_priv(rxq->mp);
2059 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2060 RTE_PKTMBUF_HEADROOM);
2063 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2064 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2065 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2066 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2067 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2068 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2069 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2070 rxq->hs_mode = i40e_header_split_enabled;
2072 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2074 rxq->rx_hdr_len = 0;
2075 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2076 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2077 rxq->hs_mode = i40e_header_split_none;
2081 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2082 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2083 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2084 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2085 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2086 PMD_DRV_LOG(ERR, "maximum packet length must "
2087 "be larger than %u and smaller than %u,"
2088 "as jumbo frame is enabled\n",
2089 (uint32_t)ETHER_MAX_LEN,
2090 (uint32_t)I40E_FRAME_SIZE_MAX);
2091 return I40E_ERR_CONFIG;
2094 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2095 rxq->max_pkt_len > ETHER_MAX_LEN) {
2096 PMD_DRV_LOG(ERR, "maximum packet length must be "
2097 "larger than %u and smaller than %u, "
2098 "as jumbo frame is disabled\n",
2099 (uint32_t)ETHER_MIN_LEN,
2100 (uint32_t)ETHER_MAX_LEN);
2101 return I40E_ERR_CONFIG;
2108 /* Init the RX queue in hardware */
2110 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2112 int err = I40E_SUCCESS;
2113 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2114 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2115 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2116 uint16_t pf_q = rxq->reg_idx;
2118 struct i40e_hmc_obj_rxq rx_ctx;
2119 struct rte_pktmbuf_pool_private *mbp_priv;
2121 err = i40e_rx_queue_config(rxq);
2123 PMD_DRV_LOG(ERR, "Failed to config RX queue\n");
2127 /* Clear the context structure first */
2128 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2129 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2130 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2132 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2133 rx_ctx.qlen = rxq->nb_rx_desc;
2134 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2137 rx_ctx.dtype = rxq->hs_mode;
2139 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2141 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2142 rx_ctx.rxmax = rxq->max_pkt_len;
2143 rx_ctx.tphrdesc_ena = 1;
2144 rx_ctx.tphwdesc_ena = 1;
2145 rx_ctx.tphdata_ena = 1;
2146 rx_ctx.tphhead_ena = 1;
2147 rx_ctx.lrxqthresh = 2;
2148 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2153 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2154 if (err != I40E_SUCCESS) {
2155 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context\n");
2158 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2159 if (err != I40E_SUCCESS) {
2160 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context\n");
2164 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2165 err = i40e_alloc_rx_queue_mbufs(rxq);
2166 mbp_priv = rte_mempool_get_priv(rxq->mp);
2167 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2168 RTE_PKTMBUF_HEADROOM);
2170 /* Check if scattered RX needs to be used. */
2171 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2172 dev_data->scattered_rx = 1;
2173 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2178 /* Init the RX tail regieter. */
2179 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
2180 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2183 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf\n");
2189 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2193 PMD_INIT_FUNC_TRACE();
2195 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2196 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2197 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2200 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2201 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2202 i40e_reset_rx_queue(dev->data->rx_queues[i]);